Implementation of a FIR Filter on a Partial Reconfigurable Platform

Transcription

1 Implementation of a FIR Filter on a Partial Reconfigurable Platform Hanho Lee and Chang-Seok Choi School of Information and Communication Engineering Inha University, Incheon, , Korea hhlee@inha.ac.kr Abstract. This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method. 1 Introduction The possibility to perform dynamic partial hardware reconfiguration of FPGAs increases their flexibility and ability of run-time adaptation. This feature is provided by Xilinx Virtex II FPGAs, which can be dynamically reprogrammed using the so called ICAP interface. FPGAs provide an array of logic cells that can be configured to perform a given functionality by means of a configuration bitstream. Many of FPGA systems can only be statically configured. Static reconfiguration means to completely configure the device before system execution. If a new reconfiguration is required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial reconfiguration, where a reduced bitstream reconfigures only a given subset of internal components. Dynamic Partial Reconfiguration (DPR) allows the part of FPGA device be modified while the rest of the device (or system) continues to operate and unaffected by the reprogramming [1]. This paper presents a partially reconfigurable FIR filter design that targets to meet all the objectives(low-power consumption, autonomous adaptability/reconfigurability, fault-tolerance, etc.) on the FPGA. The FIR filters are special kind of digital filters and have a wide applicability because it has a good characteristic such as linear phase and stability. They are employed in the majority digital signal processing (DSP) based electronic systems. The emergence of demanding applications (image, audio/video processing and coding, sensor filtering, etc.) in terms of power, speed, performance, system compatibility and reusability make it imperative to design the reconfigurable architectures. However, FIR filters may need a large number of coefficients to obtain B. Gabrys, R.J. Howlett, and L.C. Jain (Eds.): KES 2006, Part III, LNAI 4253, pp , Springer-Verlag Berlin Heidelberg 2006

2 Implementation of a FIR Filter on a Partial Reconfigurable Platform 109 Fig. 1. Design layout with two reconfigurable modules [3] the desired specification. This results in the large number of area (slice) for FPGA design. Therefore, there are certain disadvantages associated with run-time reconfigurable design of higher order tap FIR filters using conventional FPGA design techniques. One of the major disadvantages is the so called reconfigurable overhead, which is the time spent for reconfiguration. This depends on the reconfigurable device and the method of reconfiguration. The partial reconfiguration technique can be used in this case since the various taps FIR filters have so many similarities in their structure. Therefore, partial reconfiguration addresses the reduced reconfiguration overhead, coefficient flexibility and area efficiency for higher order FIR filters. 2 Module-Based Partial Reconfiguration Module-based partial reconfiguration was proposed by Xilinx [3][4]. And now many researchers have been proposed many partial reconfiguration methods (JBits, PARBIT, etc) [1][2]. But these methods are difficult to apply real applications because these methods reconfigure the gate-level based. However module-based partial reconfiguration technique can reconfigure the system-level based. The modular design flow allows the designer to split the whole system into modules. For each module, the designer generates a configuration bitstream starting from an HDL description and going through the synthesis, mapping, placement, and routing procedures, independently of other modules [3]. The modular design flow consists of Modular Design Entry/Synthesis and Modular Design Implementation steps. Modular Design Entry/Synthesis step must be done for top-level design and the modules. Top-level design is designed by the team leader and consists of black box for each sub-modules and wiring for interconnection of each sub-modules. Modular Design Implementation step comprises following three phase: 1) Initial budget phase, 2) Active module implementation, 3) Final assembly. Module-based partial reconfiguration method is a special case of modular design [3]. This method can

3 110 H. Lee and C.-S. Choi Fig. 2. n-tap symmetric transposed FIR filter (a) (b) Fig. 3. Block diagram of (a) partial reconfigurable m n order FIR filter, (b) reconfigurable multiply-accummulate (rmac) modules reconfigure only a given subset of internal components during device is activating. A complete initial bitstreams are generated for each reconfigurable module. Fig.1 shows the design layout using partial reconfigurable module. Hardwired bus macros must be included in design for guarantee that each time partial reconfiguration is performed routing channels between modules remain unchanged, avoiding contentions inside the FPGA and keeping correct inter-module connections.

4 Implementation of a FIR Filter on a Partial Reconfigurable Platform Reconfigurable FIR Filter Design The FIR filter computes an output from a set of input samples. The set of input samples is multiplied by a set of coefficients and then added together to produce the output as shown in Fig. 2. Implementation of FIR filters can be undertaken in either hardware or software [5]. A software implementation will require sequential execution of the filter functions. Hardware implementation of FIR filters allows the filter functions to be executed in a parallel manner, which makes improved filter processing speed possible but is less flexible for changes. Thus, reconfigurable FIR filter offers both the flexibility of computer software, and the ability to construct custom high performance computing circuits. Fig. 3 shows the partial reconfigurable m n order FIR filter, which consists of m n order filter modules and right side module. These FIR filter is consisted of m filter modules, which connected by bus macros on FPGA. And each filter module consists of n/2 reconfigurable multiply-accumulate (rmac) unit, which includes the serial-toparallel register to get coefficient inputs in serial. 4 Implementation On adaptive systems, a limiting factor for the overall system performance is often the speed of which the system is able to adapt to perform a certain task. This section describes the implementation method of 20-tap FIR filter, which is reconfigured partially from 12-tap FIR filter. The whole system is implemented on a Xilinx Virtex2p30 FPGA device [6]. 4.1 HDL Coding and Synthesis This step is composed to following two phase: G Top module design: In this phase, designer must consider each sub-module interconnection, area assignment and bus macro assignment. G Reconfigurable sub-module design: This phase is same to traditional HDL design method. But designer must consider input and output assign rule for partial reconfiguration. 4.2 Module-Based Design G Initial Budget: In this phase, the team leader assigns top-level constraints to the top-level design. Toplevel constraint needs to area constraint and bus-macro assignment. This step is as sequence of top module design. In this step, designer must do bus macro manual setting, sub module area constraint by using floorplanner and top module IOB assignment. Bus macro is limited by target size. Through equation (1), designer can estimate maximum usable bus macro. MaxBus = 4 * rowclb (1)

5 112 H. Lee and C.-S. Choi (a) (b) Fig. 4. PAR map of (a) 12-tap and (b)20-tap FIR filter using DPR If designer needs area optimization, optimized area can be estimated in a synthesis step. An optimized width equation is described by slice x = + 1 (2) 4* row where slice is a maximum slice number estimated in a synthesis step and row is a target row size. G Active module implementation: In this phase, the team members implement the reconfigurable modules. That is, partially reconfigurable sub-modules are generated by top module and.ucf file. Each sub-module generates a partial bitstream during this step. Fig. 4 shows a post-par (placement and routing) diagram. Through n order filter module1 is reconfigured to bypass module and module2 is reconfigured to 4-tap module on 12-tap FIR filter while other module is processing, 20-tap FIR filter is composed by partial reconfiguration of module1 showing Fig. 4 (b). G Final module assemble: In the phase, the team leader assembles and implements the top-level design using each sub-modules and generates top-module bitstream. That is, designer assembles on system from partially generated modules. All partial modules generated in active module implementation step are combined to the top-level module. 5 Experiment and Result The partial reconfiguration of symmetric transposed FIR filters was implemented on Xilinx Virtex-II FPGA device using test environment shown in Fig. 5 [7]-[9]. XUPV2P FPGA test board and Agilent logic analyzer were used for board level verification. And configuration bitstream download is operated by Xilinx Platform Cable USB and IMPACT. For dynamic partial reconfiguration experiment, the partial reconfigurable module1 and module2 were reconfigured to bypass module and 4-tap two rmac modules respectively while other areas of modules remain operational. For

6 Implementation of a FIR Filter on a Partial Reconfigurable Platform 113 Fig. 5. Test Environment. verification, we have performed following two methods. First, 12-tap and 20-tap FIR filters before/after partial reconfiguration have been simulated to verify the output results on FPGA test board using Xilinx ChipScope Pro Analyzer. Second, each module has been assigned by identification number such as bypass=00, 2-tap=01, 4- tap=10, 6-tap=11, and then during the partial reconfiguration process the waveform of logic analyzer shows the change of identification number to verify the partial reconfiguration of FIR filter. Fig. 6 shows the board test result to verify the partial reconfiguration and measure the configuration time. Fig. 6(a) shows the board test result for FIR filter using DPR technique. Because most of modules are operating except reconfigured module, module identification number is changed continuously. After completing DPR, the waveform shows the output change from 3D(111101) to 31(110001). This result (a) (b) Fig. 6. Board test result of (a) partial reconfiguration, and (b) full reconfiguration

7 114 H. Lee and C.-S. Choi shows that module2 is reconfigured partially from 6-tap three rmac modules to bypass module. And measured reconfiguration time shows about ms. Otherwise, Fig. 6(b) shows the board test result in which the full reconfiguration is processed after FPGA reset. Measure reconfiguration time is about 3.05 s. Thus the reconfiguration time of DPR FIR filter is reduced about 1/30 compared to full reconfiguration of FIR filter. Table 1. FPGA device utilization for several FIR filters GF MBF DPR Slice 3,058 5,349 4,733 LUT 5,980 9,669 8,427 Equivalent Gate N/A 76,024 68,063 GF: General Symmetric FIR Filter MBF: Multiplexer Based Reconfigurable FIR Filter DPR: Reconfigurable symmetric transposed FIR filter using DPR EG: Equivalent Gate Count For performance comparison, we have implemented general symmetric FIR filter (GF) using variable multipliers, multiplexer based reconfigurable FIR filter (MBF) and reconfigurable symmetric transposed FIR filter using DPR (DPR). Table 1 shows the utilization of slice, LUT and equivalent gate count after technology mapping. The reconfigurable FIR filter using DPR can save about 11.5% slice compared to the multiplexer based reconfigurable FIR filter, which can be reconfigured to various FIR filter using multiplexer. Compared to the general symmetric FIR filter (GF), the slice number in reconfigurable FIR filter using DPR method was increased about 54% because of adding bus macro, serial-to-parallel register and a little controller. But if we want to change 2, 4, 6-tap rmac modules in general symmetric FIR filter, the full reconfiguration must be needed and required long reconfiguration time. However, reconfigurable FIR filter using DPR method requires the partial reconfiguration of about 1,461 slices out of total 4,733 slices for 2-tap one rmac module or 6-tap three rmac module, which adds flexibility allowing dynamically inserting and/or removing the coefficient taps. 6 Conclusion This paper discusses a partial reconfigurable FIR filter design approach using dynamic partial reconfiguration. This approach has area efficiency, flexibility and fast configuration time allowing dynamically inserting and/or removing the part of modules. The proposed reconfigurable FIR filter design method produces a reduction in hardware cost compared to multiplexer-based reconfigurable FIR filter and allows performing fast partial reconfiguration, where a reduced bitstream reconfigures only a given subset of internal components. In the future, self-reconfigurable hardware

8 Implementation of a FIR Filter on a Partial Reconfigurable Platform 115 platform using microcontroller unit and configuration memory will be promising solution for automatic partial reconfiguration of digital circuit in the run-time environment. Acknowledgement This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program. References [1] D. Mesquita, F. Moraes, J. Palma, L. Moller, N. Calazanas, Remote and Partial Reconfiguration of FPGAs: tools and trends, International Parallel and Distributed Processing Symposium, April [2] A. K. Raghavan, P. Sutton, JPG-A partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs, Proc. of the International Parallel and Distributed Processing Symposium, [3] Xilinx Inc., XAPP 290: Two flows for Partial Reconfiguration: Module Based or Difference Based, Sept [4] Xilinx Inc., Development System Reference Guide, [5] Uwe Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, [6] Hyuk Kim, Real Xilinx FPGA World, Ant Media, Oct [7] Xilinx Inc., Virtex configuration architecture advanced user s guide, Oct [8] Philippe Brutel, Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs, Xcell Journal, Xilinx, Fall [9] Xilinx Inc., Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual, March 2005.