CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline
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1 CPE/EE 422/522 Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices Dr. Rhonda Kay Gaede UAH Outline Introduction Field-Programmable Gate Arrays Virtex Virtex-E, Virtex-II, and Virtex-II Pro Page 2 of 30 1
2 The World of Application Specific Integrated Circuit Design Application Specific Integrated Circuit Design Custom Mask-Programmable User Programmable Page 3 of 30 Selecting a Technology High Development Costs Non-Recurring- Engineering Cost Power Consumption Low Cost (High Volume) High Performance Low Development Costs No Non-Recurring- Engineering Cost Reconfigurable Higher Cost Pretty Good Performance Custom Programmable Page 4 of 30 2
3 What is an FPGA? Reconfigurable Black-Box Hardware Page 5 of 30 What are FPGAs made of? FPGA: Field-Programmable Gate Arrays Basic blocks of logic function (CLBs) Programmable input/output blocks (IOBs) Programmable interconnections Embedded memory (brams) Type of interconnections network Anti-fuse SRAM Page 6 of 30 3
4 Basic Layout of an FPGA Input/Output Blocks Logic Basic Blocks Embedded Memory Page 7 of 30 Xilinx Virtex 2.5V FPGA (1) Densities from 50k to 1M system gates System performance up to 200 MHz Four dedicated delay-locked loops (DLLs) for advanced clock control Dedicated carry logic for high-speed arithmetic Look-up-table based architecture IEEE boundary-scan logic SRAM-based in-system configurable Unlimited re-programmability 0.22 µm 5-layer metal process Number of user I/O pins range from 94 to 512 Page 8 of 30 4
5 Xilinx Virtex 2.5V FPGA (2) Page 9 of 30 Xilinx Virtex 2.5V FPGA (3) Page 10 of 30 5
6 CLB: Configurable Logic Block (1) The Logic Cell (LC) is the basic building block of the Virtex CLB LC includes 4-input function generator carry logic storage element CLB = 4 LCs Page 11 of 30 Virtex Slice Page 12 of 30 6
7 LUT: Look Up Table Basic building blocks of a logic function Virtex contains 4-input LUT Capacity limited by number of input Configures as LUT, ROM, and RAM X 1 X 2 X 3 X 4 LUT Z Example: Z = X 1 X 2 + X 3 + X 4 X 1 X 2 X 3 X 4 Z Page 13 of 30 IOB: Input/Output Block Interface between pins and CLBs Supports wide variety of I/O signalling standards Page 14 of 30 7
8 Input Page 15 of 30 Output Page 16 of 30 8
9 Compatible Output Standards Page 17 of 30 Embedded Memory Two Types Block RAM Block SelectRAM Page 18 of 30 9
10 Programmable Routing Matrix (1) Quality of routing controls the speed of a design Local Routing: CLB feedback paths Chains horizontal CLBs together Page 19 of 30 Programmable Routing Matrix (2) General Routing General Routing Matrix (GRM) Horizontal and vertical routing resources 24 single-length lines in each of the four directions 12 longlines (horizontal and vertical) VersaRing: interface between the CLBs and IOBs pinswapping and pin-locking Global Routing: 4 dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew Delay-Locked Loop: eliminate skew between the clock input pad and internal clock-input pins throughout the device Page 20 of 30 10
11 Programmable Routing Matrix (3) Page 21 of 30? Direction of Technology Page 22 of 30 11
12 Device Release Dates Virtex, November 1998 Virtex-E, December 1999 Virtex-II, November 2000 Virtex-II Pro, January 2002 Page 23 of 30 Virtex-E Page 24 of 30 12
13 Virtex-E Page 25 of 30 Virtex-II Page 26 of 30 13
14 Virtex-II Page 27 of 30 Virtex-II Pro Page 28 of 30 14
15 Virtex-II Pro Page 29 of 30 Problems and Challenges How to best utilize this pre-fabricated reconfigurable black-box? Page 30 of 30 15
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