CPE/EE 421 Microcomputers
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1 CPE/EE 421 Microcomputers Instructor: Dr Aleksandar Milenkovic Lecture Note S09 *Material used is in part developed by Dr. D. Raskovic and Dr. E. Jovanov CPE/EE 421/521 Microcomputers 1 Performance Outline MSP430: An Introduction CPE/EE 421/521 Microcomputers 2 Alex Milenkovich 1
2 Speed and Performance of Microprocessors Why is difficult to compare the speed of two microprocessors? 1. Clock speed 2. Meaningless MIPS 3. Memory access times 4. Are registers used optimally? 5. Special addressing modes (not generally useful) 6. Misleading benchmarks 7. Use of cache 8. Pipeline Carefully interpret benchmarks! Clock Cycles/Bus Cycles CPE/EE 421/521 Microcomputers 3 Speed and Performance of Microprocessors, cont d Example: Interpret the high-level language construct IF COUNT[CLASS[I]] <> 0 THEN Version Version Clock Bus Clock Bus Cycles Cycles Cycles Cycles Code MOVE.W D1,D LSL.W #1,D LEA 0(A5,D3.W),A MOVE.W CLASS(A2),D LSL.W #1,D LEA 0(A5,D3.W),A TST.W COUNT(A2) BEQ ELSE CPE/EE 421/521 Microcomputers 4 Alex Milenkovich 2
3 Speed and Performance of Microprocessors, cont d MIPS = Million Instructions Per Second For the previous example, 68000: Execution time = 6.32 µs => 8 instructions / 6.32 µs = 1.27 MIPS using the same code Execution time = 2.52 µs => 8 instructions / 2.52 µs = 3.17 MIPS using special features Execution time = 1.44 µs => 3 instructions / 1.44 µs = 2.08 MIPS MOVE.W (CLASS,A5,D1.W*2),D3 TST.W (COUNT,A5,D3.W*2) BEQ ELSE CPE/EE 421/521 Microcomputers 5 Example For the given assembly language program: LEA TABLE,A0 CLR.W D1 LOOP MOVE.B D0,(A0)+ ADDQ.W #1,D1 CMPI.W #9,D1 BNE LOOP a) Find the total execution time of the given program on a 12.5 MHz microprocessor. b) What is the average CPI (number of clocks per instructions)? c) What is the MIPS rate? CPE/EE 421/521 Microcomputers 6 Alex Milenkovich 3
4 #of cycles LEA TABLE,A0 8 CLR.W D1 4 LOOP MOVE.B D0,(A0)+ 8 ADDQ.W #1,D1 4 CMPI.W #9,D1 8 BNE LOOP 10(taken)/8 Singe execution Loop (9 iterations) a) Find the total execution time of the given program on a 12.5 MHz microprocessor. Cycle time T cycle = 1 / 12.5 MHz = 80 ns Clock cycles C = 1 (8+4) + 8 ( ) + 1 ( ) = 280 cycles Number of instructions Execution time N = = 38 instructions T exe = C T cycle = 22.4 ms CPE/EE 421/521 Microcomputers 7 #of cycles LEA TABLE,A0 8 CLR.W D1 4 LOOP MOVE.B D0,(A0)+ 8 ADDQ.W #1,D1 4 CMPI.W #9,D1 8 BNE LOOP 10(taken)/8 Singe execution Loop (9 iterations) b) What is the average CPI (number of clocks per instructions)? Number of clocks/instruction CPI = C / N = 280 / 38 = 7.37 Total number of clock cycles to execute the program Total number of instructions in the program (loops!) CPE/EE 421/521 Microcomputers 8 Alex Milenkovich 4
5 #of cycles LEA TABLE,A0 8 CLR.W D1 4 LOOP MOVE.B D0,(A0)+ 8 ADDQ.W #1,D1 4 CMPI.W #9,D1 8 BNE LOOP 10(taken)/8 Singe execution Loop (9 iterations) b) What is the MIPS rate? MIPS rate = 10-6 f / CPI = 12.5 / 7.37 = 1.7 MIPS Processor s clock frequency The average number of clocks per instruction CPE/EE 421/521 Microcomputers 9 The MSP430 Family Alex Milenkovich 5
6 The Family Broad family of TI s 16-bit microcontrollers from 1Kbytes ROM, 128 bytes RAM (approx. $1 ) to 60Kbytes ROM, 2K RAM ( $10) Three subfamilies MSP430x1xx: basic unit MSP430x3xx: more features MSP430x4xx: built-in LCD driver CPE/EE 421/521 Microcomputers 11 Part numbering convention MSP430M t F a F b M c Mt : Memory type C ROM, F Flash, P OTP, E EPROM Fa,Fb 10, 11 basic 12, 13 HW UART 14 HW UART, HW multiplier 31, 32 LCD Controller 33 LCD controller, HW UART, HW multiplier 41 LCD controller 43 - LCD controller, HW UART 44 - LCD controller, HW UART, HW multiplier CPE/EE 421/521 Microcomputers 12 Alex Milenkovich 6
7 Part numbering convention MSP430M t F a F b M c Mc : Memory capacity 0: 1 Kb ROM, 128 b RAM 1: 2 KB ROM, 128 b RAM 2: 4 KB ROM, 256 b RAM... 9: 60 KB ROM, 2 Kb RAM CPE/EE 421/521 Microcomputers 13 MSP 430 Roadmap CPE/EE 421/521 Microcomputers 14 Alex Milenkovich 7
8 MSP430 Typical Applications Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Humidity measurement Temperature measurement Weight scales Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system Utility Metering Gas Meter Water Meter Heat Volume Counter Heat Cost Allocation Electricity Meter Meter reading system (RF) Sports equipment Altimeter Bike computer Diving watches Security Glass break sensors Door control Smoke/fire/gas detectors Home environment Air conditioning Control unit Thermostat Boiler control Shutter control Irrigation system White goods (Washing machine,..) Misc Smart card reader Taxi meter Smart Batteries CPE/EE 421/521 Microcomputers 15 LCD Adj. Vol. Regul. RS232 RS232 controller Analog I/O 2-axes joystick LEDs Switches Keypad Thermistor An MSP430-Based System mc CPE/EE 421/521 Microcomputers 16 Alex Milenkovich 8
9 Basic WISE Battery Microcontroller TI MSP430F149 8-channel 12-bit AD conv. Accelerometer Movement detection Analog Device ADXL202 Transceiver LINX 916 MHz Another MSP430-Based System CPE/EE 421/521 Microcomputers 17 MSP430 Documentation MSP430 home page (TI) User s manual Datasheet TI Workshop document IAR Workbench Tutorial CPE/EE 421/521 Microcomputers 18 Alex Milenkovich 9
10 MSP 430 Modular Architecture CPE/EE 421/521 Microcomputers 19 MSP bit RISC Large 16-bit register file eliminates single accumulator bottleneck High-bandwidth 16-bit data and address bus with no paging RISC architecture with 27 instructions and 7 addressing modes Single-cycle register operations with full-access Direct memory-memory transfer designed for modern programming Compact silicon 30% smaller than an 8051 saves power and cost CPE/EE 421/521 Microcomputers 20 Alex Milenkovich 10
11 Double Data Fetch Technology (DDFT) CPE/EE 421/521 Microcomputers 21 CPU Introduction RISC architecture with 27 instructions and 7 addressing modes. Orthogonal architecture with every instruction usable with every addressing mode. Full register access including program counter, status registers, and stack pointer. Single-cycle register operations. Large 16-bit register file reduces fetches to memory. 16-bit address bus allows direct access and branching throughout entire memory range. 16-bit data bus allows direct manipulation of word-wide arguments. Constant generator provides six most used immediate values and reduces code size. Direct memory-to-memory transfers without intermediate register holding. Word and byte addressing and instruction formats. CPE/EE 421/521 Microcomputers 22 Alex Milenkovich 11
12 CPU Registers CPE/EE 421/521 Microcomputers 23 Registers: PC (R0) Each instruction uses an even number of bytes (2, 4, or 6) PC is word aligned (the LSB is 0) MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL ; Branch indirect, indirect R14 CPE/EE 421/521 Microcomputers 24 Alex Milenkovich 12
13 Registers: SP (R1) Stack pointer for return addresses of subroutines and interrupts SP is word aligned (the LSB is 0) Pre-decrement/post-increment scheme MOV 2(SP),R6 ; Item I2 > R6 MOV R7,0(SP) ; Overwrite TOS with R7 PUSH #0123h ; Put 0123h onto TOS POP R8 ; R8 = 0123h CPE/EE 421/521 Microcomputers 25 Registers: SR (R2) C: SR(0) Z: SR(1) N: SR(2) GIE (Global interrupt enable): SR(3) CPUOff: SR(4) OSCOff: SR(5) SCG1, SCG0: SR(7), SR(6) V: SR(8) CPE/EE 421/521 Microcomputers 26 Alex Milenkovich 13
14 Status bits CPE/EE 421/521 Microcomputers 27 Constant Generators As source register addressing mode in the instruction word CPE/EE 421/521 Microcomputers 28 Alex Milenkovich 14
15 CISC / RISC Instruction Set CPE/EE 421/521 Microcomputers 29 Memory Map Special function registers memory locations 0000h 000Fh 0000h, 0001h: interrupt enables 0002h, 0003h: interrupt flags 0004h, 0005h: module enable flags Peripheral registers byte addressable: 0010h 00FFh word addressable: 0100h 01FFh RAM: 0200h CPE/EE 421/521 Microcomputers 30 Alex Milenkovich 15
16 27 Core RISC Instructions CPE/EE 421/521 Microcomputers 31 Emulated Instructions CPE/EE 421/521 Microcomputers 32 Alex Milenkovich 16
17 51 Total Instructions CPE/EE 421/521 Microcomputers 33 Double operand instructions CPE/EE 421/521 Microcomputers 34 Alex Milenkovich 17
18 Single Operand Instruction CPE/EE 421/521 Microcomputers 35 Jump Instructions CPE/EE 421/521 Microcomputers 36 Alex Milenkovich 18
19 3 Instruction Formats CPE/EE 421/521 Microcomputers 37 Addressing Modes CPE/EE 421/521 Microcomputers 38 Alex Milenkovich 19
20 Register Addressing Mode CPE/EE 421/521 Microcomputers 39 Register-Indexed Addressing Mode CPE/EE 421/521 Microcomputers 40 Alex Milenkovich 20
21 Symbolic Addressing Mode CPE/EE 421/521 Microcomputers 41 Absolute Addressing Mode CPE/EE 421/521 Microcomputers 42 Alex Milenkovich 21
22 Register Indirect Addressing Mode CPE/EE 421/521 Microcomputers 43 Register Indirect Autoincrement Addressing Mode CPE/EE 421/521 Microcomputers 44 Alex Milenkovich 22
23 Immediate Addressing Mode CPE/EE 421/521 Microcomputers 45 Code Reduction Effect of Constant Generator CPE/EE 421/521 Microcomputers 46 Alex Milenkovich 23
24 Machine Cycles for Format I Instructions CPE/EE 421/521 Microcomputers 47 Machine Cycles for Format II/III Instructions CPE/EE 421/521 Microcomputers 48 Alex Milenkovich 24
25 MSP430 Memory Model CPE/EE 421/521 Microcomputers 49 Memory Organization CPE/EE 421/521 Microcomputers 50 Alex Milenkovich 25
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