INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

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UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T,

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 21 Title: s and Summary: Architectures; Examples of current devices. 2010/2011 Nuno.Roma@ist.utl.pt

.. Digital Signal Processors (DSP) Architectures TMS320C55 Parallelism

2 Architectures for Embedded Computing s and Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 47 Previous Class In the previous class... Digital Signal Processors (DSP) Architectures TMS320C55 Parallelism exploitation (SIMD, VLIW) TMS320C6x DSP market and their future Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 47

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 47 Summary Today: s & : Architectures; Examples of current devices. Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 47

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 47 Processing unit particularly suited to the control of simple procedures or devices in embedded systems; Processor families: General Purpose Processors (GPP): transfer and data manipulation operations (MOVs); conditional execution operations (IF... ELSE...); Digital Signal Processors (DSP): mathematical computation (mainly, multiplications); s: interface with the outside world (peripherals). Common applications: control, actuators, instrumentation, etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 47

5 Application examples Personal appliances: Cellular phones; Watches; Calculators; PDAs. Computer components: Mouse; Keyboards; Modem; Fax; Battery charger. Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 47 Application Examples Home appliances: Alarms; Thermostats; Ar conditioners; Remote controllers; Most domestic machines. Industrial applications: Industrial robots (manipulators); Belt conveyor systems; Lifts; Automatic control; Instrumentation. Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 47

Application Examples Car industry: On-board

Entertainment: Video games; Consoles; Toys. Prof.

General Purpose Processors (GPPs): CPU, Memory and

6 Application Examples Car industry: On-board computer; Controllers of traction, injection, transmission, break (ABS), etc.; Air bag; Air conditioning; Instrumentation. Entertainment: Video games; Consoles; Toys. Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 47 GPPs versus s General Purpose Processors (GPPs): CPU, Memory and IO integrated in a single chip, board or several boards. Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 47

GPPs versus s General Purpose Processors (GPPs): CPU, Memory and IO integrated in a single chip, board or several boards. s: CPU, Memory, IO and peripherals integrated in a single chip. Prof.

7 GPPs versus s General Purpose Processors (GPPs): CPU, Memory and IO integrated in a single chip, board or several boards. s: CPU, Memory, IO and peripherals integrated in a single chip. Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 47 GPPs versus s General Purpose Processors (GPPs): High performance CPU, in an independent chip; Absence of any RAM, ROM and IO modules in the CPU chip: The used memory space should be defined and adjusted according to each particular application; Peripherals (timer, serial port, etc.) are external to the CPU chip. Expansible, versatile and general purpose Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 47

GPPs versus s s: CPU with few resources (e.g.: 8-bits); RAM, ROM and IO integrated within the CPU chip; The available memory space is fixed; Peripherals integrated within the CPU chip.

8 GPPs versus s s: CPU with few resources (e.g.: 8-bits); RAM, ROM and IO integrated within the CPU chip; The available memory space is fixed; Peripherals integrated within the CPU chip. Suitable for low-cost and restricted (power, HW, etc.) applications Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 47 GPPs versus s Adopted architectures: Von Neumann architecture: Single memory shared by program and data; The processor is interconnected by a data and an address bus. Harvard architecture: Separated memories for program and data; Independent data data and address buses for each memory device. Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 47

9 s CPU and Peripherals Simple CPU, implemented either with: Single-cycle state machine; Control unit with a state machine; Microprogrammed control unit; Very simple pipeline. On-chip peripherals: I/O ports; RAM and ROM memories; Timer; Interruptions controller; USART; Parallel port; etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 47 s Families Most manufacturers offer a wide set of devices, with different performance levels; Processing power: 4-bits, 8-bits, 16-bits, 32-bits: 8-bits microcontrollers are the most widely adopted and used by the majority of the applications; 32-bits and 64-bits are only requested by very specialized and reduced markets, with very specific requisites: Communications; Signal processing; Video processing; etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 47

10 s Families Atmel AVR ARM Intel 8-bit 8XC42 MCS48 MCS51 8xC bit MCS96 MXS296 Microchip 12-bit instruction PIC 14-bit instruction PIC PIC16F84 16-bit instruction PIC National Semiconductor COP8 NEC Motorola 8-bit 68HC05 68HC08 68HC11 16-bit 68HC12 68HC16 32-bit 683xx SGS/Thomson ST62 Texas Instruments TMS370 MSP430 Zilog Z8 Z86E02 Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 47 s Market Market: About 16 Billions, in 2000; 8-bits microcontrollers satisfy half of the market needs! Dominant microcontrollers: Microchip 16Fxx Intel 8051 Motorola MC68HC05 National COP800 SGS/Thomson ST62 Zilog Z86Cxx Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 47

11 s Market Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 47 Intel MCS-51 s Family Intel 8051 microcontroller Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 47

Intel MCS-51 s Family 8-bits microcontroller; Introduced in the market by Intel (8051) by the end of the 1970 s; One of the most popular microcontrollers (about 40% of the market); Today, it is

12 Intel MCS-51 s Family 8-bits microcontroller; Introduced in the market by Intel (8051) by the end of the 1970 s; One of the most popular microcontrollers (about 40% of the market); Today, it is produced by several manufacturers in different formats: Intel: 8751 microcontroller UV-EPROM Atmel: AT89C51, Flash (erase before write) Dallas Semiconductor: DS5000 NV-RAM, RTC Philips: 8051 AD, DA, extended I/O, OTP and flash Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 47 Intel MCS-51 s Family CPU, RAM, ROM, I/O, interrupt logic, timer, etc. in a single chip; 8-bits data bus; 16-bits address bus: can accede 2 16 =64 kb memory positions (RAM and ROM); On-chip RAM bytes ( Data Memory ); On-chip ROM - 4 kb ( Program Memory ); 4-bytes bi-directional IO port; UART (serial port); 2 16-bit counters/timers; Interrupt controller (2 priority levels); Low-power mode. Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 47

13 Intel MCS-51 s Family Architecture: Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 47 Intel MCS-51 s Family Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 47

14 Intel MCS-51 s Family Some elements of the 8051 family: Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 47 Intel MCS-51 s Family Internal peripherals: Parallel IO ports; Clock generator; Serial port; Timers; Interrupt controller. Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 47

15 Intel MCS-51 s Family Parallel IO ports: Each port can be configured either for input or output; The direction is defined by special registers. Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 47 Intel MCS-51 s Family Serial port: Data is sent/received serially; The transmission rate (BAUD rate) and the transmission mode are configured with specific registers (SFR). Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 47

16 Intel MCS-51 s Family 2 internal timer: Each timer increments the counter at each clock cycle; The count limit is configured using specific timer registers (TH0, TL0, TH1, TL1); The current count value can be read in registers TH0, TL0, TH1, TL1; At the end of the count: An interruption is generated; Dedicated bits at SFR register are activated. Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 47 Intel MCS-51 s Family Interrupt controller: 5 types of interruption: Timer 1 Overflow; Timer 2 Overflow; External interruption 1; External interruption 2; Serial port event (buffer full, buffee empty, etc.). Interruptions are activated/inhibited using the SFR register. Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 47

Microchip s PIC Family Large microcontrollers (PIC) family:

(memory) addressing spaces available: RAM ROM EEPROM Flash

Nuno Roma ACE 2010/11 - DEI-IST 30 / 47 Microchip s PIC

17 Microchip s PIC Family Large microcontrollers (PIC) family: Wide processing capacity offer: 8, 16 or 32 bits; Several (memory) addressing spaces available: RAM ROM EEPROM Flash Advanced communication peripherals and protocols. Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 47 Microchip s PIC Family PIC microcontrollers family: Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 47

18 Microchip s PIC Family Vast set of peripherals and protocols: Communication peripherals and protocols: RS232/RS485 SPI I 2 C CAN USB TCP/IP Ethernet Control and timer peripherals: Acquisition and comparison Pulse Width Modulation (PWM) Counters and timers Watchdogs Visual peripherals: LED drivers LCD drivers Analog peripherals: A/D converters up to 12-bits D/A converters Comparators and signal amplifiers Voltage detectors Temperature sensors Oscillators Voltage references Voltage regulators Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 47 Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 47

19 - Are they another particular application of microcontrollers? Prof. Nuno Roma ACE 2010/11 - DEI-IST 34 / 47 Appeared in the beginning of the 1970 s, but... Only by the beginning of the 1980 s were the supporting technologies developed. Two types of cards appeared: Memory card (without CPU); Card with microprocessor. Prof. Nuno Roma ACE 2010/11 - DEI-IST 35 / 47

Applications: Information technology: Secure access and user authentication; Storage of digital certificates and passwords; Encryption of critical data; Cellular phones (GSM) Subscriber

20 Applications: Information technology: Secure access and user authentication; Storage of digital certificates and passwords; Encryption of critical data; Cellular phones (GSM) Subscriber authentication; Data storage; e-commerce: e-banking and e-payments; Identification and access control (tickets); Parking; Phone credit (decrement of a credit counter). Prof. Nuno Roma ACE 2010/11 - DEI-IST 36 / 47 WITHOUT microprocessor: They are usually based on the I 2 C bus (serial memory); Typical storage space: 256 Bytes; EEPROM memory: Non-volatile; write/erase cycles; 10ms to write a given cell or a group of cells; Low cost. Prof. Nuno Roma ACE 2010/11 - DEI-IST 37 / 47

WITH microprocessor Processor: Usually, 8-bits @ 3.5-5.0 MHz. E.g.

kbytes) for persistent data; ROM size 4 EEPROM size 16 RAM size; File system supported on the installed memory; Small silicon area (5mm 2 ),

21 WITH microprocessor Processor: Usually, MHz. E.g.: Intel s 8051; Memory: ROM (16 kbytes - 32 kbytes) for the operating system; RAM (256 Bytes Bytes) for data; EEPROM (4 kbytes - 16 kbytes) for persistent data; ROM size 4 EEPROM size 16 RAM size; File system supported on the installed memory; Small silicon area (5mm 2 ), due to space and energy restrictions. Prof. Nuno Roma ACE 2010/11 - DEI-IST 38 / 47 Communication: Contact-based; Contact-less (transmission with an antena); Serial protocol, 9600 bps. Prof. Nuno Roma ACE 2010/11 - DEI-IST 39 / 47

22 Power-supply: With battery; Without battery: the CPU is powered with an inductive circuit. Prof. Nuno Roma ACE 2010/11 - DEI-IST 40 / 47 Cipher algorithms: Public / Private key algorithms: RSA (Rivest-Shamir-Adleman): 1024 bits EC-167 (Elliptic Curve Cryptography): 167 bits Symmetric key algorithms: AES (Advanced Encryption Standard) 128/192/256 bits DES (Data Encryption Standard) 56/112 bits SG-LFSR (Shrinking Generator - Linear Feedback Shift Register) Prof. Nuno Roma ACE 2010/11 - DEI-IST 41 / 47

Dedicated commands to support secure / cryptography protocols: Access control: Examples: check key(), change key() Authentication: Examples: autenticate() Encryption: Examples: start encription(),

23 Dedicated commands to support secure / cryptography protocols: Access control: Examples: check key(), change key() Authentication: Examples: autenticate() Encryption: Examples: start encription(), stop encription() Atomic operations: Examples: exchange(), increment(), decrement() Prof. Nuno Roma ACE 2010/11 - DEI-IST 42 / 47 Other examples: Key generation to access e-banking systems: Prof. Nuno Roma ACE 2010/11 - DEI-IST 43 / 47

24 Other examples: Dallas ibutton: Applications: Access control; Storage; Security; Interface: Only two wires: Power + Data Ground Serial communication: 16kbps a 142kbps Prof. Nuno Roma ACE 2010/11 - DEI-IST 44 / 47 Other examples: Dallas ibutton: Functionality: Each unit has an unique address; When existent, the installed microprocessor has very scarce resources and is dedicated to the target application (e.g.: encryption engine). Available models: Address-only (ID only); Memory-only; Real-time clock; Authentication/encryption key; Sensor (thermometer, hydrometer); Data-logger. Prof. Nuno Roma ACE 2010/11 - DEI-IST 45 / 47

25 Prof. Nuno Roma ACE 2010/11 - DEI-IST 46 / 47 Dedicated architectures: Application Specific Instruction-set Processors (ASIPs) Architectures extensions: Instruction Set Architecture (ISA) extensions Prof. Nuno Roma ACE 2010/11 - DEI-IST 47 / 47

Embedded Systems. Computer Organization. Wednesday 25 November 15

Embedded Systems. Computer Organization. Wednesday 25 November 15 Embedded Systems Computer Organization Wednesday 25 November 15 Summary Previous Class Analog-Digital Interface Today: Embedded Systems Characteristics Architectures Complete Systems Computer Organization