Memory Module Specifications KVR667D2Q8F5K2/8G. 8GB (4GB 512M x 72-Bit x 2 pcs.) PC CL5 ECC 240-Pin FBDIMM Kit DESCRIPTION SPECIFICATIONS

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1 Memory Module Specifications KVR667DQ8F5K/8G 8GB (4GB 5M x 7-Bit x pcs.) PC-5300 CL5 ECC 40- FBDIMM Kit DESCRIPTION s KVR667DQ8F5K/8G is a kit of two 4GB (5M x 7-bit) PC-5300 CL5 SDRAM (Synchronous DRAM) fully buffered ECC quad rank memory modules. Total kit capacity is 8GB (89MB). Each module is based on thirty-six 8M x 8-bit 667MHz DDR FBGA components. Each module also includes an AMB device (Advanced Memory Buffer). The electrical and mechanical specifications are as follows: SPECIFICATIONS FBDIMM Module 40-pin JEDEC Standard Memory Organization 4 rank of x8 devices DDR DRAM Interface SSTL_8 DDR Speed Grade 667 Mbps CAS Latency Module Bandwidth 5.3 GB/s DRAM VDD = VDDQ =.8V AMB VCC = VCCFBD =.5V EEPROM VDDSPD = 3.3V (typical) Heat Spreader Full DIMM Heat Spreader (FDHS) PCB Height 38mm, double-side RoHS Compliant Kingston.com Document No. VALUERAM A00 0/8/07 Page

2 DDR 40-pin FBDIMM out: V DD V DD 3 PN3 5 SN3 6 PN9 8 SN9 9 PS9 SS9 V DD V DD 3 PN3 5 SN3 6 V SS 8 V SS 9 V SS V SS 3 V DD 3 V DD 33 V SS 53 V SS 63 PN0 83 SN0 93 PS5 3 SS5 4 V SS 4 V SS 34 PN4 54 SN4 64 PN0 84 SN0 94 PS5 4 SS5 5 V DD 5 V DD 35 PN4 55 SN4 65 V SS 85 V SS 95 V SS 5 V SS 6 V DD 6 V DD 36 V SS 56 V SS 66 PN 86 SN 96 PS6 6 SS6 7 V DD 7 V DD 37 PN5 57 SN5 67 PN 87 SN 97 PS6 7 SS6 8 V SS 8 V SS 38 PN5 58 SN5 68 V SS 88 V SS 98 V SS 8 V SS 9 V CC 9 V CC 39 V SS 59 V SS KEY 99 PS7 9 SS7 0 V CC 30 V CC 40 PN3 60 SN3 69 V SS 89 V SS 00 PS7 0 SS7 V SS 3 V SS 4 PN3 6 SN3 70 PS0 90 SS0 0 V SS V SS V CC 3 V CC 4 V SS 6 V SS 7 PS0 9 SS0 0 PS8 SS8 3 V CC 33 V CC 43 V SS 63 V SS 7 V SS 9 V SS 03 PS8 3 SS8 4 V SS 34 V SS 44 RFU* 64 RFU* 73 PS 93 SS 04 V SS 4 V SS 5 V TT 35 V TT 45 RFU* 65 RFU* 74 PS 94 SS 05 RFU** 5 RFU** 6 VID 36 VID0 46 V SS 66 V SS 75 V SS 95 V SS 06 RFU** 6 RFU** 7 RESET 37 DNU/M_Test 47 V SS 67 V SS 76 PS 96 SS 07 V SS 7 V SS 8 V SS 38 V SS 48 PN 68 SN 77 PS 97 SS 08 V DD 8 SCK 9 RFU** 39 RFU** 49 PN 69 SN 78 V SS 98 V SS 09 V DD 9 SCK 0 RFU** 40 RFU** 50 V SS 70 V SS 79 PS3 99 SS3 0 V SS 30 V SS V SS 4 V SS 5 PN6 7 SN6 80 PS3 00 SS3 V DD 3 V DD PN0 4 SN0 5 PN6 7 SN6 8 V SS 0 V SS V DD 3 V DD 3 PN0 43 SN0 53 V SS 73 V SS 8 PS4 0 SS4 3 V DD 33 V DD 4 V SS 44 V SS 54 PN7 74 SN7 83 PS4 03 SS4 4 V SS 34 V SS 5 PN 45 SN 55 PN7 75 SN7 84 V SS 04 V SS 5 V DD 35 V DD 6 PN 46 SN 56 V SS 76 V SS 85 V SS 05 V SS 6 V DD 36 V DD 7 V SS 47 V SS 57 PN8 77 SN8 86 RFU* 06 RFU* 7 V TT 37 V TT 8 PN 48 SN 58 PN8 78 SN8 87 RFU* 07 RFU* 8 SA 38 VDDSPD 9 PN 49 SN 59 V SS 79 V SS 88 V SS 08 V SS 9 SDA 39 SA0 30 V SS 50 V SS 60 PN9 80 SN9 89 V SS 09 V SS 0 40 SA 90 PS9 0 SS9 RFU = Reserved Future Use. * These pin positions are reserved for forwarded clocks to be used in future module implementations ** These pin positions are reserved for future architecture flexibility ) The following signals are CRC bits and thus appear out of the normal sequence: PN/PN, SN/SN, PN3/PN3, SN3/SN3, PS9/PS9, SS9/SS9 Kingston.com Document No. VALUERAM A00 0/8/07 Page

3 DIMM Connector Description: Name Description Count SCK System Clock Input, positive line SCK System Clock Input, negative line PN[3:0] Primary Northbound Data, positive lines 4 PN[3:0] Primary Northbound Data, negative lines 4 PS[9:0] Primary Southbound Data, positive lines 0 PS[9:0] Primary Southbound Data, negative lines 0 SN[3:0] Secondary Northbound Data, positive lines 4 SN[3:0] Secondary Northbound Data, negative lines 4 SS[9:0] Secondary Southbound Data, positive lines 0 SS[9:0] Secondary Southbound Data, negative lines 0 Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output SA[:0] VID[:0] SPD Address Inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR-based Fully Buffered DIMMs VID[0] is V DD value: OPEN =.8 V, GND =.5 V; VID[] is V CC value: OPEN =.5 V, GND =. V 3 RESET AMB reset signal RFU Reserved for Future Use 6 V CC AMB Core Power and AMB Channel Interface Power (.5 Volt) 8 V DD DRAM Power and AMB DRAM I/O Power (.8 Volt) 4 V TT DRAM Address/Command/Clock Termination Power (V DD /) 4 V DDSPD SPD Power V SS Ground 80 DNU/M_Test The DNU/M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. Total 40. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility Absolute Maximum Ratings Symbol Parameter MIN MAX Units VIN, VOUT Voltage on any pin relative to V SS V VCC Voltage on V CC pin relative to V SS V VDD Voltage V DD pin relative to Vss V VTT Voltage on V TT pin relative to V SS V T STG Storage temperature C T CASE DDR SDRAM device operating temperature (Ambient) 0 95 C 95 () AMB device operating temperature (Ambient) 0 0 C Note: () Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to trefi = 3.9 µs. Kingston.com Document No. VALUERAM A00 0/8/07 Page 3

4 Functional Block Diagram: S3 S S S DQ0 DQ DQ DQ3 DQ4 DQ5 DQ6 DQ7 CS NU/ NU/ CS NU/ NU/ CS CS I/O D0 I/O D9 I/O D8 I/O D7 DQ3 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CS NU/ NU/ CS NU/ NU/ CS CS I/O D4 I/O D3 I/O D I/O D DQ8 DQ9 DQ0 DQ DQ DQ3 DQ4 DQ5 CS NU/ NU/ CS NU/ NU/ CS CS I/O D I/O D0 I/O I/O D9 D8 DQ40 DQ4 DQ4 DQ43 DQ44 DQ45 DQ46 DQ47 CS NU/ NU/ CS NU/ NU/ CS CS I/O D5 I/O D4 I/O I/O D3 D DQ6 DQ7 DQ8 DQ9 DQ0 DQ DQ DQ3 CS NU/ NU/ CS NU/ NU/ CS CS I/O D I/O D I/O I/O D0 D9 DQ48 DQ49 DQ50 DQ5 DQ5 DQ53 DQ54 DQ55 CS NU/ NU/ CS CS NU/ NU/ CS I/O D6 I/O D5 I/O D4 I/O D DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ30 DQ3 NU/ NU/ CS CS I/O D3 I/O D NU/ I/O CS NU/ CS I/O D D DQ56 DQ57 DQ58 DQ59 DQ60 DQ6 DQ6 DQ63 CS NU/ NU/ CS CS NU/ NU/ CS I/O D7 I/O D6 I/O I/O D5 D34 CB0 CB CB CB3 CB4 CB5 CB6 CB7 NU/ NU/ CS CS I/O D8 I/O D7 NU/ I/O CS NU/ CS D6 I/O D35 PN0-PN3 PN0-PN3 PS0-PS9 PS0-PS9 SDA SA-SA SA0 RESET SCK/SCK A M B SN0-SN3 SN0-SN3 SS0-SS9 SS0-SS9 S0 -> CS (D0-D8) / S -> CS (D8-D6) CKE0 -> CKE (D0-D8 / D8-D6) S -> CS (D9-D7) / S3 -> CS (D7-D35) CKE -> CKE (D9-D7 / D7-D35) ODT -> ODT (all SDRAMs) BA0-BA (all SDRAMs) A0-A5 (all SDRAMs) RAS (all SDRAMs) CAS (all SDRAMs) WE (all SDRAMs) CK/CK (all SDRAMs) 85 All address/command/control/clock Notes:. DQ-to-I/O wiring may be changed within a byte.. There are two physical copies of each address/command/control/clock WP A0 Serial PD A A SA0 SA SA SDA V TT V TT V CC V DDSPD V DD V REF V SS Terminators AMB SPD, AMB D0-D35, AMB D0-D35 D0-D35, SPD, AMB Kingston.com Document No. VALUERAM A00 0/8/07 Page 4

5 Architecture: Advanced Memory Buffer Description: Name Description Count FB-DIMM Channel Signals 99 SCK System Clock Input, positive line SCK System Clock Input, negative line PN[3:0] Primary Northbound Data, positive lines 4 PN[3:0] Primary Northbound Data, negative lines 4 PS[9:0] Primary Southbound Data, positive lines 0 PS[9:0] Primary Southbound Data, negative lines 0 SN[3:0] Secondary Northbound Data, positive lines 4 SN[3:0] Secondary Northbound Data, negative lines 4 SS[9:0] Secondary Southbound Data, positive lines 0 SS[9:0] Secondary Southbound Data, negative lines 0 FBDRES To an external precision calibration resistor connected to Vcc DDR Interface Signals 75 [8:0] Data Strobes, positive lines 9 [8:0] Data Strobes, negative lines 9 [7:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. 9 [7:9] Data Strobes (x4 DRAM only), negative lines 9 DQ[63:0] Data 64 CB[7:0] Checkbits 8 A[5:0]A, A[5:0]B Addresses. A0 is part of the pre-charge command 3 BA[:0]A, BA[:0]B Bank Addresses 6 RASA, RASB Part of command, with CAS, WE, and CS[3:0]. CASA, CASB Part of command, with RAS, WE, and CS[3:0]. WEA, WEB Part of command, with RAS, CAS, and CS[3:0]. ODTA, ODTB On-die Termination Enable CKE[:0]A, CKE[:0]B Clock Enable (one per rank) 4 CS[:0]A, CS[:0]B Chip Select (one per rank) 4 CLK[3:0] CLK[:0] used on 9 and 8 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:] should be output disabled when not in use. 4 CLK[3:0] Negative lines for CLK[3:0] 4 DDRC_C4 DDR Compensation: Common return pin for DDRC_B8 and DDRC_C8. DDRC_B8 DDR Compensation: Resistor connected to common return pin DDRC_C4 DDRC_C8 DDR Compensation: Resistor connected to common return pin DDRC_C4 DDRC_B DDR Compensation: Resistor connected to V SS DDRC_C DDR Compensation: Resistor connected to V DD Kingston.com Document No. VALUERAM A00 0/8/07 Page 5

6 Advanced Memory Buffer Description: SPD Bus Interface Signals 5 Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output SA[:0] SPD Address Inputs, also used to select the DIMM number in the AMB Miscellaneous Signals 63 PLLTSTOP LL Clock Observability Output VCCAPLL VSSAPLLA Analog VCC for the PLL. Tied with low pass filter to VCC. nalog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM. TEST_pin Leave floating on the DIMM 6 TESTLO_pin Tie to ground on the DIMM 5 BFUNC Tie to ground to set functionality as buffer on DIMM. RESET AMB reset signal NC No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands. RFUR eserved for Future Use 8 Power/Ground Signals 3 V CC AMB Core Power (.5 Volt) 4 V CCFBD AMB Channel I/O Power (.5 Volt) 8 V DD AMB DRAM I/O Power (.8 Volt) 4 V DDSPD SPD Power (3.3 Volt) V SS Ground Total 655. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.. TESTLO_AB0 and TESTLO_AC0 should be configured for debug purposes on prototype DIMMs: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground. Kingston.com Document No. VALUERAM A00 0/8/07 Page 6

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