SAR ADC That is Configurable to Optimize Yield

Transcription

1 APCCAS 2010 Session :Hang Jebat 1 & 2 ADC / DAC II Paper ID : SAR ADC That is Configurable to Optimize Yield T. Ogawa, H. Kobayashi, Y. Tan, S. Ito, S. Uemori, N. Takai, K. Niitsu, T. J. Yamaguchi, T. Matsuura, N. Ishikawa Gunma University Supported by STARC 1

2 Outline Research purpose Background Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 2

3 Research purpose Non-binary SAR ADC can achieve High-speed operation Power consumption increased This work introduces the solution for the speed-power trade-off for yield improvement. Propose the method of estimating the DAC output settling time and speed margin at production test. Test chip fabrication & its measurements demonstrate the effectiveness of our approach. 3

4 Outline Research purpose Background Successive approximation algorithm DAC incomplete settling SA algorithm selection Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 4

5 SAR ADC Block Analog input S/H Comparator DAC CLK SAR Logic Digital output SAR ADC is digital rich approach. Suitable for fine CMOS implementation. 5

6 Binary search algorithm 16 Vin 8 Principle of a balance Binary weight 4bit 4step Vin 8 Comparison 0 Comparator output Vin = 8 _ 1 2 = 9 6

7 Problem of binary search algorithm 16 Search result has error. Error Vin 8 Principle of a balance Binary weight 4bit 4step Error Vin Comparator output 1 Vin = 2 _ 8 4 = 7 Digital output has error. 7

8 16 Vin 8 Error correction with non-binary Redundancy Error correction Non-binary weight Error Vin 8 1 Error bit 5step Redundancy:1step 1 2 Vin = _ 8 3 = 9 8

9 Digital error correction principle of non-binary algorithm Digital output 9 case Binary search algorithm Comparator output: Error Correction : Not Available Dout = = 9 Only one Non-binary search algorithm Error Correction : Available Comparator output: Dout = = 9 Comparator output: Multiple Dout = = 9 9

10 Outline Research purpose Background Successive approximation algorithm DAC incomplete settling SA algorithm selection Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 10

11 Output of DAC [LSB] Settling of DAC output Last step First step 1/2LSB Short Long Settling time [τ] 11

12 AD conversion time for both algorithms Step 1 Binary search algorithm Step1 Step2 Step3 Step4 Exact DAC settling Long time Non-binary search algorithm Step 2 Step 3 Step 4 Total AD conversion time Step 5 Step 6 Correct incomplete settling error. Incomplete DAC settling Short time 12

13 Signal level Digital output code DAC settling estimation algorithm Comparator output changing point DAC settling value Ideal setting value at second step Settling value Input Comparator:1 Comparator: Redundancy Step 15 13

14 Signal level Setting test at second step (5bit 6step) Ideal settling value at second step Input Comparator :1 Comparator:0 Settling value 21LSB Correction margin: Go/No- Go 17 (Good chip) 16 Step 15 14

15 Signal level Setting test at second step (5bit 6step) Ideal settling value at second step Input Settling value 18LSB Comparator:1 Comparator: Correction Margin: Go/No- Go (Bad chip) Step 15 15

16 Step Settling value at second step V DAC TP ( k 1) V ( k) DAC( k 1)*(1 e DAC (1 e 2.3 TP TP Comparator output ) 733.3LSB t ) DAC Settling estimation ADC output

17 Research purpose Background Outline Successive approximation algorithm DAC incomplete settling SA algorithm selection Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 17

18 Fast chip (τ=3.5 ns) 10bit 11step Low-power Step P(k) SA algorithm selection for 10bit non-binary SAR ADC Middle chip (τ=4.0 ns) 10bit 12step Middle-power Step P(k) Slow chip (τ=4.5 ns) 10bit 13step High-power Step P(k) Even slow chips can meet the spec. (10MS/s) with additional power requirement. 18

19 Outline Research purpose Background Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 19

20 AD_out register Analog input Digital output Configurable non-binary SAR ADC diagram CLK frequency is variable Number of steps are variable Algorithm can be varied by rewriting RAM CLK Timing generator address Memory(RAM) S/H DAC Register + + Adder 1 0 MUX - + Subtracter Observe comparator output. 20

21 Outline Research purpose Background Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 21

22 Test of the reconfigurable non-binary SAR ADC Ramp input S/H DAC settling time is the dominant speed limiting factor of SAR ADC. Comparator CLK SAR Logic Binary digital output DAC time Comparator output 22

23 Cooperation with ATE Configurable non-binary SAR ADC DUT Ramp input DAC incomplete settling value is measured Flash Memory Write optimum SA algorithm P(k) Estimate DAC time constant τ (ATE) ATE τ is large τ is small Satisfy speed spec. with large steps Decrease power with small steps ATE: Automatic Test Equipment 23

24 Outline Research purpose Background Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 24

25 Reconfigurable Non-Binary SAR ADC Implementation and Measurement Results 0.18um CMOS 2.5mm x 2.5mm with two SAR ADCs SNDR comparison of 10step (binary) and 12step (non-binary) F in :100kHz 25

26 Verification with prototype chip DAC settling value estimation by prototype DAC output ringing case (ADC_A) DAC output no-ringing case(adc_b) Verify difference of settling values ADC_A:without bias capacitance 26

27 Signal level DAC settling estimation in ringing case DAC settling value overshoots. Step step Step Ideal value step1 step2 step3 step4 Comparator opinion Ideal:512 Ideal:758 Estimate:765 Ideal:266 Estimate:258 Ideal:871 Estimate:876 Ideal:645 Estimate:647 Ideal:379 Estimate:377 Ideal:153 Estimate:146 Ideal:936 Estimate:939 Ideal:806 Estimate:809 Ideal:710 Estimate:712 Ideal:580 Estimate:580 Ideal:444 Estimate:443 Ideal:314 Estimate:311 Ideal:218 Estimate:214 Ideal:88 Estimate:

28 Signal level DAC settling estimation in no-ringing case DAC settling is incomplete. Step step Step 2 Ideal value step1 step2 step3 step4 Comparator opinion Ideal:512 Estimate:511 Ideal:758 Estimate:750 Ideal:266 Estimate:273 Ideal:871 Estimate:864 Ideal:645 Estimate:642 Ideal:379 Estimate:381 Ideal:153 Estimate:160 Ideal:936 Estimate:931 Ideal:806 Estimate:802 Ideal:710 Estimate:707 Ideal:580 Estimate:579 Ideal:444 Estimate:444 Ideal:314 Estimate:315 Ideal:218 Estimate:221 Ideal:88 Estimate:

29 Outline Research purpose Background Successive approximation algorithm DAC incomplete settling SA algorithm selection Configurable non-binary algorithm SAR ADC Production-time configuration SAR ADC Test chip design & measurement Results Conclusion 29

30 Conclusion Propose a configurable non-binary SAR ADC. - Optimal yield DAC output settling margin is estimated by checking comparator output at each step and ADC output at final step. Measurement and simulation results validate the effectiveness of our proposed SAR ADC. 30