SuperH RISC engine Family

Transcription

1 Safety Service Satisfaction -Renesas Microcomputer- 4/28/2009 Rev

2 SuperH RISC engine Roadmap SH-4A SH-4 SH-3, SH3-DSP SH7750 series SH7750R SH7751R SH7750S SH7751 to 240 MHz SH7700 series SH7720/21 SH7727 SH7729R SH7705 SH7706 SH7709S SH7710/12/13 to 200 MHz SH-2 (SH2-DSP) SH-1 SH7030 series 20 MHz SH7020 series 20 MHz SH2-DSP SH7060 series 60 MHz SH7040 series 28.7 MHz SH7010 series to 20 MHz SH7760 SH7606 series 100 MHz SH7144 series 50 MHz SH7047 series 50 MHz SH7046 series 50 MHz SH7780 series SH7780 SH7781 SH7785 SH7763 SH7764 SH7722 SH7723 SH7730 to 600 MHz SH-2A SH2A-FPU SH7080 series 80 MHz SH7147 series 80 MHz SH7137 series SH7146 series 80 MHz SH7125 series 50 MHz SH7260 series to 200 MHz SH7200 series to 200 MHz SH7210 series 160 MHz Dual Core SH7786 Dual Core SH MHz SH MHz SH7280 series 100 MHz SH7243 series 100 MHz ASSP SuperH for Digital Audio SH-Ether SuperH with USB SuperH for Car Information System, SH-Navi SH-Mobile 2

3 SuperH Instruction System SH-1/2 SH-3/4 SH-4A 15 0 SH2-DSP instructions for DSP 160 instructions MMU control instruction, etc. instruction for DSP SH3-DSP SH-2A instructions 62 instructions 32-bit multiply-andaccumulation, etc. 68 instructions MMU control instruction, etc. 94 instructions Floating-point instruction (single/double precision), etc. 103 instructions Floating-point instruction, cache operation instruction, etc. 91 instructions Enhanced shift, operation, bit manipulation, and division instructions 112 instructions Floating-point instruction (single/double precision) 3

4 Background of SH-2A Development - Demands of Automotive, Industrial, and Consumer Appliances Fields - - High-speed, highly-functional operations due to complex compound control - High-speed control of mechanical sections such as external I/O module - Improved real-time performance Increased ROM capacity - Reduction of program code size Better cycle performance - Instruction execution time (CPI) improvement High-speed response and improved real-time performance - Shorter interrupt response time 4

5 Features of the SH-2A Improved execution cycle performance - Harvard architecture (prevention of IF-MA contention) - 5-stage pipeline deferred Prevention of increase in branch penalty and data hazard - Superscalar architecture (two instructions are issued simultaneously) - New instructions (32-bit + 16-bit instructions) added Improved interrupt response time - Introduction of register banks Reduced program code size - New instructions (32-bit + 16-bit instructions) added Improved code efficiency together with optimization by compiler 5

6 SH-2A: Most Powerful Real-Time Control Engine 1. Fastest interrupt response time - Shortest interrupt response time: 6 clock cycles (30 ns at 200 MHz) - On-chip memory for saving register contents 2. Significantly-improved performance times the performance of the SH-2 at the same operation frequency - Adoption of superscaler architecture (two instructions are simultaneously executed) 3. Greatly-improved code efficiency times the code efficiency of the SH-2 Efficiency in code size: 75% compared to the SH-2 - Addition of new instructions and improved compiler performance Relative value SH-2 at 50 MHz Relative value SH-2 at 50 MHz SH-2 1/25 SH-2A at 200 MHz SH-2A at 200 MHz Relative value % 0.5 SH-2A 6

7 SH-2A Pipeline Operation In the SH-2A, an instructions is executed by five-stage pipeline as shown below. Two instruction are simultaneously issued by superscalar operation. Instruction 1 IF ID EX MA WB Instruction 2 Instruction 3 Instruction 4 IF ID EX Instruction 5 IF ID EX MA WB IF ID EX IF ID EX MA WB IF: Instruction fetch ID: Decode EX: Execution MA: Memory access WB: Write back Instruction 6 IF ID EX Time 7

8 SH-2A Interrupt Latency Improvement (1) (1) SH-2 (2) SH-2A CPU Internal RAM 15 banks CPU Internal RAM R0 R0 R0 R14 R14 R14 SP GBR MACH MACL SP GBR MACH MACL Register banks SP GBR MACH MACL PR PR PR SR SR SR SR PC PC PC PC All registers SR and PC 32 bits 32 bits The SH-2A has memory for saving register contents according to interrupt priority level, which enables automatic and collective saving of register contents when an interrupt occurs. 8

9 SH-2A Interrupt Latency Improvement (2) SH-2: Interrupt Exception processing Saving register contents by software processing Saving Register contents 9 37 Cycles SH-2A: Interrupt Exception processing Saving register contents Saving register contents by hardware processing: Automatic and fast (1) PR, GBR, MCL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 (4) R4, R5, R6, R7 (5) R0, R1, R2, R Cycles 9

10 Controller Type SH7020 Series SH7030 Series SH7040 Series SH7010 Series SH7060 Series SH7144 Series SH7046 Series SH7047 Series SH7125 Series SH7146 Series SH7080 Series SH7147 Series SH7137 Series SH7200 Series SH7260 Series SH7210 Series SH7280 Series SH7243 Series 10

11 Roadmap of the SuperH Controllers SH /12.5 MHz, 112/120 pins SH /12.5 MHz, 100 pins SH-1 Under development In planning SH MHz, 176 pins SH2-DSP SH /28.7 MHz, 112/120/144 pins SH /28.7 MHz, 100/112 pins SH-2 SH MHz, 176 pins SH MHz, 112/144 pins SH MHz, 100 pins SH MHz, 80 pins CAN SH MHz, 100/112/144/176 pins SH /64 MHz, 100 pins SH MHz, 80/100 pins SH MHz 80/100 pins SH MHz, 48/64 pins CAN CAN SH7260 SH7200 to 200 MHz, 176 to 240 pins SH MHz, 144 pins SH MHz, 144/176 pins SH MHz, 100 pins 200 MHz, 272 pins USB, CAN Dual-core SH7265 SH7205 Next generation SH-2A, SH2A-FPU ROM-less On-chip ROM 11

12 Features of the SH7280 Series Products in the SH7280 Series of flash-memory-equipped microcontrollers feature the new SH-2A CPU core and operate at a maximum frequency of 100 MHz. As well as A/D converters with a 12-bit resolution and timers for motor control, on-chip peripheral modules include a USB interface. High performance SH-2A core - Higher CPU performance with 200 MIPS@100 MHz - Faster response to interrupts On-chip register bank On-chip large-capacity flash memory: 512 KB/768 KB/1 MB Wide range of power-supply voltage: 3.0 to 5.5 V * Abundant peripheral modules - On-chip timers for advanced three-phase motors: MTU2 and MTU2S - High-speed A/D converters with 12-bit resolution: 1 μs/ch - Full-speed USB 2.0: 1 On-chip debugging functionality * Analog power: AVcc = 4.5 to 5.5 V - Full ICE and on-chip debugger USB power: DrVcc = 3.0 to 3.6 V Main target applications Digital audio and visual devices, office equipment, card readers, general-purpose inverters, AC servomotors, numerically controlled machines, sequencers 12

13 Functional Overview of the SH7280 Series CPU core - SH-2A: SuperH RISC engine - 32-bit multiplier (32 bits 32 bits = 64 bits) - Harvard architecture Operating frequency - CPU clock: 100 MHz (max.) - Bus clock: 50 MHz (max.) - Peripheral clock: 50 MHz (max.) Power-supply voltage to 5.5 V (AVcc = 4.5 to 5.5 V, DrVcc = 3.0 to 3.6 V) On-chip memory - Flash memory: 512 KB/768 KB/1 MB - RAM: 24 KB/32 KB External memory interfaces - SRAM, byte-selectable SRAM, burst ROM, SDRAM - External bus width SH7285: 8 bits/16 bits SH7286: 8 bits/16 bits/32 bits - External memory space is divisible into up to 8 areas (maximum 64-MB each). Packages - SH7285: LQFP-144 (20 mm 20 mm, 0.5-mm pitch) - SH7286: LQFP-176 (20 mm 20 mm, 0.4-mm pitch), LQFP-176 (24 mm 24 mm, 0.5-mm pitch) On-chip function - 16-bit multi-function PWM timers: 6 (MTU2), 3 (MTU2S) - Port output enable (POE) - 16-bit peripheral timers: 2 - Watchdog timer: 1 -I 2 C bus interface: 1 - SSU interface: 1 On-chip function - USB interface: 1, 2.0 Full Speed Function - RCAN-ET: 1 (only for the SH7286) - High-speed SCI: 1 (16-stage transmission/reception FiFo) - SCI: 4 (dual use as UART or clock synchronous) - Pins used for external interrupts: 9 - DMA controller: 8 ch; DTC also included - 12-bit A/D converters SH7285: 4 ch (with three S/H circuits) 2 units SH7286: 4 ch (with three S/H circuits) 3 units - 8-bit D/A converters: 2 ch (only for the SH7286) On-chip debugging function - H-UDI/AUD - User break controller (UBC) Bus interface SH-2A 100 MHz SCI/SCIF USB 12-bit A/D converter RAM Flash ROM 32-bit multiplier MTU2 MTU2S DMAC/DTC CMT CAN * D/A converter * WDT I 2 C/SSU Port Block Diagram of the SH7280 *: SH7286 only. 13

14 Features of the SH7243 Series Products in the SH7243 Series of flash-memory-equipped microcontrollers will feature the new SH-2A CPU core and operate at a maximum frequency of 100 MHz. The SH7243 Series is derived from the SH7280 Series by trimming functionality (less on-chip ROM and RAM, USB, SSU, and other modules removed)for an initial product in a 100-pin package. High performance with SH-2A core - Higher CPU performance with 200 MIPS@100 MHz - Faster response to interrupts On-chip register bank Wide range of power-supply voltage: 3.0 to 5.5 V * Abundant peripheral modules - On-chip timers for advanced three-phase motors: MTU2 and MTU2S - High-speed A/D converters with 12-bit resolution: 1 μs/ch On-chip debugging functionality - Full ICE and on-chip debugger * Analog power: AVcc = 4.5 to 5.5 V Main target applications AC servomotors, numerically controlled machines, sequencer, general-purpose inverters, robots, measuring equipment 14

15 Functional Overview of the SH7243 Series CPU core - SH-2A: SuperH RISC engine - 32-bit multiplier (32 bits 32 bits = 64 bits) - Harvard architecture Operating frequency - CPU clock: 100 MHz (max.) - Bus clock: 50 MHz (max.) - Peripheral clock: 50 MHz (max.) Power-supply voltage to 5.5 V (AVcc = 4.5 to 5.5 V) On-chip memory - Flash memory: 128 KB/256 KB - RAM: 8 KB/12 KB External memory interfaces - SRAM, byte-selectable SRAM, burst ROM, SDRAM - External bus width: selectable as 8 bits/16 bits Package - LQFP-100 (14 mm 14 mm, 0.5-mm pitch) On-chip peripheral function - 16-bit multi-function PWM timers: 6 (MTU2), 3 (MTU2S) - Port output enable (POE) - 16-bit cycle timers: 2 - Watchdog timer: 1 On-chip peripheral function - High-speed SCI: 1 (16-stage transmission/reception FiFo) - SCI: 2 (dual use as UART or clock synchronous) - Pins used for external interrupts: 9 - DMA controller: 8 ch; DTC also included - 12-bit A/D converters: 4 ch (with three S/H circuits) 2 units On-chip debugging function - H-UDI/AUD - User break controller (UBC) Bus interface SH-2A 100 MHz SCI/SCIF 12-bit A/D converter RAM Flash ROM 32-bit multiplier MTU2 MTU2S DMAC/DTC CMT WDT Block Diagram of the SH7243 Port 15

16 Features of the SH7210 Series Products in the SH7210 Series of flash-memory-equipped microcontrollers feature the new SH-2A CPU core and operate at a maximum frequency of 160 MHz. On-chip peripheral modules include timers for motor control, A/D converters with a 12-bit resolution, etc. High performance SH-2A core - Higher CPU performance with 320 MIPS@160 MHz - Faster response to interrupts On-chip register bank On-chip large-capacity flash memory: 512 KB/384 KB Abundant peripheral modules - On-chip timers for advanced three-phase motors: MTU2 and MTU2S - High-speed A/D converters with 12-bit resolution: 1.25 μs/ch - SDRAM interface On-chip debugging functionality - Full ICE and on-chip debugger Main target applications AC servomotors, inverters, vending machines, surveillance cameras, video printers, bar-code readers, printers, color photocopiers 16

17 Functional Overview of the SH7210 Series CPU core - SH-2A: SuperH RISC engine - 32-bit multiplier (32 bits 32 bits = 64 bits) - Harvard architecture Operating frequency - CPU clock: 160 MHz (max.) - Bus clock: 40 MHz (max.) - Peripheral clock: 40 MHz (max.) Power-supply voltage V ±0.1 V (CPU), 3.3 V ±0.3 V (I/O), 5.0 V ±0.5 V (A/D converter) On-chip memory - Flash memory: 512 KB/384 KB - RAM: 32 KB/24 KB External memory interfaces - SRAM, byte-selectable SRAM, burst ROM, SDRAM - External bus width: 8 bits/16 bits Package - LQFP (0.5-mm pitch) On-chip peripheral function - 16-bit multi-function PWM timers: 6 (MTU2), 3 (MTU2S) - Port output enable (POE) - 16-bit cycle timers: 2 - Watchdog timer: 1 -I 2 C bus interface: 1 - High-speed SCI: 4 (16-stage transmission/reception FiFo) - DMA controller: 8 ch - 12-bit A/D converters: 8 ch (with three S/H circuits) On-chip peripheral function - 8-bit D/A converters: 2 ch On-chip debugging function - H-UDI/AUD - User break controller (UBC) Block Diagram of the SH7211 SH-2A BSC SDRAM, SRAM, burst ROM, MPX DMAC: 8 ch Part no. Flash memory: 512 KB/384 KB RAM: 2 KB/24 KB WDT I/O Ports SCIF: 4 IIC: I 2 C bus MTU2: 16 bits 6 MTU2S: 16 bits 3 CMT: 16 bits 2 12-bit A/D converter: 8 8-bit D/A converter: 2 Range of operating temperature R5F72115D160FPV -40 to +85 C 17

18 Functions and Features of SH7206 High-performance SH-2A CPU core - Equivalent to SH MIPS@200 MHz - Faster response to interrupts internal register banks Low-power consumption and high performance: 2560 MIP software Large-capacity RAM: 128-KB/200-MHz access On-chip data/instruction separation cache: Total 16 KB Abundant bus interface - SDRAM I/F, PCMCIA - Burst ROM I/F, etc. On-chip peripheral functions for real time control - Multi-functional timer: 16 bits 11 ch, motor control - Various analog input/output: 10-bit A/D converter, 8-bit D/A converter 18

19 Overview of the SH7206 CPU core - SH-2A (SuperH RISC engine) - 32-bit on-chip multiplier (32 bits 32 bits 64 bits) - Harvard architecture Operating frequency - CPU clock: 200 MHz (max.) - Bus clock: 66 MHz (max.) - Peripheral clock: 33 MHz (max.) - Clock dedicated for the MTU2S: 100 MHz (max.) Power supply voltage to 3.6 V and 1.15 to 1.35 V (analog power supply: 3.0 to 3.6 V) Internal memory - 32 KB RAM 4 mat: a total of 128 KB - Instruction cache: 8 KB - Operand cache: 8 KB External memory interface - SRAM, byte selectable SRAM, multiplexed I/O, PCMCIA, burst ROM - External bus width: selectable from 8 bits, 16 bits, or 32 bits - External memory spaces can be divided into 9 spaces (576 Mbytes at maximum) Package - LQFP-176 (24 mm square, 0.5 mm pitch) Internal functions - Multifunctional 16-bit PWM timer: 6 (MTU2) and 3 (MTU2S) - Port output enable (POE): 9 Internal functions - 16-bit cycle timer: 2 - Watchdog timer (WDT): 1 -I 2 C bus interface: 1 - DMA controller: 8 ch - 10-bit A/D converter: 4 ch 2-8-bit D/A converter: 2 ch - SCIF: 4 (16-stage built-in FIFO for transmit and receive operations) - I/O port: 81 - External interrupt pin: 17 -JTAG interface Bus interface SH-2A: 200 MHz SCIF 8-bit D/A converter 10-bit A/D converter Cache memory 128-KB RAM 32-bit multiplier MTU2 MTU2S DMAC CMT WDT I 2 C Port 19

20 Example: AC Servo System Configuration Using SH7206 Achieves maximum CPU performance by having programs resident in internal RAM. On-chip cache improves the performance of externally installed programs. Abundant functions such as three-phase PWM output timeaaar, 10-bit A/D converter, and more. For various control Abundant Communications functions On-chip 4-ch SCIF and on-chip 1-ch I 2 C Sub-MCUs etc. EEPROM etc. SCI bus I 2 C bus 200 MHz SH7206 PWM output PWM output 8, 16, 32 bits * External 66 MHz USB 128-KB RAM ASIC ROM A/D input A/D input Motor control Possible to control 2 types of motors! *: When expanding to 32 bits, one type of motor can be controlled. Directly connectable to various memory types High-speed execution is enabled by storing the boot program to the Internal RAM!! 20

21 SH7201 Functions and Features Incorporates high-performance SH-2A core - CPU performance equivalent to the SH MIPS@120 MHz - High-speed response to interrupt processing On-chip register bank On-chip double-precision FPU - Realizes signal processing performance higher than the DSP - Enhances software development by the FPU (eliminates digit alignment processing) Abundant interfaces such as CAN and I 2 C-bus Rich set of bus interface - SDRAM interface - Burst ROM interface, etc. Internal peripheral functions for realtime control - Many on-chip timers: 16 bits 11 ch, motor control is possible - Ample analog input/output 10-bit A/D converter, 8-bit D/A converter 21

22 Overview of the SH7201 CPU core - SH-2A (SuperH RISC engine) FPU - 32-bit multiplier (32 bits 32 bits 64 bits) - Harvard architecture Operating frequency - CPU clock: 120 MHz (max.) - Bus clock: 60 MHz (max.) - Peripheral clock: 40 MHz (max.) Power-supply voltage to 3.6 V Internal memory - RAM: 32 KB - Instruction cache: 8 KB - Operand cache: 8 KB External memory interface - SRAM, SDRAM interface - External bus width is selectable from 8, 16 bits or 32 bits - External memory spaces can be divided into 7 areas (64 MB max.) Internal functions - Multi-functional 16-bit PWM timer: 6 (MTU2) - 8-bit timer (waveform output): 2 - Watchdog timer: 1 - CAN interface: 2 (2.0A, 2.0B) -I 2 C bus interface: 3 - DMA controller: 8 ch (includes 4 ch for external requests) - 10-bit A/D converter: 4 ch 2-8-bit D/A converter: 2 ch -SCIF: 8 (16-stage transmit/receive FIFO included) - I/O port: I/O: 116, Input: 8 - External interrupt pin: 17 -JTAG interface Package pin LQFP (24-mm square, 0.5-mm pitch) SH-2A 120 MHz JTAG FPU INTC interrupt controller UBC RTC MTU2 Instruction cache 8 KB 8-bit timer RAM 32 KB I/O 116 bits +8 bits WDT CAN Data cache 8 KB BSC ROM, SRAM/SDRAM SCIF A/D 10-bit 8 ch Functions newly added to the SH7206 Functions changed from the SH7206 DMAC I 2 C D/A 8-bit 2 ch 22

23 Industrial Measurement Device Application Example Using the SH phase PWM waveform required for inverter control System controller SH7201 Microcomputer SH-2A CPU 120 MHz DMAC FPU U-RAM 32 KB Network Monitor output MTU2 10-bit A/D converter 8-bit D/A converter CAN Serial interface I 2 C BSC memory interface Transmit/ receive Display microcomputer 16 bits Various control Instructions from host (1) On-chip MTU2 suitable for motor control (PWM waveform output, 2-phase encoder function, etc.) (2) On-chip CAN controller suitable for interface between industrial devices (3) On-chip FPU enables highly accurate current control DMAC I 2 C 23

24 Functions and Features of the SH7203 High-performance SH-2A core - Performance comparable to an SH-4 CPU 480 MIPS@200 MHz - Highly responsive interrupt processing incorporation of register banks Double-precision FPU - Better signal-processing performance than a DSP - Simpler development of software using FPU (matching digits is not required.) On-chip module for USB v.2.0 standard high-speed Host and Function operation - Large amount of data transferable at high-speed - Switching between Host and Function Liquid crystal display controller handles displays up to WVGA size ( pixels) Abundant communications interface functions -I 2 C, CAN, serial with FIFO, SPI-compliant serial, serial for sound Multifunctional timer for motor control, A/D converter, D/A converter 24

25 Overview of the SH7203 CPU core - SH-2A (SuperH RISC engine) FPU Operating frequency - CPU clock: 200 MHz (max.) - Bus clock: 66 MHz (max.) Power-supply voltage: dual power supply - Internal 1.2 V/external 3.3 V Internal memory - URAM: 64 KB - RAM with standby retention: 16 KB - Cache: I = 8 KB, D = 8 KB External memory interface - SRAM, SDRAM, PCMCIA interface - External data-bus width selectable as 8, 16, or 32 bits - External memory space can be divided into seven areas (64 MB max.) Internal functions - 16-bit multifunctional timer: 5 (MTU2) - 16-bit timer (CMT): 2 - Watch dong timer: 1 - CAN interfaces: 2 (2.0A, 2.0B) -I 2 C bus interfaces: 4 - DMA controller: 8 ch (includes 4 ch. that can be activated by external requests) - 10-bit A/D converter: 8 ch - SCIF: 4 (16-stage transmit/receive FIFO included) - SSI: 4 - SSU: 2 - USB2.0 (high speed): Host or Function selectable - NAND flash I/F - LCD controller - I/O ports -JTAG interface Package pin QFP SH-2A 200 MHz BSC ROM, SRAM, SDRAM, PCMCIA I 2 C: 4 Fast SCIF: 4 16-bit CMT: 2 SSI: 4 * Specifications are subject to change. FPU DMAC 8 ch MTU2: 5 A/D 10-bit: 8 ch Instruction cache: 8 KB INTC WDT D/A 8-bit: 2 ch Data cache: 8 KB NAND Flash I/F RTC LCDC : Function added to the SH7201 URAM 64 KB 16 KB SSU: 2 CAN: 2 USB2.0 H/F (HS): 1 25

26 SH7261 Functions and Features for Digital Audio Systems Using the SH-2A CPU (120 MHz performance) and FPU, decoding and encoding WMA, AAC, MP3, ATRAC3, etc. can be achieved by software - Eliminates external decoder chip - Multi-decoding is enabled Ripping an external USB memory or HDD player is possible - CPU encoding - Support for various encoder is in examination On-chip CD-ROM decoder - External components can be eliminated Various on-chip interfaces such as CAN and audio interface (SSI) 26

27 SH7261 Functional Outline CPU core - SH-2A (SuperH RISC engine) - On-chip 32-bit multiplier (32 bits 32 bits 64 bits) Operating frequency - CPU clock: 120 MHz (max.) - Bus clock: 60 MHz (max.) - Peripheral clock: 40 MHz (max.) Power-supply voltage to 3.6 V On-chip memory - RAM: 32 KB - Instruction cache: 8 KB - Operand cache: 8 KB External memory interface - SRAM, SDRAM interface - External bus width selectable from 8, 16, or 32 bits - External memory space can be divided into 7 (64 Mbytes max.) areas Internal functions - Multifunctional 16-bit PWM timer: 6 (MTU2) - 8-bit timer (waveform output): 2 ch - Watchdog timer: 1 - CAN interface: 2 (2.0A, 2.0B) -I 2 C bus interface: 3 - DMA controller: 8 ch (includes 4 ch which external request is enabled) - 10-bit A/D converter: 4 ch 2-8-bit D/A converter: 2 ch - SCIF: 8 (16-stage transmit/receive FIFO included) - SSI: 2 - CD-ROM decoder (Mode0/1/2/2Form1/2Form2) - I/O port: I/O: 116, Input: 8 - External interrupt pin: 17 -JTAG interface Package pin LQFP (24 mm square, 0.5-mm pitch) SH-2A 100/120 MHz I/O 116 bits + 8 bits JTAG UBC FPU INTC interrupt controller RTC MTU2 Instruction cache 8 KB WDT 8-bit timer RAM 32 KB CD-ROM decoder Functions added to the SH7206 SSI CAN Functions changed from the SH7206 Data cache 8 KB BSC ROM, SRAM/SDRAM SCIF A/D 10-bit 8 ch DMAC I 2 C D/A 8-bit 2 ch 27

28 Configuration Example of Digital Home Audio System Using the SH7261 Supporting USB Memory System controller SH7261 microcomputer Tuner CD driver SH-2A CPU/FPU 100/120 MHz U-RAM 32 KB CD-ROM decoder SSI SCIF Audio D/A converter LCD panel Playing Portable audio player CD-DSP/ Servo SSI A/D converter Key input I 2 C INT Remote controller Multi-codec by software Audio codec library* WMA/MP3/AAC BSC memory interface 16 bits USB Host M66596 Hi-Speed host 1-to-1 communications USB memory SDRAM Flash memory (1) Music playback from USB device Uncompress and playback compressed audio sound within USB memory or portable players (2) CD ripping to USB device Compress music CD data, and store them in USB memory or portable audio players 28

29 SH7263 Functions and Features for Digital Audio Systems High-performance SH-2A core - Performance comparable to an SH-4 CPU 480 MIPS@200 MHz - Highly responsive interrupt processing incorporation of register banks Double-precision FPU - Better signal-processing performance than a DSP - Decoding and encoding of WMA, AAC, and MP3 realizable in software On-chip module for USB v.2.0 standard high-speed Host and Function operation - Large amount of data transferable at high speeds - Switching between Host and Function Liquid crystal display controller handles displays up to WVGA size ( pixels) Abundant communications interface functions -I 2 C, CAN, serial with FIFO, SPI-compliant serial, serial for sound Internal functions for digital audio - CD-ROM decoder, sampling-rate converter, SD-card interface 29

30 Functional Overview of the SH7263 CPU core - SH-2A (SuperH RISC engine) FPU Operating frequency - CPU clock: 200 MHz (max.) - Bus clock: 66 MHz (max.) Power-supply voltage: dual power supply - Internal 1.2 V/external 3.3 V Internal memory - URAM: 64 KB - RAM with standby retention: 16 KB - Cache: I = 8 KB, D = 8 KB External memory interfaces - SRAM, SDRAM, PCMCIA interface - External data-bus width selectable as 8, 16, or 32 bits - External memory space can be divided into seven areas (64 MB max.) Internal functions - 16-bit multifunctional timers: 5 ch (MTU2) - 16-bit timers (CMT): 2 - Watchdog timer:1 - CAN interfaces: 2 (2.0A, 2.0B) -I 2 C bus interfaces: 4 - DMA controller: 8 ch (includes 4 ch that can be activated by external requests) - 10-bit A/D converter: 8 ch -SCIF: 4 (16-stage transmit/receive FIFO included) - SSI: 4 - SSU: 2 - SRC (sampling-rate converter) - USB2.0 (high-speed): Host or Function selectable - SD-card interface - NAND flash I/F - CD-ROM decoder Internal functions - LCD controller (equivalent to that of the SH7760) - I/O ports -JTAG interface Package pin QFP * Specifications are subject to change. SH-2A 200 MHz BSC ROM, SRAM, SDRAM, PCMCIA I 2 C: 4 Fast SCIF: 4 A/D 10-bit 8 ch 16-bit CMT: 2 SSI: 4 D/A 8-bit 2 ch FPU DMAC 8 ch MTU2: 5 CAN: 2 CD-ROM DEC : Function added to the SH7261 Instruction cache: 8 KB INTC WDT SSU: 2 LCDC : Function changed from the SH7261 Data cache: 8 KB PIO RTC URAM 64 KB 16 KB SRC NAND Flash I/F USB2.0 HOST/FUNC (HS): 1 IE-Bus SD card IF 30

31 Using the SH7263 for a USB-Supporting Audio System HDD SH7263 SH-2A CPU/FPU 200 MHz PCMCIA SSI Tuner Audio D/A converter CD driver Flash (option) Multi-codec in software NAND Flash CD-DSP /servo NAND I/F URAM 64 KB SSI I 2 C CD-ROM decoder SRC A/D converter Audio codec library(*) WMA/MP3/AAC 16 bits DMAC LCDC USB 2.0 BSC Memory interface SDRAM INT Flash memory Playing... Key input Remote controller Hi-Speed Host for 1-to-1 communications LCD panel Portable audio player USB memory (1) Music playback from USB devices Decompress and playback compressed audio data from USB memory or portable players. (2) Ripping CDs to USB devices Compress music CD data and store them in USB memory or portable players. 31

32 Summary of the SH2A-DUAL Platform AMP: Asymmetric multiprocessor Application of the multi-layer bus (MLB), designed with an emphasis on low latency - Bus configuration with four independent layers: two for CPU use as bus masters, two for the DMAC - Two CPUs to act as the two bus masters - The MLB has been widely used as a standard bus for SoC (system on chip). On-chip SH2A-FPU (200 MHz) CPU cores suit embedded control systems. - The FPUs handle signal processing and calculations for industrial, music, and other applications. - Concomitant usage of URAM draws out greater effective performance. - Register banks enable faster response. Configurations that include internal flash memory will be available. Dual ITRON and debuggers We are working towards even better performance and power consumption. 32

33 Functional Overview of the SH7205 Applications - Equipment and devices for industrial and general uses Abundant peripheral functional modules 1. Supports various storage interfaces (ATAPI/NAND flash/usb 2.0) 2. On-chip 2D engine (input of digital video, output of analog RGB) 3. On-chip multi-functional timers: Facility for motor control Package: 272-pin BGA (ball-grid array) SH-2A (200 MHz) SH-2A (200 MHz) BSC ROM, SRAM, SDRAM FPU FPU DMAC Instruction cache: 8 KB Instruction cache: 8 KB URAM: 32 KB Data cache: 8 KB Data cache: 8 KB URAM: 64 KB MTU2: 5 INTC SSI: 6 ATAPI CAN: 2 10-bit A/D Converter: 8 RTC WDT SSU: 2 NAND Flash IF 2D Graphics USB 2.0 HOST (HS) 2 ports/ FUNC (HS) 1 port SCIF: 6 I 2 C 33

34 Functional Overview of the SH7265 Applications - Digital on-board equipment for vehicles, including car audio and car navigation systems Functional modules added to those of the SH SD-card interface 2. IE Bus 3. Handling of compressed music files (AAC format) Encoding accelerator Support for vehicle product quality (-40 to 85 C) Package 272-pin BGA (Ball Grid Array) SH-2A (200 MHz) SH-2A (200 MHz) BSC ROM, SRAM, SDRAM MTU2: 5 10-bit A/D Converter: 8 INTC WDT FPU FPU DMAC SSI: 6 NAND Flash IF Instruction cache: 8 KB Instruction cache: 8 KB URAM 32 KB SCIF: 6 SD Card IF Data cache: 8 KB Data cache: 8 KB URAM 64 KB CAN: 2 USB 2.0 HOST (HS) : 2 ports/ FUNC (HS) : 1 port I 2 C RTC SSU: 2 2D Graphics AAC Enc. ATAPI IE Bus : Difference from the SH

35 Example of an Application for Music Playback and CD Encoding - A CD drives are connectable to the PC-ATA driver or the SSI interface (4 read CD-ROM drive). - I/O functions for video allow for display of external video. - Two USB 2.0 (HS) ports are available RGB RGB ATA AAC Encoder I 2 C SH-2A CPU/FPU 200 MHz 2D Graphics A/D A2D IC Touch panel 2 Ports USB TFT Monitor QVGA SD IF Video SH-2A CPU/FPU 200 MHz IIS (SSI) USB 2.0 (HS) Bus I/F ROM, SRAM, SDRAM USB Connector USB Connector Hub Hub D/A Flash Decompression and playback of compressed audio data: the SH-2A CPU is capable of decompressing and playing back compressed audio data in several formats (MP3/WMA/AAC codecs are available). Compression of audio data: The SH-2A CPU can handle software compression (MP3/AAC) or use the AAC encoder. SDRAM 35

36 Features of the SH7262 and SH7264 SH7262/SH7264 On-chip large-capacity SRAM (1 MB/640 KB) - Reducing requirements for external SDRAM facilitates reducing numbers of parts and system costs. - For display sizes up to WQVGA, the SRAM is capable of holding dual frame buffers. - External SDRAM is still connectable. USB2.0 and graphics functions - Products incorporate a USB controller for High-Speed USB2.0 and a display controller that handles video input. Abundant peripheral functions - Inclusion of on-chip peripheral functions such as the FPU, CAN, MTU2, and PWM timers for motor control makes the products suitable for industrial applications. - Flash memory (NOR, NAND, serial flash memory etc.) is connectable. 36

37 Outline of the SH7262 Specifications SH7262 CPU: SH2A-FPU (SuperH RISC engine) Frequency: CPU 144 MHz/External bus 72 MHz (max.) Power: Internal 1.2 V/External 3.3 V Internal Memory - URAM: 64 KB - SRAM: 1 MB (includes standby RAM: 32 KB) 640 KB (includes standby RAM: 320 KB) - Cache: Instruction = 8 KB, data = 8 KB External memory interface - SRAM, NOR-type flash memory, SDRAM, PCMCIA - Bus width: 8 or 16 bits, memory space: 64 MB (max.) Peripheral modules - DMAC: 16 ch - USB host/function: 1 - Multi function timer (MTU2): 5-16-bit timer (CMT): 2-10-bit PWM timer: 16 - Watchdog timer (WDT): 1 - Real-time clock (RTC): 1 -I 2 C bus interface: 3 - Serial communication interface with FIFO (SCIF): 8 - Renesas serial peripheral interface (RSPI): 2 - Clock synchronous serial interface with FIFO (SIOF): 1 - RCAN: 2 (option) - Video display controller (VDC3): D-RGB (up to WQVGA) Video IN (BT. 656) - NAND-type flash memory controller - Serial sound interface (SSI): 4 - SPDIF: 1 - Sample rate converter (SRC): 2 - CD-ROM decoder - 10 bit A/D converter: 4 ch - Decompression unit 37 Peripheral modules - SD card host interface (SDHI): 1 - IEBus: 1 (option) Package pin QFP SH2A-FPU: 144 MHz BSC SRAM, NOR, SDRAM, PCMCIA I 2 C: 3 SCIF: 8 10-bit A/D Converter: 4 ch CMT: 2 MTU2: 5 SSI (I2S): 4 SPDIF: 1 RSPI: 2 Inst. cache: 8 KB DMAC: 16 ch 10 bit PWM: 16 CAN: 2 CD-ROM decoder Data cache: 8 KB URAM: 64 KB Under Development SRAM: 1 MB or 640 KB INTC PIO SRC: 2 WDT SIOF: 1 RTC USB2.0 host /func. VDC3 Video In (BT.656) Display cnt. (D-RGB) NAND flash I/F SDHI IEBus: 1 De- Compress Unit Functionality added to that of the current product (SH7263) Option

38 Outline of the SH7264 Specifications SH7264 CPU: SH2A-FPU (SuperH RISC engine) Frequency: CPU 144 MHz/external bus 72 MHz (max.) Power: Internal 1.2 V/external 3.3 V Internal Memory - URAM: 64 KB - SRAM: 1 MB (includes standby RAM: 32 KB) 640 KB (includes standby RAM: 320 KB) - Cache: Instruction = 8 KB, data = 8 KB External memory interface - SRAM, NOR-type flash memory, SDRAM, PCMCIA - Bus width: 8 or 16 bits, memory space: 64 MB (max.) Peripheral modules - DMAC: 16 ch - USB host/function: 1 - Multi-function timer (MTU2): 5-16-bit timer (CMT): 2-10-bit PWM timer: 16 - Watchdog timer (WDT): 1 - Real-time clock (RTC): 1 -I 2 C bus interface: 3 - Serial communication interface with FIFO (SCIF): 8 - Renesas serial peripheral interface (RSPI): 2 - Clock synchronous serial interface with FIFO (SIOF): 1 - RCAN: 2 (option) - Video display controller (VDC3): D-RGB (up to WQVGA) Video IN (BT. 656) - NAND-type flash memory controller - Serial sound interface (SSI): 4 - SPDIF: 1 - Sample rate converter (SRC): 2 - CD-ROM decoder - 10-bit A/D converter: 8 ch - Decompression unit Peripheral modules - SD card host interface (SDHI): 1 - IEBus: 1 (option) Package pin QFP SH2A-FPU 144 MHz BSC SRAM, NOR, SDRAM, PCMCIA I 2 C: 3 SCIF: 8 10-bit A/D Converter: 8 ch CMT: 2 MTU2: 5 SSI (I2S): 4 SPDIF: 1 RSPI: 2 Inst. cache: 8 KB DMAC: 16 ch 10-bit PWM: 16 CAN: 2 CD-ROM decoder Data cache: 8 KB INTC WDT SIOF: 1 URAM: 64 KB PIO RTC USB2.0 host /func. VDC3 Video In (BT.656) Display cnt. (D-RGB) Under Development SRAM: 1 MB or 640 KB SRC: 2 NAND flash I/F SDHI IEBus: 1 De- Compress Unit Functionality added to that of the current product (SH7263) Option 38

39 Fields of Application SH7262/SH7264 Digital audio devices In-vehicle devices with USB, mini-and micro-component audio systems, ipod * accessories, etc. Graphical dashboards In-vehicle information panels, displays on AV centers, etc. Office automation and industrial equipment Copying machines, printers,etc. AC servomotors, general-purpose inverters, robots, sequencers,etc. *: ipod is a trademark of Apple Inc., registered in the U.S. and other countries. 39

40 Development Concepts of SH7080 Series Various features to achieve high-end embedded systems Usage : Printers, DVD recorders, fax machines, AC servo motors, and inverters for industrial use. Feature 1 With on-chip high-speed flash memory and 80-MHz/104-MIPS high-performance CPU arithmetic operation Achieves high-performance control Feature 2 Upper model of SH7040/7144 Series and 3.3-V or 5-V single-power supply No need of external regulators Feature 3 Bus extension function and improved PWM timer, high-speed A/D converter (2.5 μs/ch) *1 Peripheral functions suitable for machine and system controls Feature 4 On-chip debugging function, full spec. ICE, and JTAG-ICE are available. Reasonable development tools *1: Pφ =20 MHz 40

41 Overview of the SH7080 CPU core - SH-2 (SuperH RISC engine) - 32-bit multiplier (32 bits 32 bits 64 bits) Operating Frequency - CPU clock: 80 MHz (max.) - External bus clock: 40 MHz (max.) - Peripheral clock: 40 MHz (max.) - Clock dedicated for MTU2S: 80 MHz (max.) Power Supply -3.3 ±0.3 V or 5.0 ±0.5 V (5.0 ±0.5 V for analog supply) Internal Memory [ROM/RAM] - Flash version [512 KB/32 KB]: SH7083/84/85/86, [256 KB/16 KB]: SH7083/84/85 - Mask version [256 KB/16 KB]: SH7083/84/85 - ROM less version [RAM: 16 KB]: SH7083/84/85 External Memory Interface - SRAM, SRAM with byte selection, multiplex I/O - SDRAM, PCMCIA, burst ROM *1 Internal Functions - Multi-function 16-bit PWM timer: 6 (MTU2), 3 (MTU2S) - Port output enable (POE) - 16-bit cyclic timer: 2 - Watchdog timer: 1 -I 2 C bus interface: 1 *2 - Synchronous serial interface unit: 1 - DMA controller: 4 ch - DTC (simple DMA controller) - High-speed 10-bit A/D converter: 4 ch 2 (SH7083/84/85) 4 ch ch (SH7086) - SCI: 4 (1 ch for 16-stage transmit and receive FIFO) Internal Functions - I/O port: 73 (SH7083), 84 (SH7084), 108 (SH7085), 134 (SH7086) - External interrupt pins (NMI+IRQ): 9 - On-Chip Debugging function (H-UDI) Packages - SH7083 (100-pin): TQFP (14 mm square, 0.5-mm pitch) - SH7083 (BGA): P-LFBGA (112 pin, 10 mm square) - SH7084 (112-pin): LQFP (20 mm square, 0.65-mm pitch) -SH7085 (144-pin) LQFP (20 mm square, 0.5-mm pitch) -SH7086 (176-pin) LQFP (24 mm square, 0.5-mm pitch) Bus interface SH-2 80 MHz SCI 10-bit A/D converter Internal ROM Internal RAM 32-bit multiplier MTU2 MTU2S DMAC/DTC CMT WDT *1: Supported only at 3.3-V operation, and not supported at 5.0-V operation. *2: SH7083 is not supported. I 2 C Port 41

42 Development Concepts of SH7146 Series Various features suitable for high-performance motor control. Usage : Invertors for consumer electronics such as air-conditioning outside equipment and washing machine, invertors for general use, and devices for industrial use. Feature 1 With on-chip high-speed flash memory and 80-MHz and 104-MIPS high-performance CPU arithmetic operation Achieves vector and PAM controls in a single chip Feature 2 Feature 3 Enhanced usability by 5-V single power supply Improved two-way PWM timers Three high-speed A/D converters (2.5 μs/ch) *1 Realizes one-shunt vector control. Controls fan motor and compressor in a single chip Feature 4 On-chip debugging functions: Full spec. ICE and JTAG-ICE Reasonable development tools *1: Pφ =20 MHz 42

43 SH7146 Series Overview CPU core - SH-2 (SuperH RISC engine) - 32-bit multiplier (32 bits 32 bits 64 bits) Operating Frequency - CPU clock: 80 MHz (max.) - Bus clock: 40 MHz (max.) - Peripheral clock: 40 MHz (max.) - Clock dedicated for MTU2S: 80 MHz (max.) Power Supply Voltage -4.0-to 5.5-V single power supply Internal Memory [ROM/RAM] - Flash version [256 KB/8 KB]: SH7146/SH Mask version [256 KB/8 KB]: SH7146/SH7149 External Memory Interface *1-8-/16-bit external bus, SRAM I/F Internal Functions - Multi-functional 16-bit PWM timer: 6 (MTU2), 3 (MTU2S) - Port output enable (POE): 9 - Watchdog timer: 1 - High-speed 10-bit A/D converter: 2 ch ch (A total 12 ch) - DTC (simple DMA controller) *2 - SCI: 3 - I/O ports: 57 (SH7146), 75 (SH7149) Internal Functions - External interrupt pins (NMI+IRQ): 5 - On-Chip Debugging function (H-UDI) *2 - AUD function: Available only in the flash-memory version (SH7149) supporting full functions of the E10A for evaluation. Packages - SH7146 (80-pin): LQFP80 (14 mm square, 0.65-mm pitch) - SH7149 (100-pin): LQFP100 (14 mm square, 0.5-mm pitch) Bus interface SH-2 80 MHz SCI 10-bit A/D converter Internal ROM 256 KB Internal RAM 8 KB 32-bit multiplier MTU2 MTU2S CMT WDT Port *1: For external memory Interface, only SH7149 is supported. SH7146 is not supported. *2: Not available in Mask-ROM versions. 43

44 Development Concept of SH7125 Series Various features to realize small high-performance motor control system. Usage : Invertors for consumer electronics such as refrigerators and vacuum cleaners, and motor control devices such as pumps, fans, and compressors. Feature 1 32-bit RISC-engine microcomputer in a small package: 64 pins/48 pins Feature 2 50-MHz and 65-MIPS high-performance CPU arithmetic operation Much higher-performance of CPU compared to that of 8-bit/16-bit CPU Feature 3 Improved PWM timers: Two high-speed A/D converters (2 μs/ch) Achieves one-shunt vector control Feature 4 On-chip debugging functions: Full spec. ICE and JTAG-ICE Reasonable development tools 44

45 SH7125 Series Overview CPU core - SH-2 (SuperH RISC engine) - 32-bit multiplier (32 bits 32 bits 64 bits) Operating Frequency - CPU clock and peripheral I/O clock: 50 MHz, 25 MHz or 40 MHz, 40 MHz Power Supply Voltage to 5.5-V single power supply Internal Memory (flash memory, RAM) - Flash memory: 128 KB/64 KB/32 KB/16 KB - RAM: 8 KB/4 KB Internal Functions - Multi-functional 16-bit PWM timer: 6 (MTU2) - Port output enable (POE) - Watchdog timer: 1 - High-speed 10-bit A/D converter: 4 ch 2 (total 8 ch) -SCI: 3 - I/O ports: 33 (SH7125), 26 (SH7124) - External interrupt pins (NMI + IRQ): 4 (SH7124), 5 (SH7125) - On-Chip Debugging function (H-UDI) * Packages - SH7125 (64-pin): LQFP-64 (10 mm square/0.5-mm pitch), QFP-64A (14 mm square/0.8-mm pitch), VQFN-64 (8 mm square/0.4-mm pitch) - SH7124 (48-pin): LQFP-48 (10 mm square/0.65-mm pitch) VQFN-52 (7 mm square/0.4-mm pitch) SH-2 50 MHz Flash ROM RAM 10-bit A/D converter Note *: The function is not included in the 32- and 16-KB ROM versions. 32-bit multiplier MTU2 CMT WDT SCI 45

46 Development Concepts of SH7147 Series Various features suitable for high-performance motor control. Usage: Power steering systems, hybrid electric vehicles, general-purpose inverters, inverter control of AC servo, etc. Feature 1 Feature 2 80-MHz and 104-MIPS high-performance CPU arithmetic operation Single-cycle access to high-speed flash memory at 80 MHz Achieves vector control of a motor Feature 3 Peripheral functionality dedicated for motor control A 12-bit resolution A/D converter enables simultaneous sampling of all phases of a three-phase motor. Timers for a three-phase motor (Multi-function timer pulse unit 2 and Multi-function timer pulse unit 2S) A single chip can control two three-phase brushless motors. Feature 4 Abundant communications interface functions (RCAN-ET, Synchronous Serial Communication Unit, Serial Communication Interface) 46

47 Overview of SH7147 Series CPU core - SH-2 (SuperH RISC engine) - 32-bit multiplier (32 bits 32 bits 64 bits) Operating Frequency - CPU clock: 80 MHz (max.) /64 MHz (max.) *1 - Bus clock: 40 MHz (max.) /32 MHz (max.) *1 - Peripheral clock: 40 MHz (max.) /32 MHz (max.) *1 - Clock dedicated for Multi-function timer pulse unit 2S: 80 MHz (max.) /64 MHz (max.) *1 Power-Supply Voltage - 80-MHz/5.0-V single power supply - 64 MHz/3.3 V (internal), 5.0 V (I/O, analog power supply) *1 Internal Memory - Flash memory: 256 KB/384 KB/512 KB - Internal RAM: 16 KB/12 KB External Memory Interface - 8-bit external bus, SRAM interface Internal Functions - 16-bit multifunctional PWM timer: 5 (Multi-function timer pulse unit 2), 3 (Multi-function timer pulse unit 2S) - Port output enable (POE) - Advanced user debugger (RAM-monitoring function) - Data transfer controller (simplified DMA controller) - Synchronous serial interface unit (SSU): 1 - Serial communications interface: 3 Internal Functions - High-speed, 12-bit A/D converter: 8 ch 2 (total 16 ch) - Controller Area Network (RCAN-ET) - Watchdog timer: 1 - I/O ports: 57 - External interrupt pins (including NMI): 5 Package - LQFP (14-mm square, 0.5-mm pitch) Target Applications Automobile field: power steering systems, inverter control of hybrid electric vehicles Industrial field: general-purpose inverters, AC servo motors SH-2: 80 MHz/64 MHz* 1 SCI 12-bit A/D converter Internal ROM: 256 KB Internal RAM: 16 KB/12 KB * 1 32-bit multiplier MTU2 MTU2S CMT WDT AUD DTC SSU RCAN-ET UBC Note) *1: temperature range (-40 to 125 C) 47

48 Development Concepts of the SH7137 Various features to adapt to high-performance motor control system Applications: Inverters, AC servo motors, manipulators, measuring equipment, etc. for industrial use Feature 1: Feature 2: Feature 3: Feature 4: Feature 5: High-performance CPU arithmetic operation at 80 MHz/104 MIPS Single-cycle access to high-speed flash memory at 80 MHz On-chip peripheral functional modules dedicated for motor control A 12-bit resolution A/D converter enables simultaneous sampling of all phases of a three-phase motor. On-chip timer for a three-phase motor (MTU2 and MTU2S) Abundant communications interface functions (RCAN-ET, SSU, SCI) On-chip debugging functions Full ICE and JTAG-ICE are available. Vector control of a motor is enabled. A single chip can control two 3-phase brushless motors. Reasonable development tool 48

49 Functional Outline of the SH7137 CPU core - SH-2: SuperH RISC engine Operating frequency - CPU clock: 80 MHz (max.) - Bus clock: 40 MHz (max.) - Peripheral clock: 40 MHz (max.) Power-supply voltage -3.3 V±0.3 V or 5.0 V±0.5 V Single-power supply (AVcc = 5.0 V±0.5 V) On-chip memory KB Flash memory - 16-KB RAM External memory interface - SH7136: None - SH7137: External bus width is 8 bits. Internal peripheral function - Multi-functional 16-bit PWM timer: 6 (MTU2), 3 (MTU2S) - Port output enable (POE) - Compare match timer (CMT): 2 - Watchdog timer (WDT): 1 - Data transfer controller (DTC) - Serial communications interface (SCI): 3 - Synchronous communications interface (SSU): 1 -I 2 C bus interface: 1 -RCAN-ET: 1 - A/D converter: 12 bits 16 ch (SH7137), 12 bits 12 ch (SH7136) On-chip debugging function - H-UDI - User break controller (UBC) Packages - SH7136: LQFP (14-mm square, 0.65-mm pitch) - SH7137: LQFP (14-mm square, 0.5-mm pitch) SH-2 80 MHz UBC H-UDI BSC* SRAM I 2 C: 1 SSU: 1 RAM 16 KB Flash ROM 256 KB WDT DTC SCI: 3 I/O Ports INTC MTU2 (16 bits 6) MTU2S (16 bits 3) CMT (16 bits 2) 12-bit A/D converter RCAN Note *: Only available for SH

50 SH7144 Series Overview Features CPU core - SH-2 with an operating frequency of 50 MHz, 3.0 to 3.6 V operation - 32-bit multiplier (32 bits 32 bits 64 bits) Internal memory - ROM: 256 KB (Flash/Mask/ROMless) -RAM: 8 KB Internal functions - Multi-functional 16-bit timer (MTU): 5 - Internal DMAC and DTC - External bus: 8/16/32 bits - A/D converter: 10 bits, 8 ch (4 ch 2 units) -SCI: 4 -I 2 C: 1 Package - QFP-112 (SH7144)/LQFP-144 (SH7145) SH7144 Series Block Diagram Bus interface SH-2 50 MHz 32-bit multiplier MTU 16-bit 5 A/D 10-bit 8 ch SCI 4 Internal ROM Flash/Mask Internal RAM WDT DTC CMT DMAC 4 ch Port Main areas of application Digital consumer appliances, OA equipment industrial use 50

51 SH7046 Overview - Single-Chip Microcomputer in a Small Package - Features CPU core - SH-2 (Renesas s original SuperH 32-bit RISC) - Max. operating frequency: to 5.5-V operation - 32-bit multiplier (32 bits 32 bits 64 bits) (The SH7101: 40 MHz) Internal functions - Powerful 16-bit timer (MTU, MMT) - Enables output of a max. 15-phase PWM waveform - Built-in DTC - A/D converter: 10 bits, 12 ch (4 ch 3 units) - SCI: 2 (SH7101: Without MMT and DTC 8 channel A/D converter (4 ch 2 units)) Main applications White ware goods with inverters such as air conditioners, washing machines, and refrigerators, and industrial applications such as inverters, AC servos, FA, UPS, and FA sequencers SH7046 Block Diagram SH-2 50 MHz 32-bit multiplier MTU MMT 10-bit A/D SCI 2 SH7046F (Flash Version) SH7104 (Mask Version)* SH7048 (Mask Version) SH7108 (Mask Version)* SH7148 (Mask Version) SH7106 (Mask Version)* SH7101 (Mask Version)** 80-pin QFP Internal ROM Flash/Mask Internal RAM WDT DTC CMT ROM 256 KB 256 KB 128 KB 128 KB 64 KB 64 KB 32 KB RAM 12 KB 8 KB 4 KB 4 KB 4 KB 4 KB 2 KB *: Without DTC **: Without DTC and MMT 51

52 SH7047 Overview - Microcomputer with a Built-in CAN Bus Interface - Features CPU core - SH-2 (Renesas original SuperH 32-bit RISC) - Max. operating frequency: 50 to to 5.5-V operation - 32-bit multiplier (32 bits 32 bits 64 bits) Internal functions - Powerful 16-bit timer (MTU, MMT) - Enables output of a max. 15-phase PWM waveform - Built-in DTC - A/D converter: 10 bits, 16 ch (8 ch 2 units) -SCI: 3 - HCAN2: 1 Main applications Automobile applications such as EPS and airbags, and industrial applications such as inverters, AC servo, FA, UPS, and FA sequencers SH7047 Block Diagram SH-2 32-bit multiplier MTU MMT 10-bit A/D SCI pin QFP SH7047F (Flash Version) SH7049 (Mask Version) SH7105 (Mask Version)* SH7109 (Mask Version)* SH7107 (Mask Version)* Internal ROM Flash/Mask Internal RAM WDT DTC CMT HCAN 2 ROM RAM 256 KB 12 KB 128 KB 8 KB 256 KB 8 KB 128 KB 4 KB 64 KB 4 KB * SCI: 2, Without DTC 52

53 SH7040 Series Overview Features SH-2 core high-performance single-chip RISC - 37 MIPS/28.7 MHz - Built-in 32-bit multiplier Built-in large-capacity memory - ROM: 64 KB (mask)/128 KB (mask, OTP)/ 256 KB (mask, Flash)/ROMless - RAM: 4 KB (can be used as 1-KB cache + 2-KB RAM) Built-in cache memory - 1-KB instruction cache, 256 entries, and direct mapping Various peripheral functions - Powerful timer: MTU, 2-ch compare-match timer - A/D converter: 10 bits 8 ch - Serial interface: 2 -DMAC: 4 ch Products lineup (ROMless type is also available) ROM size Package SH7040 Series Block Diagram Bus interface SH-2 CPU Multiplier Timer 16-bit 7 A/D 10-bit 8 ch SCI 2 ROM 64 KB/128 KB 256 KB Selectable Cache 1 KB RAM 2 KB RAM 4 KB CPG WDT DMAC 4 ch Port SH7040/42/44 SH7041/43/45 64 KB/128 KB/256 KB QFP KB/128 KB/256 KB QFP-144 Note: SH7042 (3.3-V Version): TQFP-120 Main applications Motor controls, navigation systems, digital cameras, PPCs, printers, faxes, and JPEG application system 53

54 SH7014, SH7016, and SH7017 Overview Features High-performance single-chip RISC with SH-2 core - 37 MIPS/28.7 MHz/5 V - Built-in 32-bit multiplier Built-in memory - ROM: 64 KB (Mask)/128 KB (Flash)/ROMless - RAM: 3 KB/4 KB (can be used as 1-KB cache + 1-KB/2-KB RAM) Built-in cache memory - 1-KB instruction cache, 256 entries, and direct mapping Peripheral functions - Powerful timer: 16 bits 5 (MTU: 0-2, CMT: 2) - A/D* converter: 10 bits 8 ch - Serial interface: 2 -DMAC: 2 ch Product lineup ROM size RAM Package SH KB QFP-112 SH KB (Mask) 3 KB QFP-112 SH KB (Flash) 4 KB QFP-112 f/v 28.7 MHz/5 V Bus interface SH7017F Block Diagram SH-2 CPU Multiplier Timer 16-bit 5 A/D 10-bit 8 ch SCI 2 ROM Flash: 128 KB Selective Cache: 1 KB RAM: 2 KB RAM 4 KB CPG WDT DMAC 2 ch Port Main applications Video printers, liquid crystal projectors, Scanners, and electronic musical instruments, etc. *: A/D module is different between SH7014 and SH7016/17 54

55 SH7020 and SH7030 Series Overview - Another Low Price ROMless Version is Added to the Lineup - Features 32-bit single-chip RISC with high-performance - 26 MIPS/20 MHz Built-in 16-bit multiplier Various built-in large-capacity memories - ROM: 64 KB/32 KB/16 KB/ROMless - RAM: 8 KB/4 KB/1 KB Various built-in peripheral functions - 16-bit timer, A/D converter, DMAC, SCI, INTC, Bus state controller (BSC), etc Package - TQFP-120, QFP-112, and TQFP-100 Product lineup - 5 types (ROMless Versions for the SH7034 and SH7020 also available) SH7032 SH7034 SH7034B ROM/RAM A/D Package -/8 KB 64 KB/4 KB -/4 KB Yes Yes Yes SH KB/1 KB - SH KB/1 KB - QFP-112 TQFP-120 TQFP-100 BSC SH7034 Block Diagram SH-1 CPU Multiplier Timer 16-bit 5 A/D 10-bit 8 ch SCI 2 ROM (OTP/Mask) 64 KB RAM 4 KB CPG WDT DMAC 4 ch Port Main applications Motor controls, FAs, navigation systems, HDDs, printers, faxes, digital cameras, etc 55

56 SH7065 Overview - High-Performance Single-Chip RISC Microcomputer with a Built-in Large-Capacity Flash Memory - Features SH-core (with an enhanced DSP function) high-performance single-chip RISC - 60 MHz/3.3 V - All SH-2 instructions + DSP-function enhanced instructions (SH2-DSP core) Built-in large-capacity memory - ROM: 256 KB (Flash/Mask) - RAM: 8 KB (X-RAM: 4 KB, Y-RAM: 4 KB) Powerful peripheral functions - Timers: TPU (6) + CMT (2) + MMT (1) - A/D converter: 10 bits 4 ch 2 units - D/A converter: 8 bits 2 ch - SCIF: (FIFO) 3 -DMAC: 4 ch - INTC (interrupt controller), WDT etc Bus state controller (BSC) - Directly connected with ROM/SRAM/DRAM/EDO Power management unit - Can be switched between the CPU, internal peripheral, and external bus clock - Module standby function Endian switching of external data available Package - LQFP-176 (24 mm 24 mm, 0.5-mm pitch) BSC SH7065 Block Diagram SH2-DSP CPU DMAC: 4 ch SCIF: 3 INTC WDT Timer 16-bit 8 MMT ROM: 256 KB (Flash/Mask) RAM: 8 KB D/A converter 8-bit 2 ch A/D converter 10-bit 8 ch I/O port PLL Main applications MFPs, high-performance digital cameras, digital video cameras, DVD systems, communication terminals, and industrial controllers 56

57 SuperH with Built-in Ether 57

58 SH-Ether Overview The SH-Ether Series products are the SuperH microcomputers equipped with the 10/100-Mbps supporting Ethernet controllers in compliance with the IEEE802.3u standard. Target applications - LBPs (Laser Beam Printer), MFPs (Multi Function Printer) - LAN cards (PC peripherals, FA devices) - Digital home electronics, IP Phones - Amusement devices - POS systems - Monitoring systems - Others (The Ethernet required systems) Adopted for various embedded Ethernet systems 58

59 SH-Ether Roadmap High Performance SH-Ether 200 MHz SH7710 (SH3-DSP) Ether: 2 IPsec SH7712 (SH3-DSP) IPsec-less SH7713 (SH3-DSP) Ether: 1 SH7763 (SH-4A) GbEther: 2 PCI, IPsec SH7764 (SH-4A) Ether: 1 USB2.0 2D Graphic Planning UD MP Single-chip solution Simple-Ether 62.5 MHz SH7615 (SH2-DSP) SH7616 (SH2-DSP) 100 MHz SH7618 (SH-2) HIF 125 MHz SH7619 (SH-2) PHY 133 MHz SH7650 (SH-2) DTCP-IP equipped 200 MHz SH7652 (SH-2A) SH7670/71/72/73 (SH-2A) Ether: 1 USB2.0 DTCP-IP equipped FIFO: 512 B FIFO: 2 KB 59

60 SH7615 Overview Features High performance RISC engine SuperH core (SH2-DSP) - 81 MIPS, 125 MOPS MHz Instruction/data combination type cache (4 KB) - 4-way set associative, 64 entries, 16-byte line length Internal RAM (8 KB) SDRAM Interface - Supports high-speed access: external bus CPG to 62.5 MHz (max.) PLL - Possible 16 Byte DMA dual burst access Ethernet controller INTC (MAC *1 : accordance with IEEE802.3u) - transmission rate: 10/100 Mbps, Full duplex transmit and receive - Assembles/Disassembles data frame, CRC - Supports MII *2, Magic packet *3 - FIFO 512 Byte each for transmission and reception Boundary Scan - Boundary Scan Function (accordance with IEEE1149.1) Peripheral function - TPU (3), SCIF (2), DMAC (2), INTC, WDT (1), FRT (1), SIO (3), I/O port etc Vcc = 3.3 V (supports 5 V I/F regarding I/O and Ethernet pin) SH7615 Block Diagram SH2-DSP CPU 16-bit free-run timer WDT Bus-State Controller Cache memory 4 KB DMAC 2 ch SCI: 2 UBC: 4 RAM X: 4 KB Y: 4 KB Ether 10/100 SIO: 3 I/O port Ether FIFO = 512 B Package: QFP-208 / CSP-240 *1 MAC:Media Access Control, *2 MII:Media Independence Interface, *3 Magic Packet is a trademark of Advanced Micro Devices, Inc. 60

61 SH7616 Overview Features High performance RISC engine SuperH core (SH2-DSP) - 81 MIPS, 125 MOPS MHz Instruction/data combination type cache (4 KB) - 4-way set associative, 64 entries, 16-byte line length Internal RAM (8 KB) SDRAM Interface - Supports high-speed access: CPG external bus to 62.5 MHz (max.) PLL - Possible 16 Byte DMA dual burst access Ethernet controller (MAC *1 INTC : accordance with IEEE802.3u) - transmission rate: 10/100 Mbps, Full duplex transmit and receive - Assembles/Disassembles data frame, CRC - Supports MII *2, Magic packet *3 - FIFO 2 KB each for transmission and reception Boundary Scan - Boundary Scan Function (accordance with IEEE1149.1) Peripheral function - TPU (3), SCIF (2), DMAC (2), INTC, WDT (1), FRT (1), SIO (2), I/O port etc - SIO with FIFO (16 bits 16) for CODEC Vcc = 3.3 V (supports 5 V I/F regarding I/O and Ethernet pin) SH7616 Block Diagram SH2-DSP CPU 16-bit free-run timer WDT Bus-State Controller Cache memory 4 KB DMAC 2 ch SCI: 2 UBC: 4 Ether = 2 KB SIO with FIFO 1 ch Package: QFP-208 RAM X: 4 KB Y: 4 KB Ether 10/100 SIO: 1 w/fifo SIO: 2 I/O port *1 MAC: Media Access Control, *2 MII: Media Independence Interface, *3 Magic Packet is a trademark of Advanced Micro Devices, Inc. 61

62 Difference Between SH7615 and SH7616 FIFO (up to 2 KB) Possible one transaction per frame Improve the efficiency of transmission and reception of frames CAM match signal Multi Address support Useful for FA network SIOF (SIO with FIFO) Improve the efficiency of G.729a handling Support for CODEC having Communication Data e.g. Si 3000 (Silicon Laboratories), STLC7550 (SGS Thompson) 62

63 Overview of SH7618/7618A Specifications - Inexpensive network controller incorporating EtherMAC and host interface - CPU core - SH-2 (SuperH 32-bit RISC engine, 32-bit multiplier) - PVcc = 3.0 to 3.6 V, Vcc = 1.4 to 1.6 V Operating Frequency - CPU clock: 100 MHz - Bus clock: 50 MHz Internal Memory - RAM: 4 KB - Cache memory: 4 KB (Four-way set associative): KB (Four-way set associative): 7618A Host I/F - 1 KB 2 sections - HIF boot function Ethernet functions - EtherMAC (10/100 Mbps): 1 ch - MII is also available. - Transmit and receive FIFO: 256 bytes each (7618), 512 bytes each (7618A) - Dedicated DMA controller: 2 ch External Memory Interfaces - SRAM, SDRAM, and PCMCIA I/F - Switchable to big/little endian - External bus can be extended up to 16 bits Peripheral Functions - Serial communication interface: 3 Switchable to UART/clock synchronous 16-stage transmit and receive FIFO - 16-bit interval timer: 2 - Watchdog timer: 1 - General-purpose I/O port: 78 - JTAG interface support - External interrupt pins: 9 Package - CSP-176 (13 mm square, 0.8-mm pitch) SH MHz RAM: 4 KB Cache: 4 KB SCI (with FIFO): 3 Host interface Interval timer External bus interface EDMAC EtherMAC: 1 ch 63

64 Overview of SH7619 Specifications - PHY in a single chip improves performance - CPU core - SH-2 (32-bit SuperH RISC engine, 32-bit multiplier) - PVcc = 3.0 to 3.6 V, Vcc = 1.7 to 1.9 V Operating Frequency -CPU clock: 125 MHz - Bus clock: 62.5 MHz Internal Memory -RAM: 16 KB - Cache memory: 16 KB (4-way set associative) Host I/F - 1 KB 2 sections - HIF boot function Ethernet Functions - EtherMAC (10/100 Mbps): 1 ch - EtherPHY (10/100 Mbps): 1 (MII is also available) - Transmit and receive FIFO: 512 bytes each - Dedicated DMA controller: 2 ch External Memory Interface - SRAM, SDRAM, and PCMCIA - Switchable to big/little endian - External bus can be extended up to 32 bits General-Purpose DMA Controller -4 ch Peripheral Functions - Serial communication interface: 3 Switchable to UART/clock synchronous 16-stage transmit and receive FIFO - 16-bit interval timer: 2 - Watchdog timer: 1 - General-purpose I/O ports: 78 - JTAG interface support - External interrupt pins: 9 Package - CSP-176 (13 mm square, 0.8-mm pitch) SH MHz RAM: 16 KB Cache: 16 KB SCI (with FIFO): 3 Host interface Interval timer External bus interface E-DMAC/DMAC EtherMAC/PHY: 1 ch 64

65 SH7650 Functions and Features Incorporates high-performance SH-2 core - Realizes network processing and DTCP processing at 173 MIPS@133 MHz with no load on the main CPU On-chip functions supporting DTCP-IP * - Authentification between systems and encryption/decryption of contents are achieved by hardware and supplied firmware Internal PCI bus controller and host interface - Facilitates connection with the main CPU Includes wireless LAN interface and MPEG-TS port for moving image streaming Abundant bus interfaces - SDRAM interface - Burst ROM interface, etc. *: DTCP-IP standard is a standard for protecting contents on the IP network standardized by DTLA (Digital Transmission Licensing Administrator) 65

66 SH7650 Overview CPU core -SH-2 (SuperH 32-bit RISC, with on-chip 32-bit multiplier) - PVcc = 3.0 to 3.6 V, Vcc = 1.4 to 1.6 V Operating frequency -CPU clock: 133 MHz - Bus clock: 66 MHz Internal memory - Internal RAM: 8 KB - Cache memory: 16 KB On-chip DTCP-IP Host interface - 1 KB 2 banks - Includes HIF boot function PCI controller - 33 MHz/32 bits Ethernet controller - EtherMAC (10/100 Mbps): 1 ch - Includes MII - Transmit/receive FIFO: each 512 bytes - Dedicated DMA controller: 2 ch - Incorporates TCP/IP checksum accelerator Memory interface - SRAM, SDRAM interface - External bus can be extended up to 32 bits Encryption module - AES encryption/decryption - Dedicated DMA controller On-chip MPEG-TS interface - Includes 3 channels Peripheral functions - Serial communication interface: 2-16-bit interval timer: 2 - Support for JTAG interface, external interrupt pin, and I/O ports Package - CSP-336 (17-mm square, 0.8-mm pitch) SH MHz RAM: 8 KB Cache: 16 KB DTCP-IP Host interface/ PCI controller Encryption module MPEG-TS: 3 Interval timer 2 SCI: 2 EtherMAC: 1 ch 66

67 SH7652 Overview - Network processor with DTCP-IP function for DLNA (Digital Living Network Alliance) incorporated - Network-specialized cost performance - SH-2A core: 200 MHz DTCP-IP -support functions - An inter-device authentication function and content encryption/decryption function implemented by hardware and firmware provided with the SH7652, compliant with the DTCP-IP standard. - Network functions for IP broadcasting USB 2.0 High Speed and SD host interface Abundant bus interfaces - SDRAM I/F - Burst ROM I/F etc. 67

68 Functional Overview of SH7652 CPU core - SH2A-FPU (32-bit SuperH RISC, 32-bit multiplier) - PVcc = 3.0 to 3.6 V, Vcc = 1.1 to 1.3 V Operating frequency -CPU clock: 200 MHz - Bus clock: 66 MHz Internal memory - RAM: 32 KB - Cache memory: 16 KB DTCP-IP Host interface - 2 KB 2 banks - HIF boot function Ethernet controller - EtherMAC (10/100 Mbps): 1 - Transmit/receive FIFO: 512 Bytes each - TCP/IP checksum accelerator USB 2.0 High Speed - Host or Function: 1 Memory interface - SRAM, SDRAM interface - External bus can be extended up to 32 bits. Encryption module - AES encryption/decryption - FIFO (independent transmit/receive) - Dedicated DMAC (AES FIFO SDRAM) MPEG-TS interface -PS - 2 channels included Peripheral functions - Serial communication interface with FIFO: 2 -I 2 C: 1 ch - SD host interface - 16-bit interval timer: 2 - JTAG interface support, external interrupt pin, I/O port, etc. Package - BGA-240 SH2A-FPU: 200 MHz Encryption module RAM: 32 KB Cache: 16 KB DTCP-IP USB2.0 HS *The specification is subject to change. Host interface MPEG-TS: 2 16-bit Timer 2 SCIF: 3 EtherMAC: 1 ch SD I/F 68

69 Functional Overview of SH7670/SH7671/SH7672/SH7673 CPU core -SH2A-FPU (32-bit SuperH RISC, 32-bit multiplier) - PVcc = 3.0 to 3.6 V, Vcc = 1.1 to 1.3 V Operating frequency -CPU clock: 200 MHz - Bus clock: 66 MHz Internal memory - RAM: 32 KB - Cache memory: 16 KB Host interface - 2 KB 2 banks - HIF boot function Ethernet controller - EtherMAC (10/100 Mbps): 1 - Transmit/receive FIFO: 512 Bytes each - TCP/IP checksum accelerator USB 2.0 High Speed - Host or Function: 1 Memory interface - SRAM, SDRAM interface - External bus can be extended up to 32 bits. Encryption module (Only SH7672, 73) - AES encryption/decryption - FIFO (independent transmit/receive) - Dedicated DMAC (AES FIFO SDRAM) Peripheral functions - Serial communication interface with FIFO: 2 -I 2 C: 1 - SD host interface (Only SH7671, 73) - 16-bit interval timer: 2 - JTAG interface support, external interrupt pin, I/O port, etc. Package - BGA-256 SH2A-FPU: 200 MHz Encryption module RAM: 32 KB Cache: 16 KB USB2.0 HS *The specification is subject to change. Host interface 16-bit Timer 2 SCIF: 3 EtherMAC: 1 ch SD I/F 69

70 Host Interface (HIF) Features: 1. Connectable to the main CPU with parallel bus 2. HIF boot function eliminates the need for boot ROM Main CPU bus Main CPU SH-2 Cache SH local bus RAM SDRAM Boot ROM not required Flash memory 16 bits EDMAC Flash memory HIFRAM Ether-C PHY LAN Connectable with general bus SH7618/SH7619/ SH7650/SH7652 LAN port 70

71 SH7710/SH7712/SH7713 Overview SH7712 is IPsec-less version of SH7710 SH7713 is IPsec-less, Ethernet (1) version of SH7710 Features High performance RISC engine SH3-DSP core MIPS@200 MHz Ethernet Controller (MAC: IEEE802.3u compliant) - 10/100 Mbps, Full duplicate mode supported - Transfer/Receive FIFO: 2 KB each - Bridge: transfer FIFO: 3 KB each IPsec accelerator * - Authentication algorithm: SHA-1, MD5 - Cryptography algorithm: DES, 3DES - Dedicated DMAC 4 ch Unified Cache: 32 KB Internal RAM: 16-KB X/Y-RAM SDRAM interface Power Supply Voltage: Core 1.5 V, I/O 3.3 V Package: QFP-256, CSP-256 Main applications Home gateway, VoIP-TA, IP phone, IP camera, Security equipment, etc SH7710 Block Diagram SH3-DSP 200 MHz JTAG MMU INTC TMU RTC SCIF: 2 BSC SDRAM I/F ROM,SRAM I/F PCMCIA I/F Cache memory 32 KB EDMAC 4 ch DMAC 6 ch SIOF: 2 IPsec Accelerator * X/Y RAM 16 KB Ether MAC Bridge ** Ether ** MAC *: Only SH7710 **: Only SH7710 and SH

72 SH7763 Overview Features SH4-A core (266 MHz) Cache (instruction: 32 KB, data: 32 KB) On-chip MMU 2-way super scalar 7-stage pipeline Internal RAM (16 KB) SDRAM interface Double data rate: 32-bit data bus, 133 MHz (DDR266), Class 1 On-chip STIF (stream interface) Ethernet controller (IEEE802.3): 2-10/100/1000 Mbps full duplex transfer supported - Flow control (IEEE802.3x) supported - On-chip E-DMAC: 2 ch (Tx, Rx) - 2-KB send/8-kb receive FIFO IPsec accelerator - Authentification algorithm: SHA-1, MD5 - Encryption algorithm: DES, 3DES, AES - On-chip IPsec DMAC: 2 ch PCI controller: PCI ver2.2 LCD controller: VGA full color display is supported USB Host/Function: Ver. 2.0 Full Speed is supported Peripheral functions - SCIF (3), DMAC (6 ch), INTC, RTC, TMU, SIOF (3), SSI, I 2 C, HAC, various memory card I/Fs, I/O ports, A/D converter, D/A converter, etc. Vcc - Core = 1.25 V, I/O = 3.3 V, DDR I/O = 2.5 V Package - PBGA , ball pitch: 0.8 mm Block diagram of the SH7763 SH-4A: 266 MHz JTAG MMU Cache: 64 KB INTC TMU TPU RTC SSI I 2 C A/D converter: 4 ch D/A converter: 2 ch (Part No.: R5S77630Y-266BGV) STIF HAC SIOF: 3 SCIF: 3 U-RAM: 16 KB DMAC: 6 ch CPG Memory card I/F IPsec Acc. BSC1 ROM, SRAM I/F PCMCIA I/F BSC2 DDR-SDRAM-I/F PCIC USB2.0 (H/F) LCDC GbEther MAC1 Bridge GbEther MAC2 72

73 SH7764 Overview CPU core - SH-4A (SuperH RISC engine) FPU Operation frequency - CPU Clock: 324 MHz - Bus Clock: 108 MHz Operation Voltage (double voltage) - In 1.2 V/Ex 3.3 V Embedded memory - RAM: 16 Kbytes - Cache: I = 32 Kbytes D = 32 Kbytes Bus Interface - SRAM, Flash, SDRAM - External bus 8 bits, 16 bits, 32 bits (SDRAM: 32 bits/64 bits) - External bus space can be divided into 4 areas: Each 64 MB max. (Total 256 Mbytes) Peripheral - 32-bit Timer: 6 - Watch dog Timer: 1 - Ether MAC: 1 ch -I 2 C bus interface: 1 - DMA controller: 6 ch - SCIF (Asynchronous serial): 3 - SSI (Codec I/F): 6 - SCR (Sampling rate converter): 2 - NAND Flash Interface - IDE controller (UltraDMA/66 Support): 1 - SD I/O (option) - 2D Graphic - LCDC/Digital RGB (VDC2) -GPIO -INTC - H-UDI (User Debag Interface) Package - BGA404pin SH-4A 324 MHz MCU ROM, SRAM, SDRAM I 2 C: 1 GPIO MMU FPU TMU 32 bits: 6 I-cache 32 KB INTC WDT SCIF: 3 SSI: 6 IDE controller: 1 Ether MAC: 1 ch SD I/O (option) 2D Graphic Data cache 32 KB DRAM: 6 H-UDI RAM 16 KB SRC: 2 NAND Flash I/F USB2.0 host/function (HS): 1 VDC2 Digital RGB LCDC 73

74 List of Specifications for the SH-Ethernet Products (1) Item CPU Operating frequency Power supply voltage Cache memory Internal RAM General DMAC Ethernet controller Rx/Tx FIFO Ethernet-specific DMAC User break controller Timer unit Free-run timer Serial communication I/F with FIFO Serial I/O Package SH7615 DSP function enhanced version 512 B/512 B SH2-DSP core 62.5 MHz 3.3 V 4 KB 8 KB 2 ch 3 208LQFP (SH7615ARF) 240CSP (SH7615ARBP) 1 2 ch SH7616 FIFO expanded version 2 KB/2 KB 208LQFP SH7618/18A EtherMAC SH-2 core 100 MHz 1.5 V/3.3 V 4 KB/16 KB 4 KB 0 1 SH7618: 256 B/256 B SH7618A: 512 B/512 B 2 ch CSP SH7619 EtherMAC, PHY 125 MHz 1.8 V/3.3 V 16 KB 16 KB 4 ch 1, PHY 512 B/512 B 1 74

75 List of Specifications for the SH-Ethernet Products (2) SH7710 SH7712 SH7713 SH7763 SH7764 Item EtherMAC 2, Gb EtherMAC EtherMAC 2 EtherMAC 1 2, IPsec PCI EtherMAC 1 CPU SH3-DSP core SH-4A core SH-4A core Operating frequency 200 MHz 266 MHz 324 MHz Power supply voltage 1.5 V/3.3 V 1.25 V/3.3 V/2.5 V 1.25 V/3.3 V Cache memory 32 KB 64 KB 64 KB Internal RAM 16 KB 16 KB 16 KB General DMAC 6 ch 6 ch 6 ch Ethernet controller 2 2 (Gbit) 1 Rx/Tx FIFO 2 KB/2 KB 2 pairs 4 ch 2 KB/2 KB 1 pair 8 KB/2 KB 2 pairs 2 KB/2 KB 1 pair Ethernet-specific DMAC 2 ch 4 ch 2 ch User break controller Timer unit Free-run timer Serial communication I/F with FIFO Serial I/O 2 (incl.fifo) 3 + USB (1) 6 + USB (1) Package HQFP CSP PBGA PBGA

76 List of Specifications for the SH-Ethernet Products (3) Item SH7670 EtherMAC 1 SH7671 EtherMAC 1, SDIO SH7672 EtherMAC 1, Crypt SH7673 EtherMAC 1, SDIO, Crypt CPU SH-2A core Operating frequency 200 MHz Power supply voltage 1.2 V/3.3 V Cache memory 16 KB Internal RAM 32 KB General DMAC 8 ch Ethernet controller 1 Rx/Tx FIFO 512 B/512 B Ethernet-specific DMAC 2 ch User break controller 2 Timer unit 2 Free-run timer - Serial communication I/F with FIFO 3 Serial I/O -(USB2.0 1) Package 256CSP 76

77 Processor Type SH7700 Series SH7750 Series SH7780 Series 77

78 Lineup of SuperH (Processor-Type) Microcontroller Products SH7780 Series (SH-4A) SH7786 Dual Core : Mass Production : New Product : Under Development : In Planning SH MHz SH77xx SH7200 Series (SH-2A) SH7750 Series (SH-4) SH7750S 200 MHz SH MHz SH7750R 240 MHz SH MHz PCIC SH7751R PCIC LCDC SH MHz SH MHz G-Ether SH MHz Ether SH /333 MHz (SH4AL-DSP) SH /266 MHz SH MHz SH MHz SH7263 SH MHz SH7265 SH7205 Dual Core SH MHz Ether SH7729R SH7709S 167/200 MHz SH MHz SH7710/12/13 167/200 MHz Ether MAC SH /160 MHz LCDC, USB SH MHz SH7700 Series (SH-3, SH3-DSP) SH7720/ MHz LCDC, USB SH-2 SH MHz SH7261 SH MHz SH7619 SH7618 Ether 125 MHz 100 MHz SH7264 SH MHz 78

79 High-Performance 32-Bit RISC Processor Features Low power and high performance: 133 MHz (SH7705) MMU (Memory Management Unit), cache on chip Power management - Low-power mode - Frequency control - Module ON/OFF control Compatible with SH-1 and SH-2 instruction sets 79

80 SH7705 Overview - SH-3 Low Power Version - Features High-performance ultra-low power RISC CPU SH-3 - Low power-consumption: 1 ma/mhz V (Internal) - CPU clock: 133 MHz/bus clock: 66 MHz Cache: Large Capacity 32 KB On-chip USB Function Ver.2.0 (Full Speed) - On-chip USB transceiver - Control/bulk/interrupt transfer support BSC (bus state controller) - Page mode FLASH, ROM, SRAM, SDRAM Enriched on-chip peripheral functions - DMAC, WDT, A/D Converter, CMT, RTC, etc. On-chip high-speed serial interface - UART/clock synchronous switchover type (on-chip 64-byte FIFO): 2 (IrDA1.0: 1) Powerful power management function - Sleep, standby, module standby, hardware standby Package: LQFP-208 (28 mm square), CSP-208 (12 mm square) SH-3 CPU 32-bit multiplier 4-way cache 32 KB BSC ROM, SRAM I/F SDRAM I/F Burst ROM I/F SH7705 Block Diagram UBC: 2 TMU: 32-bit x 3 TPU: 16-bit 4 DMAC: 4 ch SCI: 2 IrDA1.0 Port RTC INTC CPG/PLL MMU USB function A/D 10-bit 4 ch Main applications DSC, DVC, Video printer, Faxes, Ink-jet printer, Barcode Reader, PDA, and POS terminal 80

81 SH7706 Overview - SH-3 Compact Version - Features CPU SH-3: 133 MHz Cache: 16 KB Peripheral functions -4-ch DMAC - 10-bit 4-ch A/D converter - 8-bit 2-ch D/A converter - SCI : 2 (with FIFO: 1) - 3-ch timer (32 bits) -RTC Power management function High-performance, low power consumption Package: 176-pin LQFP, 208-pin CSP Main applications MFP/Ink-jet printers, Faxes, scanners, DVD recorders, and DVC SH-3 CPU 32-bit multiplier 4-way cache 16 KB BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F PCMCIA I/F SH7706 Block Diagram UBC: 2 TMU 32-bit 3 DMAC 4 ch SCI: 2 PORT RTC INTC CPG/PLL MMU D/A 8-bit 2 ch A/D 10-bit 4 ch 81

82 SH7709S Overview - SH-3 High-speed Version - Features Improved CPU operation performance 200 MHz (260 MIPS) MAX. Line-up is 100/133/167/200 MHz Version Cache: 16 KB Peripheral functions -4-chDMAC - 10-bit 8-ch A/D converter - 8-bit 2-ch D/A converter - SCI: 3 (with FIFO: 2) (IrDA 1.0: 1) Power management function High-performance and low power consumption Package - LQFP-208, CSP-240 (100/133/167 MHz) - HQFP-208 (200 MHz) Main applications Portable information equipment, internet equipment, LBP, printer, scanner, and network equipment SH7709S Block Diagram SH-3 CPU 32-bit multiplier 4-way cache 16 KB BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F PCMCIA I/F UBC: 2 TMU 32-bit 3 DMAC 4 ch SCI: 3 PORT RTC INTC CPG/PLL MMU D/A 8-bit 2 ch A/D 10-bit 8 ch 82

83 SH7727 Overview Features Supports DSP instructions (16-bit fixed points) - to 100/160 MHz - to 200/320 MOPS MMU Cache: 16 KB X/Y memory (DSP core) RAM: 2 8 KB (total 16 KB) LCDC (color) USB function Ver.2.0 (Full Speed) USB host (Full/Low Speed), OHCI: Ver.1.0 AFE interface Other functions: A/D converter and PCMCIA I/F etc On-chip debugger - JTAG interface H-UDI (subset) - User break controller (UBC) Package - HQFP CSP-240 SH7727 Block Diagram SH3-DSP core TMU 32-bit 3 BSC ROM, SRAM I/F SDRAM I/F Burst ROM I/F A/D 10-bit 6 ch Cache 16 KB DMAC 4 ch SCI: 3 UBC: 2 USB host USB function LCDC RAM X/Y memory 2 8 KB INTC CPG/PLL H-UDI AFE I/F CMT 16-bit 1 Main applications Faxes, printer, AV equipment terminal, webphone, POS terminal, internet terminal, and DSC printer. 83

84 SH7720/SH7721 Overview SH7721 is SSL-less version of SH7720 Features Supports DSP instructions (16-bit fixed points) - to 133 MHz - to 266 MOPS MMU Cache 32 KB SSL accelerator X/Y memory (DSP core) RAM: 2 8 KB (total 16 KB) LCDC (color) USB function (Ver. 2.0 Full Speed) USB Host (Full/Low Speed) OHCI: Ver.1.0 I 2 C bus interface: DMAC 6 channels TMU: 32-bit timer 3 TPU: 16-bit timer 4 SCIF: Serial interface with FIFO 2 IrDA interface (Ver. 1.0) SIOF: Audio serial interface with FIFO 2 Smart Card Interface AFE I/F A/D converter 10-bit 4 ch, D/A converter 8-bit 2 ch PCMCIA I/F, MMC I/F Package: FBGA-256 (17 mm 17 mm, ball pitch: 0.8 mm) (11 mm 11 mm, ball pitch: 0.5 mm) SH3-DSP Core 32-bit Multiplier BSC MMU LCDC USB Host SH7720 Block Diagram 4-way Cache 32 KB X/Y Memory 16 KB RTC SSL* Accelerator USB Function Interrupt Control UBC: 2 TMU TPU I 2 C DMAC 6 ch D/A 8-bit A/D 10-bit CMT: 32-bit 5 CPG/PLL PCMCIA controller 1 slot MMC, CF AFE I/F SIM: 1 SCIF: 2 SIOF: 2: Audio CODEC I/F *: only SH7720 Main applications IP Phone, Faxes, Printer, AV equipment terminal, Webphone POS terminal, Internet terminal, and DSC printer 84

85 SH7729R Overview Features DSP instruction (SH3-DSP) MHz/133 MHz/167 MHz/200 MHz MOPS/266 MOPS/334 MOPS/400 MOPS MMU - MMU fully compatible with the SH-3 (TLB) Cache - Cache fully compatible with the SH-3 (16 KB) Built-in memory for DSP processing (X/Y memory) -RAM: 2 8 KB (total 16 KB) Built-in debugging function - Emulation interface that conforms to JTAG (H-UDI) - User break controller (UBC) Package - LQFP-208, CSP-240 (100/133/167 MHz) - HQFP-208 (200 MHz) SH7729R Block Diagram SH3-DSP core TMU 32-bit 3 BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F A/D 10-bit 8 ch Cache 16 KB DMAC 4 ch SCI: 3 UBC: 2 D/A 8-bit 2 ch RTC RAM X/Y memory 2 8 KB INTC CPG/PLL H-UDI MMU Main applications Network application (VoIP), internet FAX, webphone, DSC, and TV conference system 85

86 Multimedia SH-4/SH4-A RISC Processor Features High performance CPU that enables parallel execution of two instructions Ultra-high-speed 3D vector multiplier Upwardly compatible with SH-1/SH-2/SH-3 instruction sets - 16-bit fixed-length instructions - IEEE754 floating-point instructions are supported (high-speed single precision and double precision) 86

87 Ultra-High-Speed Floating-Point Operation FTRV instruction XMTRX, FVn a11 a12 a13 a14 a21 a22 a23 a24 a31 a32 a33 a34 a41 a42 a43 a44 x y z i = x' y' z' i' FADD FMUL FMUL FMUL FMUL 16 multiplications and 12 additions are executed in four clock cycles 128 bits FPU Register File1 ( 16) Loading/storing to other registers during an operation is possible FPU Register File2 ( 16) 87

88 Features of SH-4 - Superscalar - Clock SH-3 Instruction A Instruction B Instruction C Instruction D SH-4 SH-4A (Superscalar) Instruction A Instruction B Instruction C Instruction D Parallel processing Execution time 1/2 Execution time 88

89 2-Way Superscalar Method 2-instruction parallel execution Improved execution efficiency with simple hardware Instruction queue Decoder 1 Decoder 2 Branch unit Integer unit Load/store and simple op. unit Floating-point unit 89

90 SH7750R Overview - 2-way superscalar architecture - Features High-performance 2-way superscalar Operating frequency: 200/240 MHz - Internal power supply voltage: 1.5 V (typ.) Built-in MMU Cache: (Harvard architecture) - large-capacity cache: 16-KB instruction + 32-KB data (2-way set associative) DMAC: 8 channels When bus width is 64 bits, 256-Mbit SDRAM ( 16) is supported Package: BGA-256, QFP-208 BGA-292 (17 mm 17 mm, 0.8-mm pitch) Main applications Car navigation, image processing, STB, digital TV, and printer SH-4 CPU 2-way superscalar 32-bit multiplier FPU 3DG 32-bit TMU I-Cache 16 KB D-Cache 32 KB BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F PCMCIA I/F MPX I/F RTC INTC UBC MMU DMAC SCI CPG/PLL 90

91 SH7751R Overview - SH-4 on-chip PCI version - Features High-performance 2-way superscalar Operating frequency: 200/240 MHz - Internal power supply voltage: 1.5 V (typ.) Built-in MMU Cache: (Harvard architecture) - large-capacity Cache: 16-KB instruction + 32-KB data (2-way set associative) DMAC: 8 channels Package: BGA-256, QFP-256 BGA-292 (17 mm 17 mm, 0.8-mm pitch) Main applications Communications - Routers, PBX, LAN/WAN, and NAS OA/PC peripherals - Printer, scanner, and PPC SH-4 CPU 2-way superscalar 32-bit multiplier FPU 3DG 32-bit TMU I-Cache 16 KB D-Cache 32 KB BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F PCMCIA I/F MPX I/F RTC INTC UBC MMU DMAC SCI CPG/PLL H-UDI/AUD PCIC 91

92 SH7760 Overview - High-performance processor with on-chip LCD controller and USB host - Features High-performance 2-way superscalar Operating frequency: 200 MHz (Internal)/66 MHz (Bus) - Internal power supply voltage: 1.5 V (typ.) Large-capacity Cache: 16-KB instruction + 32-KB data (2-way set associative) Peripheral modules - LCDC: LCD controller ( : 256 colors, etc.) - USB: USB host (Full/Low Speed) - OHCI: Ver SCIF, HAC, SSI, I 2 C, HSPI, SIM, MMCIF, CMT, A/D Converter, MFI, and GPIO Package: BGA-256 (17 mm 17 mm, 0.8-mm pitch) Main applications Car navigation, Telematics SH-4 CPU 2-way superscalar 32-bit multiplier FPU 3DG 32-bit TMU LCDC I-Cache 16 KB D-Cache 32 KB BSC ROM,SRAM I/F SDRAM I/F Burst ROM I/F PCMCIA I/F MPX I/F ADC GPIO MFI INTC UBC MMU DMAC CPG/PLL H-UDI/AUD HCAN2 I 2 C USB(H) RAM HAC/SSI HSPI/SIM /MMCIF 92

93 SH7780 Overview Features CPU core - CPU core: SH-4A - Operating frequency: 400 MHz@1.25 V External bus interface (3-bus configuration) Voltage Bus width Clock frequency - DDR I/F 2.5 V 32 bits 160 MHz - Local bus 3.3 V 32 bits 100 MHz - PCI 3.3 V 32 bits 33/66 MHz Cache memory/internal memory - Instruction cache: 32 KB (4-way set associative) - Data cache: 32 KB (4-way set associative) - LRAM(high-speed): 16 KB - Medium-speed RAM: 32 KB Peripheral modules -DMAC: 12 ch -SCIF: 2 - SIOF/SSI/HAC - NAND flash controller - MMCIF Package: BGA-449 (21 mm 21 mm, 0.8-mm pitch) Main applications Car navigation, amusement equipment, network terminals, laser-beam printers SH-4A 400 MHz Superscalar CPU FPU MMU 32-KB I-Cache 32-KB D-Cache 16-KB LRAM Bus interface DDR-SDRAM controller DMAC WDT/RTC INTC CPG Medium- Speed 32-KB RAM Local bus, SRAM, MPX PCMCIA, etc. SCIF/HSPI SCIF/MMCIF SIOF/SSI/HAC TMU/CMT NAND Flash PCI bus 93

94 SH7785 Overview Features CPU core - CPU core: SH-4A - Operating frequency: 600 MHz@1.1 V External bus Interface (3-bus configuration) Voltage Bus width Clock frequency - DDR I/F 1.8 V 32 bits 300 MHz - Local bus 3.3 V 32/64 bits 100 MHz (64-bit width when PCI bus/display unit are not in use) - PCI 3.3 V 32 bits 33/66 MHz Cache memory/internal memory - Instruction cache: 32 KB (4-way set associative) - Data cache: 32 KB (4-way set associative) - LRAM (high speed): 8 KB + 16 KB - URAM (middle speed): 128 KB Peripheral modules - Display unit (DU) - Data translation accelerator (GDTA) - DMAC: 12 channels - SCIF, HSPI, and NAND Flash memory controller - SIOF, SSI, and HAC - MMCIF - H-UDI, high-speed AUD Package: BGA-436 (19 mm 19 mm, 0.8-mm pitch) Main applications SH-4A 600 MHz Superscalar CPU FPU MMU 32-KB I-Cache 32-KB D-Cache 8-KB ILRAM 16-KB OLRAM 128-KB URAM Bus interface DDR2-SDRAM Controller Car navigation systems, amusement devices, network terminals, LBPs (laser beam printers), etc. DMAC WDT INTC CPG TMU GDTA Local bus SRAM, MPX, PCMCIA, etc. SCIF/HSPI/ FLCTL H-UDI/ High-speed AUD SCIF/MMCIF SIOF/SSI/ HAC PCI Bus/ Display Unit 94

95 Overview of the SH7730 Features High-performance CPU: SH-4A - 266/200 MHz (480/360 MIPS) - On-chip FPU, Support for MMU On-chip cache memory - Instruction cache: 32 KB - Operand cache: 32 KB Internal memory: 16 KB (ILRAM) External bus: 32 bits, 66 MHz -ROM/SRAM - SDRAM Peripheral modules -DMAC: 6 ch - Various timers (TMU, TPU, and CMT) - SCIF: 6 (IrDA: 2, SIOF: 1) -I 2 C: 2 - A/D converter: 10 bits, 4 ch - D/A converter: 10 bits, 2 ch Power management function - Sleep module standby - software standby On-chip debugging Package: 208-pin QFP (28 mm 28 mm) 95 SH-4A UBC H-UDI BSC ROM, SRAM Burst ROM SDRAM PCMCIA SIM A/D converter (10 bits 4 ch) D/A converter (10 bits 2 ch) FPU MMU Instruction Cache (4 ways, 32 KB) Operand Cache (4 ways, 32 KB) High-speed RAM (16-KB ILRAM) INTC DMAC (6 ch) RTC RWDT CPG I/O Ports SCIF (6) SIOF IrDA (2) I 2 C bus I/F (2) TMU (32 bits 3) TPU (16 bits 6) CMT (32 bits 5)

96 SH7786 Overview Features CPU Core - CPU Core: SH-4A 2 - Frequency: 533 MHz@1.25 V External bus Interface - DDR3 I/F: 32 bits width (max.) : 533 MHz (max.) - Local Bus: 8/16/32 bits width : 88.9 MHz (max.) - PCI-Express: (4 lane + 1 lane) or (2 lane + 1 lane + 1 lane) Cache memory/internal RAM - I-Cache: 32 KB 2 - O-Cache: 32 KB 2 : Cache snoop function - LRAM (High speed): (8 KB + 16 KB) 2 - L2Cache: 256 KB Peripheral module - Display Unit (DU): 1 ch (max.) - USB2.0 High speed: 2 ch (max.) (Host/Function) - Ethernet Controller: 1 ch (max.) (MII Interface) - DMAC: 24 ch (max.) - SDIF: 2 ch (max.) - SCIF: 6 ch (max.) -I 2 C: 2 ch (max.) - HSPI, SSI, HAC, NAND controller, H-UDI, AUD Package: BGA-593 (25 mm 25 mm: 0.8 mm pitch) Main Application Car navigation, amusement device, Network terminals SH-4A 533 MHz Superscalar CPU FPU MMU 32 KB I-Cache 32 KB O-Cache 8 KB ILRAM 16 KB OLRAM L2Cache Bus Interface DDR3-SDRAM controller INTC CPG TMU SH-4A 533 MHz Superscalar CPU FPU MMU 32 KB I-Cache 32 KB O-Cache 8 KB ILRAM 16 KB OLRAM DMAC WDT GPIO Local Bus SRAM, MPX, PCMCIA etc. SCIF SCIF/I 2 C SCIF H-UDI/ AUD DU/ EtherC/ HSPI PCI-Express Under Development SCIF/SD SCIF/SSI SCIF SD/HAC/ SSI USB2.0 High speed Host Function 96

97 SuperH for Car Infotainment System 97

98 Roadmap of SH-4/SH-4A Product for CIS 200 MHz 400 MHz 600 MHz Multi CPU High grade Integrated Solution Aunar 200 MHz, 2DG 480 pins SH MHz, LCDC 256 pins SH7770 (SH-Navi1) 400 MHz, 2D/3D, GPS 520 pins Compact Solution SH7760(BL) 200 MHz, LCDC 256 pins SH7775 (SH-Navi2G) 600 MHz, 2/3D Processor/3D GPS, 560 pins SH7774(SH-Navi2V) 600 MHz, Image recognition, 2D, AAC encoder 554 pins SH MHz, Ether, 2D, SDRAM I/F 404 pins SH7776 (SH-Navi3) * 533 MHz 2, 2/3D Processor/3D Image recognition, PCI-e, 653 pins SH77721 (SH-NaviJ1) * 333 MHz, Map and GUI Drawing 440 pins SH-NaviX *** SH-4A Dual Scalable Solution SH7750R/51R 240 MHz, PCI 256 pins SH MHz, PCI 449 pins SH MHz, PCI 436 pins SH7786 * 533 MHz 2, PCI-e, 593 pins SH-4A Dual SH77xx *** Under development Under planning Under consideration 430 MIPS 720 MIPS >1000 MIPS * ** *** 98

99 SH7770 for Full Graphics Display Type In-Vehicle Terminal All-in-one chip with graphics accelerator Introduction of 400-MHz SH-4A core realizes the high performance of processing Effective use of software assets Consistent evolution of SuperH core System solution including graphics and IP Abundant IP lineup Bus architecture that demonstrates system performances Use of Collected know-hows 99

100 Display Example of SH7770 2D/3D Graphics SH7770 have an exclusive accelerator of 2D/3D individually. 2D Graphic 3D Graphic Translucency and reflections Menu Menu Bumpmap Menu True-color blending e.g.) Map-Drawing * 3D graphics IP from Imagination Technologies, Ltd. of the United Kingdom is used as the on-chip 3D graphics engine 100

101 SH7770 Overview Features Max. internal operating frequency of SH-4A core: 400 MHz Power supply voltage: 3.3 V (I/O), 2.5 V (DDR), 1.25 V (core) Performance: 720 MIPS MHz 2-way superscalar, 7-stage pipeline Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR SDRAM I/F 2D Graphics Engine 3D Graphics Engine Display: WVGA 854 dots 480 dots (16-bit pixel) Peripheral functions: Please refer to the diagram at right. Package: BGA-520 pins (33 mm 33 mm, 1.0-mm pitch) SH-4A 400 MHz UBC FPU MMU 32-KB I-cache 32-KB O-cache INTC WDT EX-Bus controller DDR-SDRAM controller DMAC CPG 3D Graphics 2D Graphics Display Out YUV Video In ATAPI USB (H/F) GPS A/D converter SH7770 HCAN2 HSPI HAC SPDIF SRC SSI I 2 C TMU SCIF RTC PWM Remote control 101

102 SoC SH-Navi2G SH7775 for Car Navigation System High performance SoC equipped with Map and GUI Graphics Processor, 3D Graphics Engine, and various function for car navigation system. Product concept SH-Navi2G (SH7775) External memory High- Performance SH-4A core SH-4A 600 MHz Memory Controller Map and GUI Drawing Processor and 3D Graphics Comprehensive Peripheral Modules Map and GUI Drawing Graphics Processor 3D Graphics Engine GPS B/B ATAPI USB 2.0 RCAN TS-IF 1. SH-4A CPU core operating at 600 MHz with 50% increase of current Renesas SoC products 2. Newly developed on-chip Graphics Processor optimized for Map and GUI Drawing and 3-D Graphics Engine. 3. Comprehensive range of peripheral functions for car information systems 102

103 SH7775 Overview Features SH7775 Max. internal operating frequency of SH-4A core: 600 MHz Power supply voltage: 3.3 V (I/O), 1.8 V (DDR), 1.1 V (Core) Performance: 1080 MIPS@600 MHz Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR2 SDRAM I/F Renesas Graphics Processor (2D, 3D) 3D Graphics Engine Display: WVGA 832 dots 496 dots (16-bit pixel) Peripheral functions: Please refer to the diagram at right. Package: BGA-560 pins (25 mm 25 mm) SH-4A 600 MHz FPU UBC MMU 32 KB I-cashe 32 KB O-cashe DMAC DDR2- SDRAM Controller 3D Graphics Graphics Processor (2D/3D) TS-IF Display Out Video In ATAPI INTC CPG RCAN GPS USB2.0 (H/F) SSI HSPI SCIF TMU Debug GPIO 103

104 SoC for Car Navigation System SH-Navi2V SH7774 High performance SoC equipped with the image recognition processing function and various function for car navigation system. Product concept SH-Navi2V (SH7774) External Memory High- Performance SH-4A core SH-4A 600 MHz Image Recognition Memory Controller Image Recognition 2D Graphics and Comprehensive Peripheral Modules Audio Encoder 2D Graphics Engine DISPLAY VIDEO IN 1. World s first on-chip image recognition processing IP in a car navigation SoC MHz SH-4A CPU core enabling implementation of high-performance systems for the next generation. 3. Comprehensive range of peripheral functions for next -generation in-vehicle information terminals. 104

105 SH7774 Overview SH7774 Features Max. internal operating frequency of SH-4A core: 600 MHz Power supply voltage: 3.3 V (I/O), 1.8 V (DDR), 1.1 V (Core) Performance: 1080 MIPS@600 MHz Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR2 SDRAM I/F 2D Graphics Engine Display: WVGA 832 dots 496 dots (16-bit pixel) Peripheral functions: Please refer to the diagram at right. Package: BGA-554 pins (29 mm 29 mm) SH-4A 600 MHz UBC FPU MMU 32 KB I-cache 32 KB O-cache DMAC DDR2- SDRAM Controller Image Recognition 2D Graphics AAC Encoder Video In (2 ch) ATAPI INTC CPG RCAN Ethernet Display Out SSI H/SPDIF SCIF TMU Debug GPIO 105

106 SH-Navi2V SH7774 Image Recognition Engine The seamless process is available between CPU and Image Engine Navigation Software SH-4A 600 MHz Image Application Software Image Recognition Engine Processing result of Lane Recognition by SH7774 SHwy MCU DDR600 Video In Bridge 2D Camera 106

107 SoC for Car Navigation System SH-Navi3 SH7776 High performance SoC equipped with SH-4A dual core for High-end car navigation system. Product concept SH-Navi3 (SH7776) External Memory SH-4A Dual Core Map and GUI Drawing Processor and 3D Graphics SH-4A 533 MHz SH-4A 533 MHz DDR3 Memory Controller Image Recognition Ultrahigh-speed Data Transfer by DDR3 and SATA Map and GUI Drawing Graphics Processor 3D Graphics Engine Image Recognition and Warping Correction Serial ATA PCI Express GPS B/B USB2.0 SD Card Host 1. Dual high-performance SH-4A CPU cores for superior processing power of 1920 MIPS 2. On-chip Graphics Processor optimized for Map and GUI Drawing and 3-D Graphics Engine achieving high-speed and wide variety of drawing function. 3. Comprehensive range of peripheral functions for car information systems such as Image Recognition processing IP and Wrapping Correction module. 4. On-chip DDR3-SDRAM memory interface, Serial ATA interface, and PCI Express interface for ultrahigh-speed data transfers 107

108 SH7776 Overview SH7776 Features Max. internal operating frequency of SH-4A core: 533 MHz 2 Power supply voltage: 3.3 V (I/O), 1.5 V (DDR), 1.25 V (Core) Performance: 1920 MIPS (Dhrystone)@533 MHz 2-way superscalar, 7-stage pipeline Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR3 SDRAM I/F Renesas Graphics Processor (2D, 3D) 3D Graphics Engine Display: WXGA 1280 dots 768 dots (16-bit pixel) Peripheral functions: Please refer to the diagram at right. Package: BGA-653 pins (25 mm 25 mm, 0.8-mm pitch) SH-4A 533 MHz SH-4A 533 MHz CPG DMAC INTC WDT EX-Bus Controller DDR3- SDRAM Controller PCI express 3D Graphics Graphics Processor (2D/3D) Image Recognition Warping Correction Video In (3 ch) Display Out (2 ch) USB2.0 (H/F) SD Card Host (2 ch) SATA A/D converter IF GPS RCAN HSPI SPDIF SRC SSI I 2 C TMU SCIF DARC PWM Remote Control TS-IF 108

109 SH-Navi Series Roadmap (Entry-High-End) High Mid SH-Navi2V 600 MHz, 2D/Image recognition SH-Navi1 400 MHz, 2D/3D SH-Navi3 * 533 MHz 2, 2D/3D, Image recognition, PCI-e SH-Navi3 * SH-Navi2G 600 MHz, 2D/3D SH-Navi series Bus architecture SH-Navi2V 600 MHz, 2D/Image recognition 533 MHz 2, 2D/3D, Image recognition, PCI-e SH-Navi1 400 MHz, 2D/3D SH-NaviJ* Series SH MHz, 2D/3D SH-Navi2G 600 MHz, 2D/3D Software scalability Entry * : Under Development

110 New SoC SH-NaviJ1 SH77721 for Low-End to Middle-Range Car Navigation Systems 1. The optimized specification for an entry CIS model Enhanced Renesas Graphics Processor USB 2.0 High speed Add SD Card host Interface CPU 333 MHz, low power consumption Smaller package 2. Save the software development cost Software scalability can use software property of SH-Navi series, (e.g. common 2D Graphics and peripheral modules) 3. Save the external SDRAM cost. SDRAM I/F of SH-Navi1 SDRAM I/F of SH-NaviJ1 DDR1 ( 16) 4 pcs (64 bit bus) 1600 MB/s DDR2 ( 16) 1 pcs (16 bit bus) 666 MB/s 110

111 SH77721 Overview SH77721 Features Max. internal operating frequency of SH-4A core: 333 MHz Power supply voltage: 3.3 V (I/O), 1.8 V (DDR), 1.25 V (Core) Performance: 599 MHz Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR2 SDRAM I/F Renesas Graphics Processor (2D/3D) Display: WVGA 832 dots 496 dots (16-bit pixel) Peripheral functions: Please refer to the diagram at right. Package: BGA-440 pins (23 mm 23 mm) SH-4A 333 MHz UBC FPU MMU 32 KB I-cache 32 KB O-cache DMAC DDR2- SDRAM Controller Graphics Processor (2D/3D) SD card Host (2 ch) SSI Display Out Video In A/D converter INTC DARC RCAN GPS USB2.0 (H/F) I 2 C HSPI SCIF TMU Debug GPIO 111

112 SH77650 Specialized SoC for Automotive Image Recognition Processing 1 chip solution for image recognition system SH77650 External Memory Product concept High- Performance SH-4A core Image Recognition SH-4A 300 MHz Image Recognition Memory Controller DISPLAY VIDEO IN 1. High-performance image recognition processing IP 2. SH-4A CPU core operating at 300 MHz to enable actualization of high-performance systems 3. A variety of peripheral functions for automotive image recognition applications 112

113 SH77650 Overview SH77650 Features Max. internal operating frequency of SH-4A core: 300 MHz Power supply voltage: 3.3 V (I/O), 2.5 V (DDR), 1.2 V (Core) Performance: 540 MIPS@300 MHz Image recognition engine Cache: 32-KB 4-way set associative (I-, O-cache) Memory: DDR1 SDRAM I/F Internal RAM 256 KB Peripheral functions: Please refer to the diagram at right. Package: BGA-376 pins (19 mm 19 mm) SH-4A 300 MHz UBC FPU 32 KB I-cache 32 KB O-cache DMAC Boot MMU Image Recognition RCAN I 2 C A/D converter SCIF CPG SSI INTC TMU H-UDI/AUD WDT Display Out Video In DDR1- SDRAM Controller 113

114 SuperH RISC engine System Application 114

115 Configuration Example of the Cable Modem LED SCI Receive unit SuperH SH7615 * SH7729R 10/100 M Ethernet PHY MAC Cable Cable Tuner Filter Transmit unit QAM Demod QPSK Mod FEC R-S Encode M A C SDRAM FLASH *: SH7615 incorporates Ether MAC. 115

116 Configuration Example of the AC Servo Control System IGBT module AC motor 3-phase AC supply Pulse train input Base driver 6-phase PWM output M Encoder S Communication with high-end CPU MTU2 (16-bit timer) 12-bit A/D converter SCIF 4 ROM 512 KB SH7211 RAM 32 KB Motor Current detection 2-phase encoder input 116

117 General-Purpose Inverter: Example of System Configuration High-precision and high functionality inverter system can be realized by enhancedperformance SH-2A CPU core, large-capacity flash memory with up to 1 MB, and timers (MTU2 and MTU2S) for motor control. USB controller is also included, which enables interface to a host PC. High-versatility motor control Dual motor control by timers MTU2 and MTU2S Motor 3-phase PWM output 3-phase PWM output General-purpose inverter MTU2 MTU2S SH-2A CPU (100 MHz) peripheral I/F I 2 C SCI Abundant communications functions SCI 4, SCIF, IIC, SSU EEPROM Sub MCU Host PC A/D input 12-bit Input of A/D various sensors converter Flash: 1 MB SH7280 RAM: 32 K USB function Inclusion of high-precision 12-bit A/D converter Greater precision of sensor measurement On-chip USB controller Interface to a host PC 117

118 Application Example Using the SH Controlling the external unit of air conditioner with a single chip - SH-2 80 MHz 10-bit A/D converter Sensor information Outside temperature Humidity 10-bit A/D converter Electric current detection 10-bit A/D converter 6-phase PWM output MTU2 (Inverter control) Base driver M Communication to the internal unit POE SCI Error detection signal Shunt resister 3-phase inverter 6-phase PWM output Compressor MTU2S (Inverter control) POE SH7149 Base driver Error detection signal Shunt resister 3-phase inverter M Fan motor 118

119 Configuration Example of the Page Printer System Mask ROM/flash memory SH7709S, SH7750R, SH7780 PC/ workstation CPU Multiplier Program ROM DRAM Font ROM Cache Peripheral function Receiving buffer ASIC Communication controller Parallel interface Ethernet Local talk etc 16 M SDRAM Page memory ( ) ASIC Synchronous DRAM Raster processor Raster operation Parallel to serial conversion Video signal LBP engine 8-bit microcomputer Motor controller Laser controller 119

120 Configuration Example of the Compact Printer System Stores the user program, high-speed JPEG middleware, and JPEG image data SH7705 TMU Flash ROM SDRAM ASIC Printer engine CCN CACHE 32 KB MMU TLB INTC CPG Internal bus External bus Interface CPU bus SH-3 CPU UBC AUD BSC DMAC Peripheral bus TPU RTC CMT SCIF/ IrDA SCIF USB H-UDI I/O port ADC IrDA Communication USB Communication Key input Battery monitor PWM OUT Mobile phone PC Key board Battery 120

121 Configuration Example of the Portable Information Terminal System ROM SDRAM SH7720 STN/DSTN/ TFT LCD Color LCDC USB host USB func PCMCIA controller CODEC interface CF card CODEC Music Voice Printer PC Touch panel Battery 121

122 Gateway Configuration Example Using the SH-4 FTTH/ADSL PC Low-cost PCI connection chip can be used 10/100 baset 10/100 baset SH7751R 240 MHz SH-4 core: 430 MIPS Cache: 16 KB + 32 KB On-chip high-performance FPU Linux OS PCIC PCMCIA BSC - FTP 80-Mbps transfer - Software IP sec enabled - VolP achieved by using the FPU 16-bit product 2 SDRAM PDA HUB IEEE a, etc. PCI IEEE b Companion chip MD3306, etc. FLASH Storage function enhanced example 122

123 Example of SH7785 Application (Home Server) InterNet Encryption DSC Encryption PC a/b/g LANC USB Card Bus LANC SIOF MHz SCIF PCIC DDR PCI Bus S-ATA CODEC Zigbee or PLC Mobile IP-Phone Home Electronics Printer HomeNetwork (EtherNet) ivdr HDD(iVDR)/ DVD PC TV DVD Rec Web CAM Car Audio Car Navigation 123