Processors, FPGAs, and ASICs

Transcription

1 Processors, FPGAs, and ASICs p. 1/? Processors, FPGAs, and ASICs CSEE W4840 Prof. Stephen A. Edwards Columbia University

2 Processors, FPGAs, and ASICs p. 2/? Spectrum of IC choices Full Custom You choose polygons (Intel) Flexibility ASIC Gate Array circuit (Sony) wires FPGA PLD GP Processor SP Processor Multifunction Fixed-function logic network logic function program (e.g., Pentium) program (e.g., DSP) settings (e.g., Ethernet) part number (e.g., 74LS00)

3 Processors, FPGAs, and ASICs p. 3/? NMOS Transistor Cross Section Al n+ poly Al ox n+ p

4 Processors, FPGAs, and ASICs p. 4/? Inverter Transistors and Layout V dd V dd x x x V ss V ss x

5 Processors, FPGAs, and ASICs p. 5/? NAND Gate Transistors and Layout V dd V dd y x y x y x V ss V ss x y

6 Full-custom ICs Processors, FPGAs, and ASICs p. 6/?

7 Standard Cell ASICs Processors, FPGAs, and ASICs p. 7/?

8 Standard Cell ASICs Processors, FPGAs, and ASICs p. 8/?

9 Channeled Gate Arrays Processors, FPGAs, and ASICs p. 9/?

10 Channeled Gate Arrays Processors, FPGAs, and ASICs p. 10/?

11 Sea-of-Gates Gate Arrays Processors, FPGAs, and ASICs p. 11/?

12 Processors, FPGAs, and ASICs p. 12/? FPGAs: Floorplan DLL DLL BLOCK RAM BLOCK RAM CLBs CLBs CLBs CLBs BLOCK RAM BLOCK RAM DLL DLL I/O LOGIC

13 FPGAs: Routing Processors, FPGAs, and ASICs p. 13/?

14 G4 G3 G2 G1 F5IN BY SR F4 F3 F2 F1 BX CIN CLK CE I4 I3 I2 I1 I4 I3 I2 I1 Look-Up Table Look-Up Table O O Carry and Control Logic Carry and Control Logic D CK EC D CK EC S R S R Q Q COUT YB Y YQ XB X XQ FPGAs: CLB Processors, FPGAs, and ASICs p. 14/?

15 PLAs/CPLDs: The 22v10 CLK/I 1 Increments First Fuse Numbers Macrocell 23 Async (to all I/O/Q 396 P = 5808 R = Macrocell 22 I/O/Q I P = 5810 R = Macrocell 21 I/O/Q I P = 5812 R = Macrocell 20 I/O/Q 2112 Processors, FPGAs, and ASICs p. 15/?

16 Processors, FPGAs, and ASICs p. 16/? Example: Euclid s Algorithm int gcd(int m, int n) { int r; while ((r = m % n)!= 0) { m = n; n = r; } return n; }

17 Processors, FPGAs, and ASICs p. 17/? i386 Programmer s Model eax Mostly cs Code segment ebx General- ds Data segment ecx Purpose- ss Stack segment edx Registers es Extra segment esi edi Source index Destination index fs gs Data segment Data segment ebp Base pointer esp Stack pointer eflags Status word eip Instruction Pointer

18 Processors, FPGAs, and ASICs p. 18/? Euclid on the i386 gcd: pushl %ebp movl %esp,%ebp pushl %ebx movl 8(%ebp),%eax movl 12(%ebp),%ecx jmp.l6.l4: movl %ecx,%eax movl %ebx,%ecx.l6: cltd idivl %ecx movl %edx,%ebx testl %edx,%edx jne.l4 movl %ecx,%eax movl -4(%ebp),%ebx leave ret

19 Processors, FPGAs, and ASICs p. 19/? SPARC Programmer s Model 31 0 r0 Always 0 r1 Global Registers. r7 r8/o0 Output Registers. r14/o6 Stack Pointer r15/o7 r16/l0 Local Registers. r23/l r24/i0. r30/i6 r31/i7 PSW PC npc Input Registers Frame Pointer Return Address Status Word Program Counter Next PC

20 Processors, FPGAs, and ASICs p. 20/? SPARC Register Windows The output registers of the calling procedure become the inputs to the called procedure The global registers remain unchanged The local registers are not visible across procedures r8/o0. r15/o7 r16/l0. r23/l7 r8/o0 r24/i0.. r15/o7 r31/i7 r16/l0. r23/l7 r8/o0 r24/i0.. r15/o7 r31/i7 r16/l0. r23/l7 r24/i0. r31/i7

21 Euclid on the SPARC gcd: save %sp, -112, %sp mov %i0, %o1 b.ll3 mov %i1, %i0 mov %i0, %o1 b.ll3 mov %i1, %i0.ll5: mov %o0, %i0.ll3: mov %o1, %o0 call.rem, 0 mov %i0, %o1 cmp %o0, 0 bne.ll5 mov %i0, %o1 ret Processors, FPGAs, and ASICs p. 21/?

22 Processors, FPGAs, and ASICs p. 22/? Motorola DSP Memory Expansion Area Triple Timer Host Interface (HI32) ESSI SCI Program RAM (Default) X Data RAM (Default) Y Data RAM (Default) Address Generation Unit Six Channel DMA Unit Bootstrap ROM Internal Data Bus Switch PIO_EB Peripheral Expansion Area PM_EB DDB YDB XDB PDB GDB YAB XAB PAB DAB 24-Bit DSP56300 Core XM_EB YM_EB External Address Bus Switch External Bus Interface and I - Cache Control External Data Bus Switch 24 ADDRESS 14 CONTROL 24 DATA EXTAL XTAL Clock Generator PLL Program Interrupt Controller Program Decode Controller Program Address Generator Power Management Data ALU bit JTAG MAC OnCE Two 56-bit Accumulators DE 56-bit Barrel Shifter RESET PINIT/NMI 2 MODD/IRQA MODC/IRQB MODB/IRQC MODA/IRQD

23 Processors, FPGAs, and ASICs p. 23/? DSP Programmer s Model x1 x0 Source y1 y0 Registers a2 a1 a0 Accumulator b2 b1 b0 Accumulator 15 0 r7. r4 r3. r n7. n4 n3. n m7. m4 m3. m0 Address Registers 15 0 Program Counter Status Register Loop Address Loop Count 15 PC Stack SR Stack. 0 Stack pointer

24 Processors, FPGAs, and ASICs p. 24/? Motorola DSP56301 ALU X Data Bus Y Data Bus P Data Bus Immediate Field X0 X1 Y0 Y MUX Multiplier Pipeline Register Bit Field Unit and Barrel Shifter 48 Forwarding Register Accumulator and Rounding Unit Accumulator Shifter A (56) B (56) Shifter/Limiter 24 24

25 Processors, FPGAs, and ASICs p. 25/? Motorola DSP56301 AGU Low Address ALU High Address ALU XAB YAB PAB Triple Multiplexer EP N0 M0 R0 R4 M4 N4 N1 N2 M1 M2 Address ALU R1 R2 R5 R6 Address ALU M5 M6 N5 N6 N3 M3 R3 R7 M7 N7 Global Data Bus Program Address Bus

26 Processors, FPGAs, and ASICs p. 26/? FIR Filter in move #samples, r0 move #coeffs, r4 move #n-1, m0 move m0, m4 movep y:input, x:(r0) clr a x:(r0)+, x0 y:(r4)+, y0 rep #n-1 mac x0,y0,a x:(r0)+, x0 y:(r4)+, y0 macr x0,y0,a (r0)- movep a, y:output

27 Processors, FPGAs, and ASICs p. 27/? TI TMS320C6000 VLIW DSP src1.l1 src2 Data path A ST1 dst long dst long src 8 8 long src long dst dst.s1 src Register file A (A0 A15) src2.m1 dst src1 src2 DA1 LD1.D1 dst src1 src2 2X DA2 LD2.D2 src2 src1 dst 1X src2 Data path B ST2.M2 src1 dst src2 src1.s2 dst long dst long src long src long dst dst.l2 src Register file B (B0 B15) src1 Control register file

28 Processors, FPGAs, and ASICs p. 28/? FIR in One C6 Assembly Instruction Load a halfword (16 bits) Do this on unit D1 FIRLOOP: LDH.D1 *A1++, A2 ; Fetch next sample LDH.D2 *B1++, B2 ; Fetch next coeff. [B0] SUB.L2 B0, 1, B0 ; Decrement count [B0] B.S2 FIRLOOP ; Branch if non-zero MPY.M1X A2, B2, A3 ; Sample Coeff. ADD.L1 A4, A3, A4 ; Accumulate result Use the cross path Predicated instruction (only if B0 non-zero) Run these instruction in parallel

29 Processors, FPGAs, and ASICs p. 29/? AX88796 Ethernet Controller EECS EECK EEDI EEDO Print Port or General I/O SPP / GPIO 8K* 16 SRAM and Memory Arbiter SEEPROM I/F NE2000 Registers Host Interface Remote DMA FIFOs STA MAC Core & PHY+ Tranceiver SMDC SMDIO TPI, TPO MII I/F Ctl BUS SA[9:0] SD[15:0]

30 Ethernet Controller Registers PAGE 0 (PS1=0,PS0=0) OFFSET READ WRITE 00H Command Register ( CR ) Command Register ( CR ) 01H Page Start Register ( PSTART ) Page Start Register ( PSTART ) 02H Page Stop Register ( PSTOP ) Page Stop Register ( PSTOP ) 03H Boundary Pointer ( BNRY ) Boundary Pointer ( BNRY ) 04H Transmit Status Register ( TSR ) Transmit Page Start Address ( TPSR ) 05H Number of Collisions Register ( NCR ) Transmit Byte Count Register 0 ( TBCR0 ) 06H Current Page Register ( CPR ) Transmit Byte Count Register 1 ( TBCR1 ) 07H Interrupt Status Register ( ISR ) Interrupt Status Register ( ISR ) 08H Current Remote DMA Address 0 ( CRDA0 ) Remote Start Address Register 0 ( RSAR0 ) 09H Current Remote DMA Address 1 ( CRDA1 ) Remote Start Address Register 1 ( RSAR1 ) 0AH Reserved Remote Byte Count 0 ( RBCR0 ) 0BH Reserved Remote Byte Count 1 ( RBCR1 ) 0CH Receive Status Register Receive Configuration Register Processors, FPGAs, and ASICs p. 30/?

31 Philips SAA7114H Video Decoder Processors, FPGAs, and ASICs p. 31/?

32 SAA7114H Registers, page 1 of 7 (!) Processors, FPGAs, and ASICs p. 32/?

33 Processors, FPGAs, and ASICs p. 33/? Fixed-function: The 7400 series D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ge 1 2 1A 1B 1Y 3 D D D D D D D D 4 5 2A 2B 2Y 6 CP CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q A 3B 3Y A 4B 4Y 11 OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q Quad NAND Gate Octal D Flip-Flop