New Direction New Markets New Opportunities

Transcription

1 New Direction New Markets New Opportunities

2 An Introduction to FirmASIC World leading ASIC, FPGA and DSP replacement technology Technology FirmASIC is a CML proprietary technology that has been successfully deployed in a wide range of standard and custom product offerings. Key benefits of this technology include fast time-to market, low cost, low risk, small footprint and unsurpassed flexibility. FirmASIC provides the optimum combination of analogue, digital, firmware and memory technologies in a single platform. A growing family of approved and stable hardware platforms is available, each providing a different mix of fixed and re-definable functions. The whole essence of FirmASIC is delivering a product with the right feature mix, performance and cost for a specific target application, in the shortest possible time.

3 Custom Product Direction Opening up new markets and expanding our mutual business Targeting New business direction complementing CML s standard product line Opening up new markets Developing new product opportunities Targeting key manufacturers Wireless communications Wireline communications Industrial control Security systems Displacement strategy for ASIC, FPGA and DSP FirmASIC technology has been used successfully in a number of standard, custom and semi-custom CML product offerings The FirmASIC approach is ideally suited to the European business model

4 FirmASIC - The Advantage World leading ASIC, FPGA, and DSP replacement technology Key Benefits Fast time-to-product No multiple silicon runs Evaluation samples in typically 3 months Highly flexible Family of hardware platforms each with different functions Standard Function Image library Custom functions Low cost Reasonable NRE costs (Custom/Semi-custom) Competitive end product costs Realistic option for opportunities down to 50k units per annum Low risk Stable hardware platforms Evaluation stages allowing customer field trials Low power operation The heart of the hardware platforms Small package footprint

5 FirmASIC Has The Edge World leading ASIC, FPGA, and DSP replacement technology Advantage External + Internal NRE Costs End Product Cost Time To Production Cost to Add/Change Features Field Upgrade Market Specific Analogue Functions Size ASIC High Low Long Dev. time + multiple mask revisions High No Yes Small Gate Array Tooling:Low Other:Low Low Medium Dev. time + multiple mask revisions Medium Schematic design + testing No No Large FPGA Tooling:Zero Other:High Very High Medium Dev. time + evaluation time Medium Schematic design + testing Yes No Large DSP Tooling:Zero Other:High Low Long Code dev. time + extensive code testing Low/Medium Code dev. + extensive testing Yes No Large FirmASIC Low Low Short Low/Zero Yes Yes Small

6 Stable Hardware Platforms The key to low risk low risk Hardware A family of hardware platforms are available Each has different embedded subsystems All have an analogue interface Low power operation Platforms generally have two offerings RAM based for evaluation and early production ROM based for series production 6 platforms are available Analogue Platform 3, 4, 5, 6, 7 and 8 Input Interface Master Clock PLL Digitally Controlled Amplifiers Signal Multiplexing System Clocks Analogue Output Interface Processing Channel 1 Processing Channel 2 Auxiliary DACs Auxiliary ADCs CML Signal Processing Engine Subsystem Function Library Serial Bus 1 Serial Bus 1 GPIO Power Management RF Synthesisers

7 Function Library Function Image is the key to flexibility and low risk Firmware Wireless modem schemes FFSK/MSK, GMSK/GFSK, C4FM, 4FSK, 8FSK Coding systems Interleaving, FEC, CRC Wireline modems schemes V.32bis, V.32, V.22bis, V.22/Bell 212A, V.23/Bell 202, V.21/Bell 103 Signalling Audio band and sub-audio band signalling Programmable single tone, DTMF, call progress tones, CLI, CIDCW, CTCSS, DCS, XTCSS Audio processing Filtering, AGC, companding, scrambling, pre/de-emphasis, soft limiting Signal measurement Threshold detection, averaging, hysteresis Filtering Comprehensive range of digitally implemented filters Custom Functions Application specific, user defined, designed to order

8 FirmASIC - SoC Possibilities World leading ASIC, FPGA, and DSP replacement technology Applications ASIC, DSP, Structured ASIC and FPGA replacement SoC applications Embedded solutions Unlimited applications Wireless Wireline Sensors Industrial control Security Analogue Input/Output Interface Auxiliary GPIO SRAM Typical System Application Host Microcontroller Audio Codec Signal Conditioning Auxiliary Synthesised Clock O/Ps Program Memory Serial Flash NV Data Storage Auxiliary ADCs Auxiliary DACs Program Flash Clock Management Power Management FPGA/ASIC/DSP

9 Working with FirmASIC From definition through to delivered IC Project Flow Project Flow Definition Phase Clear understanding of the requirement, operating definition And parametric specification N Customer approval FirmASIC agreement in place Y Development Phase Utilising CML s function library and construction of custom functionality Customer Evaluation Phase Evaluation board supplied containing the custom Function Image in onboard serial Flash N Customer approval Customer Preproduction RAM based product available Function Image retained in serial Flash Y N Customer approval Y Product Production Release Custom mask product availability

10 Platform 4 Field proven hardware Hardware CBUS CSN System Clock 2 output CBUS Serial Clock DVss SSP Select Out CBUS Reply Data CBUS Command Data DVdd Xtal Xtal/Clock Vdec DVss Analogue Signal Processing Mux ADC ADC Platform 4 DAC DAC Mux SSP In SSP Clock SSP Out SSP CSN Boot Enable 2 Boot Enable 1 DVss IRQN Vdec GPIO 1 GPIO 2 GPIO System Clock 1 13 DVss 14 GPIO4 15 Platform 4 Signal Input 1 16 Signal Input 1 FB 17 Signal Input 2 18 Signal Input 2 FB AVss 22 Signal Input 3 Signal Input 3 FB Signal Output 1 23 Signal Output Aux DAC 4 35 Aux DAC 3 34 AVss 33 Aux DAC 2 32 Aux 31 AVdd 30 Aux ADC 4 29 Aux ADC 3 28 Aux ADC 2 27 Aux ADC 1 26 Signal Output 3 25 Vbias Auxiliary Systems Mux Sample Hold 1 Sample Hold 2 ADC 1 ADC 2 Ramp Profile CML Signal Processing Engine Processing Channel 1 Processing Channel 2 RAM ROM Subsystem Function Library Core Systems GPIO Boot configuration Synthesised clock 1 Synthesised clock 2 PURs Power Save Management Power Supply and Bias Generator Communication Systems SSP/SPI Port Serial Flash Interface PLL and Programmable Divider Chain Xtal Oscillator C-BUS/RS232 port

11 Platform 3 Field proven hardware Hardware DVss BOOTEN2 BOOTEN1 EPSCSN EPSO EPSCLK EPSI RS232/CBUSN CSN RTSN SYSCLOCK2 Serial Clock CTSN PGMSEL 2 (GPIO 4) DSRN DVss NRESET PGMSEL 3 Reply Data RXD Command Data TXD Analogue Signal Processing Mux ADC ADC Platform 3 DAC DAC Mux IRQN RIN or DCDN RF1 - RF1+ RFVss CP1OUT ISET1 RFVdd RF2- RF2+ RFVss CP2OUT ISET2 Charge Pump RF Clock SPAREOP1 DSPSYNC Platform a DVdd XTALN XTAL/CLOCK VDEC AUXDAC4 AUXDAC3 Flat Audio AVss AUXDAC2 AUXDAC1 AVdd AUXADC4 AUXADC3 AUXADC2 AUXADC1 AUDIOOUT VBIAS Auxiliary Systems Mux Sample Hold 1 Sample Hold 2 ADC 1 ADC 2 Ramp Profile CML Signal Processing Engine Processing Channel 1 Processing Channel 2 RAM ROM Subsystem Function Library Core Systems DSPIRQ 17 VDEC 18 GPIO 1 19 SYSCLOCK1 20 DVss 21 PGMSEL 1 (GPIO 3) ESC 22 GPIO 2 DTRN ALT 26 DISC DISCFB ALTFB 27 MICFB MIC AVss MOD1 MOD2 Communication Systems GPIO Synthesised clock 1 Synthesised clock 2 SSP/SPI Port Serial Flash Interface PURs Power Save Management PLL and Programmable Divider Chain Boot configuration Power Supply and Bias Generator Xtal Oscillator C-BUS/RS232 port RF Support Systems RF Fractional-N Synthesiser RF Fractional-N Synthesiser

12 Win-Win Example Utility meter radio control processor (SoC) Case Study Opportunity qualified, FirmASIC route chosen and feasibility study completed Product definition and contract Product design and development completed and RAM based evaluation released Customer field trials and approval Semi-custom RAM based product available Custom early/preproduction can start Custom ROM based devices supplied FirmASIC Approach Typical Custom ASIC Route Definition Contract Design Tooling Packaging Evaluation & Field Trials Design Tooling Evaluation & Field Trials Initial input Company looking to commission a new ASIC to replace existing ASIC due to concerns about process availability Months

13 Product Support Fast efficient evaluation kit and IC Evaluation PE0201 PE0002 Universal interface card PE0401 USB C-BUS PE0501

14 FirmASIC The CML Advantage World leading ASIC, FPGA, and DSP replacement technology Summary Completely new design approach Target market is ASIC, FPA, and DSP replacement Embedded auxiliary functions Analogue and digital functionality on chip Fast time-to-production Highly flexibility Low risk Low cost SoC capability