Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi

Transcription

1 Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1

2 Venue Computer Lab: Tuesdays am (Fixed) Computer Lab: Wednesday am (Every other odd weeks) Note: Due to some unpredicted problems with the lab systems, you d better to have your own Laptop with already installed Qii 14.1 web edition (get it from Altera website) with you. HSU Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 2

3 References Advanced Digital Design with the Verilog HDL, Michael D. Ciletti, Pearson publisher, Some other extra notes that will be given during the term HSU Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 3

4 Midterm Exam(s)**: Evaluation 1st ME: 5th Week 10 Marks 2nd ME: 10th Week 10 Marks Or only one ME: 8th Week 20 Marks Final Exam: Homework/Labwork: Mini Project based-on Verilog: Total: 20 Marks 45 Marks 20 Marks 20 Marks 105 Marks Projects are teamwork based, will be given at 10 th week and should be submitted one week before the final exam. ** The mark of ME can goes to the HW/LW+Project HSU Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 4

5 Project Submission Deadline Your project must be submitted up to one week after the final exam. 1 min. to 24 hours after deadline: 50% > 24 hours after deadline: 0% No copy, No cheat, Collaboration s OK You need to submit your project including: Your name and a brief description on the procedure (MS Word) Your results; codes, diagrams, calculations, figures, altogether into a zipped file under your name must be sent to mhshahrokh@ieee.org Type FPGA-Project in the subject line Make sure you ve received a confirmation upon your submission HSU Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 5

6 Chapter 01 Introduction HSU Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 6

7 Intro ASIC (pronounce a-sick): Application Specific Integrated Circuit microchip that is customized for use in a particular application. Examples of ICs that are not ASICs: Standard parts such as: memory chips ROMs, DRAM, and SRAM; microprocessors; TTL or TTL-equivalent ICs from SSI to GSI levels. Examples of ICs that are ASICs: A chip for a toy bear that talks; a chip for a satellite; a chip designed to handle the interface between memory and a microprocessor for a workstation CPU; and a chip containing a microprocessor as a cell together with other logics. As a general rule, if you can find it in a data book, then it is probably not an ASIC, but there are some exceptions. For example, two ICs that might or might not be considered ASICs are a controller chip for a PC and a chip for a modem. Both of these examples are specific to an application (as an ASIC) but are sold to many different system vendors (as a standard part). ASICs such as these are sometimes called application-specific standard products ( ASSPs ). 7

8 What does do an ASIC designer An ASIC design engineer typically works within a team that is responsible for all aspects of design activities, including architecture definition, design specification, design flow development, logic design, and verification. She/he is typically responsible for designing and delivering large, complex ASIC designs They deliver efficient design methodology on industry-standard design tools. 8

9 Who Can Become an ASIC Engineer At least possess a bachelor's degree in electrical engineering, computer engineering, or a related field; however, a master's degree is often preferred Several years of experience in ASIC design Diverse background in verification methodologies Strong programming skills in VHDL, Verilog, SystemVerilog, object-oriented, C++, and logic simulation familiarity Strong understanding of computer architecture, strong communication skills, and the ability to operate well in diverse environments A team player and function effectively in a group setting they should also be able to work independently with minimal supervision. 9

10 What s an FPGA FPGAs (Field Programmable Gate Arrays) are amazing devices that now allow the average person to create their very own digital circuits. It is up to you (the designer) to create a configuration file, often called a bit file, for the FPGA. Once loaded, the FPGA will behave like the digital circuit you designed! FPGAs have two huge advantages over other ways of building hardware: First, they enable you to build exactly the hardware you need, instead of having to use the same ASSP all your competitors are using Second, avoid to undertake the time, cost, and risk of an application-specific integrated circuit (ASIC) design 10

11 What s an FPGA Ability to customize the FPGA means that often, in an FPGA, you can do operations in a simpler, faster, more energy-efficient way than they could be done in the microprocessor cores of an ASSP. Still we didn t answer to this question: what s an FPGA? An FPGA is a semiconductor device on which the function can be defined after manufacturing. An FPGA enables you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field hence the term field programmable. 11

12 What s an FPGA The interior structure of an FPGA: 12

13 FPGA Advantages Designing with FPGA: Faster, Cheaper Ideal for customized designs Product differentiation in a fast-changing market Offer the advantages of high integration High complexity, density, reliability Low cost, power consumption, small physical size Avoid the problems of ASICs high NRE cost, long delay in design and testing increasingly demanding electrical issues 13

14 FPGA Advantages Very fast custom logic massively parallel operation Faster than microcontrollers and microprocessors much faster than DSP engines More flexible than dedicated chipsets allows unlimited product differentiation More affordable and less risky than ASICs NRE, minimum order size, or inventory risk Reprogrammable at any time in design, in manufacturing, after installation 14

15 User Expectations Logic capacity at reasonable cost 100,000 to a several million gates On-chip fast RAM Clock speed 150 MHz and above, global clocks, clock management Versatile I/O To accommodate a variety of standards Design effort and time synthesis, fast compile times, tested and proven cores Power consumption must stay within reasonable limits 15

16 Field Programmable Device Basic Section of FPD: Logical Block Routing (Switch Matrix) Input Output Block More Advanced FPD Contains: On-chip Memory Embedded Processor Clock Management High-Speed Transceiver 16

17 Field-Programmable Gate Arrays An FPGA may be viewed as sea-of-gates which can be quickly configured to the desired application right on-thefield. It may also be re-configured at any point of time to another application, provided the external hardware interface circuitry doesn t need any change to suit the new application. 17

18 Field-Programmable Gate Arrays Program logic cells, I/O pads & interconnects None of the mask layers are customized. The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic (flip-flops). A matrix of programmable interconnect surrounds the basic logic cells. Programmable I/O cells surround the core. Design turnaround is a few hours. 18

19 Field-Programmable Gate Arrays All FPGAs are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. The exact type, size, and number of the programmable basic logic cells varies tremendously. 19

20 FPGA Structures Routing Local ( Local connections ) CLB to CLB CLB to IOB Global ( Span all section of chip ) Global Set/Reset Global Tri-Sate Clock 20

21 FPGA Structures Configurable Logic Block (CLB) Two identical slices in each CLB Two LUT in each slice RAM Blocks Xilinx core generator Synplify ( Best Synthesizer in the world ) CLK - Delay Locked Loop (DLL) 21

22 Reconfigurable Systems Using FPGAs FPGAs may be reconfigured many times Classified as Static or Dynamic A static reconfiguration refers to having the ability to reconfigure a system only once before execution, but once programmed, its configuration remains on the FPGA for the duration of the application. A dynamic reconfiguration is defined as the selective updating of a sub-section of an FPGA s programmable logic and routing resources, while the remainder of the device s programmable resources continues to function without interruption. 22

23 Development tools for FPGA Simulator for waveform analysis Synthesis for logic optimization Mapping the design on an FPGA Place and route for creating bit stream of the design Programmer for programming the bit stream in an EPROM 23

24 Ten Steps to Realize an FPGA 1. Formulate the detailed product specification. 2. Develop the detailed hardware architecture. 3. Code the architecture in a hardware design language, e.g. Verilog or VHDL. 4. Compile and simulate the design and verify the functionality. 5. Synthesize to map on to a target FPGA device and optimize the logic. 6. Run the place and route tool for creating bit stream of the design application. 7. Program the bit stream generated in step 6 in a serial EPROM. 8. Design and fabricate the printed circuit board to accommodate the FPGA, the serial EPROM, and other components required for the end application. 9. Solder the components and test the populated FPGA board using the development system, logic analyzer, pattern generator, etc. 10.Download the application bit stream from the development system or the onboard serial EPROM and verify the system functionality. 24

25 Types of FPGA Developer Board Spartan-3 FPGAs of Xilinx Low-cost, high-performance logic solution for high-volume, consumer-oriented applications Densities up to 74,880 logic cells (5 million gates) Homework: Find out how does the Spartan-3 structure look like with emphasize on its CLBs (Configure Logic Blocks), LUTs (Look Up Tables), and IOBs (Input/Output Blocks). Stratix Series FPGA of Altera High density and high speed device High bandwidth Integrated transceiver variants Design entire systems-on-a-chip 25

26 DE1-SoC Board The FPGA Developer Board Back Side Front Side 26

27 The FPGA Developer Board DE1-SoC Block Diagram 27

28 The FPGA Developer Board DE1-SoC Board FPGA Device Cyclone V SoC 5CSEMA5F31C6 Device Dual-core ARM Cortex-A9 (HPS) ARM-based hard processor system 85K Programmable Logic Elements 4,450 Kbits embedded memory 6 Fractional PLLs 2 Hard Memory Controllers Configuration and Debug Serial Configuration device EPCS128 on FPGA On-Board USB Blaster II (Normal type B USB connector) Memory Device 64MB (32Mx16) SDRAM on FPGA 1GB (2x256Mx16) DDR3 SDRAM on HPS Micro SD Card Socket on HPS 28

29 The FPGA Developer Board Communication Two Port USB 2.0 Host (ULPI interface with USB type A connector) USB to UART (micro USB type B connector) 10/100/1000 Ethernet PS/2 mouse/keyboard IR Emitter/Receiver Connectors Two 40-pin Expansion Headers (voltage levels: 3.3V) One 10-pin ADC Input Header One LTC connector (One Serial Peripheral Interface (SPI) Master, one I2C and one GPIO interface ) 29

30 The FPGA Developer Board Display 24-bit VGA DAC Audio 24-bit CODEC, Line-in, line-out, and microphone-in jacks Video Input TV Decoder (NTSC/PAL/SECAM) and TV-in connector ADC sample rate: 500 KSPS Channel number: 8 Resolution: 12 bits Analog input range : 0 ~ V 30

31 The FPGA Developer Board Switches, Buttons and Indicators 4 User Keys (FPGA x4) 10 User switches (FPGA x10) 11 User LEDs (FPGA x10 ; HPS x 1) 2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n) Six 7-segment displays Sensors G-Sensor on HPS Power 12V DC input 31

32 Homework A digital camera can store JPEG images of resolution pixels. Assuming 24 bit true color and an average compression of 10, estimate the memory requirements for storing a maximum of 200 images in the camera. Estimate the FIFO size required in assignment 1.2 for storing 1 s of the compressed bit stream in 4:4:4 format if compression effected is 10. Estimate the FIFO size in assignment 1.2 if the video is changed to SVGA format, whose picture size is pixels. A digital cable TV transmitter is required to process up to 50 channels at a picture resolution of pixels. Each of these channels is timemultiplexed. The picture is non-interlaced and the frame rate is 30 per second. Assuming 4:2:0 format and an average compression of 20, determine the frequency of operation of the video encoder, which transmits compressed video sequence over the cable. Also estimate the transmission rate over a serial channel. Make reasonable assumptions. 32

33 Next Session Design of Combinational and Sequential Circuits Using Verilog You need to be prepared by: Deep understanding of Combinational and Sequential Logic Systems K-Map Simplification Algorithm Quine McCluskey Simplification Algorithm Algorithmic State Machine (ASM) Finite State Machine (FSM) State Diagrams and State Tables 33