Adding C Programmability to Data Path Design

Transcription

1 Adding C Programmability to Data Path Design Gert Goossens Sr. Director R&D, Synopsys May 6,

2 Smart Products Drive SoC Developments Feature-Rich Multi-Sensing Multi-Output Wirelessly Connected Always-On Green Need for reusable SoC platforms SoC platforms must become software programmable, without compromising PPA (performance, power, area) May 6,

3 Programmable s in SoCs Control Control DDR PHY DDR controller PCIe PHY PCIe controller HDMI PHY HDMI controller USB PHY USB controller 10G PHY Ethernet controller SATA PHY SATA controller MIPI D-PHY CSI-2, DSI controller MIPI M-PHY UniPro, UFS, CSI-3, DigRFv4 controller AMBA 3 AXI & AMBA 2.0 AHB AMBA APB I2C GPIO UART Signal Processing ADC DAC Wireless Modem Radio Front End Audio Audio Codecs Video / Imaging Video Front End SD/MMC controller Embedded Memories (SRAM, ROM, NVM) May 6,

4 Solutions Spectrum Microprocessor Extensible Application-Specific P / DSP Programmable Hardwired Maximize performance Minimize power consumption Architectural specialization Parallelism: instructionlevel, data-level, task-level Architectural specialization Parallelism: instruction-level, data-level, task-level Power-optimised RTL generation Power-gating of cores ASIP = Application-Specific Instruction-set Programmability Support changing requirements, product differentiation, new features without SoC respin! Quick algorithm mapping from C to silicon, with easy debugging May 6,

5 ASIP Architectural Optimization Space ASIP architectural optimization space Parallelism Specialization Instructionlevel parallelism Datalevel parallelism Tasklevel parallelism App.- specific data types App.-specific instructions Connectivity & storage matching application s data-flow Pipeline Orthogonal instruction set (VLIW) Encoded instruction set Vector processing (SIMD) Multicore Multithreading Integer, fractional, floating-point, bits, complex, vector Distributed regs, sub-ranges Multiple mem s, sub-ranges Pipeline depth Architectural space beyond configurable templates Can be captured by processor description language Architectural exploration enabled by retargetable ASIP design tools App.-spec. memory addressing Direct, indirect, postmodification, indexed, stack indirect App.-spec. data processing Any exotic operator Single or multi-cycle App.-spec. control processing Jumps, subroutines, interrupts, HW do-loops, residual control, predication Relative or absolute, address range, delay slots Hazards: HW/SW stall, bypass May 6,

6 ASIP Designer Retargetable ASIP Design Tool Typical users: ASIC/SoC design teams May 6,

7 ASIP Designer History IP Designer description language: nml Roots in architectural exploration and retargetable compilation Designer description language: LISA Roots in modeling and fast simulation ASIP Designer description language: nml Consolidated product, combining strengths of IP Designer and Designer Stepwise deployment in time frame Legacy products remain available May 6,

8 Adding C Programmability to SoC Design CDFG Application C C FRONT-END COMPILATION ENGINE (PHASE COUPLING) * + ISG model nml X[2] nml FRONT-END mul Y[2] SOURCE-LEVEL TRANSF. CODE SELECTION REGISTER ALLOCATION SCHEDULING CODE EMISSION Machine code Elf / Dwarf add A[2] A[2] sub Graph-based compilation technology combines retargetability with high code efficiency Instruction-set graph (ISG) Graph-based optimization algorithms operate on (any) ISG Closer to HW than other compilers machine models HW resources, data types, connectivity, instruction encoding, instruction-level parallelism, instruction pipeline Supports irregular architectures Enables rapid and architectural exploration with compiler-in-the-loop Enables algorithm development in C, even for highly specialized ASIPs May 6,

9 TM Applicable to Any Application Domain Medical Audio Video & imaging Graphics Wireless Wireline Network processing High-perf. computing Automotive Crypto & identification Industrial Publicly announced IP Designer and Designer customers May 6,

10 Examples: Wireless Communication Microprocessor Domain-Specific Application-Specific BoT [1] Configurable innermodem processor LTE(A) + 11ac + 11ad + WPAN + GPS + DVBT... Programmable FlexFEC [2] 3-standard FEC engine LDPC + Turbo + Viterbi BLOX [1] Single-function sliced accelerators FFT LDPC Matrix inv. Hardwired [1] L. Van der Perre, Radios in need of (Multi-)ASIP - wanted: flexibility and energy efficiency, Synopsys User Group, Munich, May 2013 [2] F. Naessens, Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding, IP-SoC Conference, Dec May 6,

11 Examples: Wireless Communication Microprocessor Domain-Specific Application-Specific BoT [1] Configurable innermodem processor LTE(A) + 11ac + 11ad + WPAN + GPS + DVBT... Programmable FlexFEC [2] 3-standard FEC engine LDPC + Turbo + Viterbi BLOX [1] Single-function sliced accelerators FFT LDPC Matrix inv. Hardwired [1] L. Van der Perre, Radios in need of (Multi-)ASIP - wanted: flexibility and energy efficiency, Synopsys User Group, Munich, May 2013 [2] F. Naessens, Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding, IP-SoC Conference, Dec May 6,

12 BOT Configurable Inner-Modem [1] Mixed scalar/vector processor 10-slot VLIW: 3 scalar, 2 vector L/S, 3 vector compute, 2 pack/unpack Vector compute units with increased specialization VU1: alu, mul, shift VU2: alu, cabs, interleave, shift VU3: alu, recip, sqrt, tan, cexp, slope, interleave, softdemap Vector packing/unpacking Low power: clock gating exploits low duty cycle C programmable Vector RF BoT profile average: 45mW (40nm@400MHz) May 6,

13 Examples: Wireless Communication Microprocessor Domain-Specific Application-Specific BoT [1] Configurable innermodem processor LTE(A) + 11ac + 11ad + WPAN + GPS + DVBT... Programmable FlexFEC [2] 3-standard FEC engine LDPC + Turbo + Viterbi BLOX [1] Single-function sliced accelerators FFT LDPC Matrix inv. Hardwired [1] L. Van der Perre, Radios in need of (Multi-)ASIP - wanted: flexibility and energy efficiency, Synopsys User Group, Munich, May 2013 [2] F. Naessens, Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding, IP-SoC Conference, Dec May 6,

14 FlexFEC 3-Standard Forward Error-Correction (FEC) Engine [2] Application-specific mixed scalar/vector processor SIMD: n-way x 8-bit VLIW: 1 scalar and 5 vector issue slots App.-specific primitive functions LDPC decode, Turbo decode, Viterbi decode (e.g. add-compareselect), special addressing modes App.-specific complex instructions abs() + abs(), element-wise vector shift, cross correlation with programmable spreading code Transparent background memory access through lookup address generator C programmable May 6,

15 FlexFEC 3-Standard Forward Error-Correction (FEC) Engine [2] Specialization: e.g. LDPC decode function vq() Standard 32-bit RISC 3,040 cycles (mild) specialization 32-bit RISC with predicated add/sub 2,707 cycles data-level parallelism 96-lane, 16-bit SIMD with vectorpredicated add/sub 32 cycles specialization 96-lane, 16-bit SIMD with LDPC decode instruction (synthesized from C code) 1 cycle Note: cycle counts obtained for randomized input data May 6,

16 FlexFEC 3-Standard Forward Error-Correction (FEC) Engine [2] Instruction-level parallelism: 1 scalar + 5 vector (SIMD) slots C compiler efficiently exploits VLIW issue slots May 6,

17 Examples: Wireless Communication Microprocessor Domain-Specific Application-Specific BoT [1] Configurable innermodem processor LTE(A) + 11ac + 11ad + WPAN + GPS + DVBT... Programmable FlexFEC [2] 3-standard FEC engine LDPC + Turbo + Viterbi BLOX [1] Single-function sliced accelerators FFT LDPC Matrix inv. Hardwired [1] L. Van der Perre, Radios in need of (Multi-)ASIP - wanted: flexibility and energy efficiency, Synopsys User Group, Munich, May 2013 [2] F. Naessens, Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding, IP-SoC Conference, Dec May 6,

18 BLOX Single-Function Sliced Accelerators [1] Highly regular vector processors In each SIMD lane, stack elementary operators, limited HW multiplexing Low power, thanks to Short active wires and modularity Simple operators Very wide register-files (asymmetric access) Examples FFT for 11ac LDPC for 11ac Matrix ops FFT for 11ad LDPC for 11ad C programmable (but requires C code refactoring) May 6,

19 Conclusions ASIP design tools introduce C programmability in SoC design Better design reuse Functional enhancements even after tapeout Productivity increase by raising abstraction from RTL to C Compiler-in-the-Loop concept Rapid architectural exploration Highly differentiating architectures Full control on PPA (performance, power, area) Software development kit for end users is available automatically Same tool supports wide range of IP needs Royalty-free solutions May 6,