Digital system (SoC) design for lowcomplexity. Hyun Kim
|
|
- Marylou Pope
- 5 years ago
- Views:
Transcription
1 Digital system (SoC) design for lowcomplexity multimedia processing Hyun Kim
2 SoC Design for Multimedia Systems Goal : Reducing computational complexity & power consumption of state-ofthe-art technologies based on multimedia and big-data Method : Speed-up and Low-power through HW acceleration & optimization Two ways for acceleration : GPU porting / Digital circuit design GPU porting Highly optimized for parallel data processing and matrix operations Various development frameworks for DNN Size & Cost & Power consumption problem! Digital Circuit (SoC) Design Implementation is more difficult than GPU but, Fast & Small & Cheap & Low power Comparison between GPU porting & FPGA design GPU (Tesla K40) Caffe + CuDNN FPGA (Virtex 7 485T) Microsoft Catapult project 2015 Power 235W ~25W FPGA design consumes about one tenth of power compared to GPU porting High flexibility to apply various optimization techniques More than x100 speed-up can be achieved by various schemes Digital circuit design is the best option for acceleration and optimization!
3 Platform Multimedia Processing System on Chip (SoC) Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Low-Power Video Recording System Battery-operated & Video Codec Embedded compression Preprocessing Video Coding Standard Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
4 Low-Power Video Recording System Goal : Implement and optimize a HW-based low-power video recording system considering the trade-off between the performance and power consumption HW implementation Only for meaningful video data Always operating that will be stored for a long time Optimal operation scheme Camera input LWC Encoder Temp Mode LWC Decoder DRAM Perm Mode H.264 NAND FLASH Trade-off between performance & power consumption Front-end verification on FPGA board Contribution 1) HW Implementation for low-power VRS which achieves power saving up to 72.5% 2) Optimized power solution based on trade-off between power & performance Published in IEEE Transactions on Multimedia
5 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Preprocessing Video Coding Standard Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
6 Power-Scaling for Video Compression Goal : Find the optimal combination of low-power algorithms achieving best performance in the HW-based video encoder Flowchart Formulation for power estimation Trade-off between power consumption & performance Optimal Combination Selected Combination Power Saving(%) Power-level table for real-time application Candidate Combination Machine Learning Methodology Experimental results Contribution 1) Optimizing video coding standards based on trade-off between power & performance 2) HW Implementation of low-power video codec More than 2dB enhancement at 40% power saving Published in IEEE Transactions on VLSI
7 Optimized SRAM Size for Video Codec Goal : Decide optimal SRAM sizes for achieving best performance in HW-based video codec Flowchart Various SRAMs in video codec and their different sensitivities to error Formulation Optimal size Optimization Experimental results Contribution 1) Optimized SRAM size solution of HW-based video codec for minimizing the performance degradation considering trade-off between HW resource & performance Published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems
8 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Embedded compression Preprocessing Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
9 Low-cost Hardware Design of 1D SPIHT Goal : Implement a low-cost HW-based embedded compression module (1-D DWT+SPIHT) Block diagram Experimental results Implementation schemes Partitioned SPIHT Bit-allocation Contribution 1) A low-cost HW design of a 1D DWT+SPIHT with partitioned SPIHT and bit allocation 2) Optimization considering the trade-off between HW resource and performance -Reduce HW gate count and memory by 59% and 75% with only a slight PSNR degradation Published in IEEE Transactions on Consumer Electronics
10 Optimized DWT and SPIHT Goal : Optimize the R-D performance of HW-based DWT+SPIHT modules Structure of1-d DWT and SPIHT Correlation analysis between DWT coeff. & loss Machine Learning Methodology Formulation and Optimization Optimal solution of compression ratio for each coding block Experimental Results Contribution Examples before/after applying the scheme 1) Optimizing the performance of DWT and SPIHT 2) Applying the proposed scheme to HW DWT+SPIHT Accepted in IEEE Transactions on Multimedia
11 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Preprocessing Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
12 Low-Power Video Surveillance System Goal : Implement low-power HW-based video surveillance with the highest power saving Inserting BG sub. into HW-based pipeline structure Flowchart of HW-based BG sub. using only the information generated during video compression Operation of coding standard in low-power video surveillance (MK C, MK P ) Classification MB CURR coding option IME option for MB NCO-LO (FG, FG) Strong FG Regular (FME & IP) Regular SR & BM (FG,BG) Object Boundary Only IP Regular SR & BM (BG,FG) Uncovered BG Only IP Regular SR & BM (BG,BG) Strong BG SKIP mode Small SR & BM BG sub. results Experimental results Contribution 1) Performing BG sub. w/o additional resources considering HW structure of video codec 2) Achieving best power savings with negligible PSNR degradation in video surveillance Published in IEEE Transactions on Consumer Electronics
13 Real-time HW Design for Retinex Goal : Implement Low-power/Real-time HW IP of Retinex algorithm Retinex algorithm - Pre-processing for improving the brightness of the image in the dark part of the input image - Emphasize reflection components by separating illumination component and reflection component - Require a large amount of computations Dark part : image compression efficiency and recognition accuracy are very low it is very important to improve the brightness of the image Block diagram Examples before/after applying Retinex FPGA implementation results -Implemented on ZC706 FPGA board -Achieving real-time operation (FHD 60fps) -20% LUT reduction and 53% FF reduction compared to previous design -No frame memory Low-power & Fast CES2018 demo Contribution 1) Real-time HW implementation of Retinex and resource optimization for HW design Exhibited at 2018 CES Submitted in IEEE Transactions on Consumer Electronics
Scalable and Dynamically Updatable Lookup Engine for Decision-trees on FPGA
Scalable and Dynamically Updatable Lookup Engine for Decision-trees on FPGA Yun R. Qu, Viktor K. Prasanna Ming Hsieh Dept. of Electrical Engineering University of Southern California Los Angeles, CA 90089
More informationImproving Energy Efficiency of Block-Matching Motion Estimation Using Dynamic Partial Reconfiguration
, pp.517-521 http://dx.doi.org/10.14257/astl.2015.1 Improving Energy Efficiency of Block-Matching Motion Estimation Using Dynamic Partial Reconfiguration Jooheung Lee 1 and Jungwon Cho 2, * 1 Dept. of
More informationDNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs
IBM Research AI Systems Day DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs Xiaofan Zhang 1, Junsong Wang 2, Chao Zhu 2, Yonghua Lin 2, Jinjun Xiong 3, Wen-mei
More informationSmart Video Transcoding Solution for Surveillance Applications. White Paper. AvidBeam Technologies 12/2/15
Smart Video Transcoding Solution for Surveillance Applications AvidBeam Technologies 12/2/15 Table of Contents Introduction... 2 AvidBeam Smart Video Transcoding Solution... 2 Portability Solution for
More informationA Scalable Speech Recognizer with Deep-Neural-Network Acoustic Models
A Scalable Speech Recognizer with Deep-Neural-Network Acoustic Models and Voice-Activated Power Gating Michael Price*, James Glass, Anantha Chandrakasan MIT, Cambridge, MA * now at Analog Devices, Cambridge,
More informationMohsen Imani. University of California San Diego. System Energy Efficiency Lab seelab.ucsd.edu
Mohsen Imani University of California San Diego Winter 2016 Technology Trend for IoT http://www.flashmemorysummit.com/english/collaterals/proceedi ngs/2014/20140807_304c_hill.pdf 2 Motivation IoT significantly
More informationSelf-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, and Stefan Wildermann Hardware/Software Co-Design, Friedrich-Alexander-Universität
More informationHotChips An innovative HD video and digital image processor for low-cost digital entertainment products. Deepu Talla.
HotChips 2007 An innovative HD video and digital image processor for low-cost digital entertainment products Deepu Talla Texas Instruments 1 Salient features of the SoC HD video encode and decode using
More informationIndian Silicon Technologies 2013
SI.No Topics IEEE YEAR 1. An RFID Based Solution for Real-Time Patient Surveillance and data Processing Bio- Metric System using FPGA 2. Real-time Binary Shape Matching System Based on FPGA 3. An Optimized
More informationFPGA Provides Speedy Data Compression for Hyperspectral Imagery
FPGA Provides Speedy Data Compression for Hyperspectral Imagery Engineers implement the Fast Lossless compression algorithm on a Virtex-5 FPGA; this implementation provides the ability to keep up with
More informationXPU A Programmable FPGA Accelerator for Diverse Workloads
XPU A Programmable FPGA Accelerator for Diverse Workloads Jian Ouyang, 1 (ouyangjian@baidu.com) Ephrem Wu, 2 Jing Wang, 1 Yupeng Li, 1 Hanlin Xie 1 1 Baidu, Inc. 2 Xilinx Outlines Background - FPGA for
More informationFingerprint Image Compression
Fingerprint Image Compression Ms.Mansi Kambli 1*,Ms.Shalini Bhatia 2 * Student 1*, Professor 2 * Thadomal Shahani Engineering College * 1,2 Abstract Modified Set Partitioning in Hierarchical Tree with
More informationA 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation Abstract: The power budget is expected to limit the portion of the chip that we can power ON at the upcoming technology nodes. This problem,
More informationSystem Verification of Hardware Optimization Based on Edge Detection
Circuits and Systems, 2013, 4, 293-298 http://dx.doi.org/10.4236/cs.2013.43040 Published Online July 2013 (http://www.scirp.org/journal/cs) System Verification of Hardware Optimization Based on Edge Detection
More informationVLSI Implementation of Daubechies Wavelet Filter for Image Compression
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 7, Issue 6, Ver. I (Nov.-Dec. 2017), PP 13-17 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org VLSI Implementation of Daubechies
More informationIntroduction to Embedded Systems
Introduction to Embedded Systems Outline Embedded systems overview What is embedded system Characteristics Elements of embedded system Trends in embedded system Design cycle 2 Computing Systems Most of
More informationMulticore SoC is coming. Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems. Source: 2007 ISSCC and IDF.
Scalable and Reconfigurable Stream Processor for Mobile Multimedia Systems Liang-Gee Chen Distinguished Professor General Director, SOC Center National Taiwan University DSP/IC Design Lab, GIEE, NTU 1
More informationFPGA IMPLEMENTATION OF BIT PLANE ENTROPY ENCODER FOR 3 D DWT BASED VIDEO COMPRESSION
FPGA IMPLEMENTATION OF BIT PLANE ENTROPY ENCODER FOR 3 D DWT BASED VIDEO COMPRESSION 1 GOPIKA G NAIR, 2 SABI S. 1 M. Tech. Scholar (Embedded Systems), ECE department, SBCE, Pattoor, Kerala, India, Email:
More informationPANEL MMEDIA Challenges in Multimedia
WWW.IARIA.ORG PANEL MMEDIA Challenges in Multimedia Prof. Dr. Petre DINI Concordia University, Canada China Space Agency Center, China IARIA Organization petre@iaria.org Petre DINI 1 Panel Moderator Petre
More informationStar Diamond-Diamond Search Block Matching Motion Estimation Algorithm for H.264/AVC Video Codec
Star Diamond-Diamond Search Block Matching Motion Estimation Algorithm for H.264/AVC Video Codec Satish Kumar Sahu 1* and Dolley Shukla 2 Electronics Telecommunication Department, SSTC, SSGI, FET, Junwani,
More informationORBX 2 Technical Introduction. October 2013
ORBX 2 Technical Introduction October 2013 Summary The ORBX 2 video codec is a next generation video codec designed specifically to fulfill the requirements for low latency real time video streaming. It
More informationImplementing Long-term Recurrent Convolutional Network Using HLS on POWER System
Implementing Long-term Recurrent Convolutional Network Using HLS on POWER System Xiaofan Zhang1, Mohamed El Hadedy1, Wen-mei Hwu1, Nam Sung Kim1, Jinjun Xiong2, Deming Chen1 1 University of Illinois Urbana-Champaign
More informationFPGA Implementation of Image Compression Using SPIHT Algorithm
FPGA Implementation of Image Compression Using SPIHT Algorithm Mr.Vipin V 1, Miranda Mathews 2, Assistant professor, Department of ECE, St. Joseph's College of Engineering & Technology, Palai, Kerala,
More informationComputer Architectures for Deep Learning. Ethan Dell and Daniyal Iqbal
Computer Architectures for Deep Learning Ethan Dell and Daniyal Iqbal Agenda Introduction to Deep Learning Challenges Architectural Solutions Hardware Architectures CPUs GPUs Accelerators FPGAs SOCs ASICs
More informationMassively Parallel Computing on Silicon: SIMD Implementations. V.M.. Brea Univ. of Santiago de Compostela Spain
Massively Parallel Computing on Silicon: SIMD Implementations V.M.. Brea Univ. of Santiago de Compostela Spain GOAL Give an overview on the state-of of-the- art of Digital on-chip CMOS SIMD Solutions,
More informationA LOW-COMPLEXITY AND LOSSLESS REFERENCE FRAME ENCODER ALGORITHM FOR VIDEO CODING
2014 IEEE International Conference on Acoustic, Speech and Signal Processing (ICASSP) A LOW-COMPLEXITY AND LOSSLESS REFERENCE FRAME ENCODER ALGORITHM FOR VIDEO CODING Dieison Silveira, Guilherme Povala,
More informationThroughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks Naveen Suda, Vikas Chandra *, Ganesh Dasika *, Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-sun Seo, Yu
More informationLSN 6 Programmable Logic Devices
LSN 6 Programmable Logic Devices Department of Engineering Technology LSN 6 What Are PLDs? Functionless devices in base form Require programming to operate The logic function of the device is programmed
More informationDCT-BASED IMAGE COMPRESSION USING WAVELET-BASED ALGORITHM WITH EFFICIENT DEBLOCKING FILTER
DCT-BASED IMAGE COMPRESSION USING WAVELET-BASED ALGORITHM WITH EFFICIENT DEBLOCKING FILTER Wen-Chien Yan and Yen-Yu Chen Department of Information Management, Chung Chou Institution of Technology 6, Line
More informationReview and Implementation of DWT based Scalable Video Coding with Scalable Motion Coding.
Project Title: Review and Implementation of DWT based Scalable Video Coding with Scalable Motion Coding. Midterm Report CS 584 Multimedia Communications Submitted by: Syed Jawwad Bukhari 2004-03-0028 About
More informationFRAME-LEVEL QUALITY AND MEMORY TRAFFIC ALLOCATION FOR LOSSY EMBEDDED COMPRESSION IN VIDEO CODEC SYSTEMS
FRAME-LEVEL QUALITY AD MEMORY TRAFFIC ALLOCATIO FOR LOSSY EMBEDDED COMPRESSIO I VIDEO CODEC SYSTEMS Li Guo, Dajiang Zhou, Shinji Kimura, and Satoshi Goto Graduate School of Information, Production and
More informationIntroduction of the Research Based on FPGA at NICS
Introduction of the Research Based on FPGA at NICS Rong Luo Nano Integrated Circuits and Systems Lab, Department of Electronic Engineering, Tsinghua University Beijing, 100084, China 1 luorong@tsinghua.edu.cn
More informationA 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias. David Kidd August 26, 2013
A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias David Kidd August 26, 2013 1 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved. Agenda DDC transistor and PowerShrink platform
More informationParallel graph traversal for FPGA
LETTER IEICE Electronics Express, Vol.11, No.7, 1 6 Parallel graph traversal for FPGA Shice Ni a), Yong Dou, Dan Zou, Rongchun Li, and Qiang Wang National Laboratory for Parallel and Distributed Processing,
More informationHigh-Performance Data Loading and Augmentation for Deep Neural Network Training
High-Performance Data Loading and Augmentation for Deep Neural Network Training Trevor Gale tgale@ece.neu.edu Steven Eliuk steven.eliuk@gmail.com Cameron Upright c.upright@samsung.com Roadmap 1. The General-Purpose
More informationDeep learning in MATLAB From Concept to CUDA Code
Deep learning in MATLAB From Concept to CUDA Code Roy Fahn Applications Engineer Systematics royf@systematics.co.il 03-7660111 Ram Kokku Principal Engineer MathWorks ram.kokku@mathworks.com 2017 The MathWorks,
More informationN RISCE 2K18 ISSN International Journal of Advance Research and Innovation
FPGA IMPLEMENTATION OF LOW COMPLEXITY DE-BLOCKING FILTER FOR H.264 COMPRESSION STANDARD S.Nisha 1 (nishasubu94@gmail.com), PG Scholar,Gnanamani College of Technology. Mr.E.Sathishkumar M.E.,(Ph.D),Assistant
More informationCo-synthesis and Accelerator based Embedded System Design
Co-synthesis and Accelerator based Embedded System Design COE838: Embedded Computer System http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer
More informationHardware Design I Chap. 10 Design of microprocessor
Hardware Design I Chap. 0 Design of microprocessor E-mail: shimada@is.naist.jp Outline What is microprocessor? Microprocessor from sequential machine viewpoint Microprocessor and Neumann computer Memory
More informationAltera SDK for OpenCL
Altera SDK for OpenCL A novel SDK that opens up the world of FPGAs to today s developers Altera Technology Roadshow 2013 Today s News Altera today announces its SDK for OpenCL Altera Joins Khronos Group
More informationHEAD HardwarE Accelerated Deduplication
HEAD HardwarE Accelerated Deduplication Final Report CS710 Computing Acceleration with FPGA December 9, 2016 Insu Jang Seikwon Kim Seonyoung Lee Executive Summary A-Z development of deduplication SW version
More informationDesign of Embedded DSP Processors Unit 5: Data access. 9/11/2017 Unit 5 of TSEA H1 1
Design of Embedded DSP Processors Unit 5: Data access 9/11/2017 Unit 5 of TSEA26-2017 H1 1 Data memory in a Processor Store Data FIFO supporting DSP executions Computing buffer Parameter storage Access
More informationLow-complexity video compression based on 3-D DWT and fast entropy coding
Low-complexity video compression based on 3-D DWT and fast entropy coding Evgeny Belyaev Tampere University of Technology Department of Signal Processing, Computational Imaging Group April 8, Evgeny Belyaev
More informationThe Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
More informationOptimized Progressive Coding of Stereo Images Using Discrete Wavelet Transform
Optimized Progressive Coding of Stereo Images Using Discrete Wavelet Transform Torsten Palfner, Alexander Mali and Erika Müller Institute of Telecommunications and Information Technology, University of
More informationThe Implement of MPEG-4 Video Encoding Based on NiosII Embedded Platform
The Implement of MPEG-4 Video Encoding Based on NiosII Embedded Platform Fugang Duan School of Optical-Electrical and Computer Engineering, USST Shanghai, China E-mail: dfgvvvdfgvvv@126.com Zhan Shi School
More informationHardware Architecture For Fast Intra Mode and Direction Prediction In Real-Time MPEG-2 to H.264/AVC Transcoder
Hardware Architecture For Fast Intra Mode and Direction Prediction In Real-Time MPEG-2 to H.264/AVC Transcoder Tarek A Elarabi, Randa Ayoubi, Hanan Mahmoud University of Louisiana at Lafayette, CACS Lafayette,
More informationAll MSEE students are required to take the following two core courses: Linear systems Probability and Random Processes
MSEE Curriculum All MSEE students are required to take the following two core courses: 3531-571 Linear systems 3531-507 Probability and Random Processes The course requirements for students majoring in
More informationISSCC 2006 / SESSION 22 / LOW POWER MULTIMEDIA / 22.1
ISSCC 26 / SESSION 22 / LOW POWER MULTIMEDIA / 22.1 22.1 A 125µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications Tsu-Ming Liu 1, Ting-An Lin 2, Sheng-Zen Wang 2, Wen-Ping Lee
More informationAn Introduction to Programmable Logic
Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor
More informationA FAST AND EFFICIENT HARDWARE TECHNIQUE FOR MEMORY ALLOCATION
A FAST AND EFFICIENT HARDWARE TECHNIQUE FOR MEMORY ALLOCATION Fethullah Karabiber 1 Ahmet Sertbaş 1 Hasan Cam 2 1 Computer Engineering Department Engineering Faculty, Istanbul University 34320, Avcilar,
More informationNvidia Jetson TX2 and its Software Toolset. João Fernandes 2017/2018
Nvidia Jetson TX2 and its Software Toolset João Fernandes 2017/2018 In this presentation Nvidia Jetson TX2: Hardware Nvidia Jetson TX2: Software Machine Learning: Neural Networks Convolutional Neural Networks
More informationDeep Learning: Transforming Engineering and Science The MathWorks, Inc.
Deep Learning: Transforming Engineering and Science 1 2015 The MathWorks, Inc. DEEP LEARNING: TRANSFORMING ENGINEERING AND SCIENCE A THE NEW RISE ERA OF OF GPU COMPUTING 3 NVIDIA A IS NEW THE WORLD S ERA
More informationHybrid Memory Platform
Hybrid Memory Platform Kenneth Wright, Sr. Driector Rambus / Emerging Solutions Division Join the Conversation #OpenPOWERSummit 1 Outline The problem / The opportunity Project goals Roadmap - Sub-projects/Tracks
More informationARM Multimedia IP: working together to drive down system power and bandwidth
ARM Multimedia IP: working together to drive down system power and bandwidth Speaker: Robert Kong ARM China FAE Author: Sean Ellis ARM Architect 1 Agenda System power overview Bandwidth, bandwidth, bandwidth!
More informationECE 448 Lecture 15. Overview of Embedded SoC Systems
ECE 448 Lecture 15 Overview of Embedded SoC Systems ECE 448 FPGA and ASIC Design with VHDL George Mason University Required Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 8, Overview of Embedded
More informationGroup Testing for Image Compression
Group Testing for Image Compression Edwin Hong and Richard Ladner. IEEE Transations on Image Processing. Aug. 2003 By Chih-Yu (Joey) Tang November 22, 2006 The Concept of Group Testing Identify Army recruits
More informationEXPLORING ON STEGANOGRAPHY FOR LOW BIT RATE WAVELET BASED CODER IN IMAGE RETRIEVAL SYSTEM
TENCON 2000 explore2 Page:1/6 11/08/00 EXPLORING ON STEGANOGRAPHY FOR LOW BIT RATE WAVELET BASED CODER IN IMAGE RETRIEVAL SYSTEM S. Areepongsa, N. Kaewkamnerd, Y. F. Syed, and K. R. Rao The University
More informationLecture #1: Introduction
Lecture #1: Introduction Kunle Olukotun Stanford EE183 January 8, 20023 What is EE183? EE183 is continuation of EE121 Digital Logic Design is a a minute to learn, a lifetime to master Programmable logic
More informationS2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
More informationHybrid Face Recognition and Classification System for Real Time Environment
Hybrid Face Recognition and Classification System for Real Time Environment Dr.Matheel E. Abdulmunem Department of Computer Science University of Technology, Baghdad, Iraq. Fatima B. Ibrahim Department
More informationHardware-Software Codesign. 1. Introduction
Hardware-Software Codesign 1. Introduction Lothar Thiele 1-1 Contents What is an Embedded System? Levels of Abstraction in Electronic System Design Typical Design Flow of Hardware-Software Systems 1-2
More informationCatapult: A Reconfigurable Fabric for Petaflop Computing in the Cloud
Catapult: A Reconfigurable Fabric for Petaflop Computing in the Cloud Doug Burger Director, Hardware, Devices, & Experiences MSR NExT November 15, 2015 The Cloud is a Growing Disruptor for HPC Moore s
More informationWireless Video Chat System
Wireless Video Chat System EECS 488 April 24, 2003 Tim O Leary Greg Ferreri State of the Art D-Link s i2eye videophone 30 fps Remote Control Caller ID Standalone (no PC required) i2eye Drawbacks Not wireless
More informationA Low Power 720p Motion Estimation Processor with 3D Stacked Memory
A Low Power 720p Motion Estimation Processor with 3D Stacked Memory Shuping Zhang, Jinjia Zhou, Dajiang Zhou and Satoshi Goto Graduate School of Information, Production and Systems, Waseda University 2-7
More informationReducing DRAM Latency at Low Cost by Exploiting Heterogeneity. Donghyuk Lee Carnegie Mellon University
Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity Donghyuk Lee Carnegie Mellon University Problem: High DRAM Latency processor stalls: waiting for data main memory high latency Major bottleneck
More informationThe Challenges of System Design. Raising Performance and Reducing Power Consumption
The Challenges of System Design Raising Performance and Reducing Power Consumption 1 Agenda The key challenges Visibility for software optimisation Efficiency for improved PPA 2 Product Challenge - Software
More informationReduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
More informationEmbedded Systems: Hardware Components (part I) Todor Stefanov
Embedded Systems: Hardware Components (part I) Todor Stefanov Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded System
More informationarxiv: v1 [cs.cv] 11 Feb 2018
arxiv:8.8v [cs.cv] Feb 8 - Partitioning of Deep Neural Networks with Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms ABSTRACT Jong Hwan Ko, Taesik Na, Mohammad Faisal Amir,
More informationEmbedded Real-Time Video Processing System on FPGA
Embedded Real-Time Video Processing System on FPGA Yahia Said 1, Taoufik Saidani 1, Fethi Smach 2, Mohamed Atri 1, and Hichem Snoussi 3 1 Laboratory of Electronics and Microelectronics (EμE), Faculty of
More informationESL design with the Agility Compiler for SystemC
ESL design with the Agility Compiler for SystemC SystemC behavioral design & synthesis Steve Chappell & Chris Sullivan Celoxica ESL design portfolio Complete ESL design environment Streaming Video Processing
More informationIntroduction. Definition. What is an embedded system? What are embedded systems? Challenges in embedded computing system design. Design methodologies.
Introduction What are embedded systems? Challenges in embedded computing system design. Design methodologies. What is an embedded system? Communication Avionics Automobile Consumer Electronics Office Equipment
More informationMulti-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture
The 51st Annual IEEE/ACM International Symposium on Microarchitecture Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture Byungchul Hong Yeonju Ro John Kim FuriosaAI Samsung
More informationSystem-on-Chip Architecture for Mobile Applications. Sabyasachi Dey
System-on-Chip Architecture for Mobile Applications Sabyasachi Dey Email: sabyasachi.dey@gmail.com Agenda What is Mobile Application Platform Challenges Key Architecture Focus Areas Conclusion Mobile Revolution
More informationNew STM32 F7 Series. World s 1 st to market, ARM Cortex -M7 based 32-bit MCU
New STM32 F7 Series World s 1 st to market, ARM Cortex -M7 based 32-bit MCU 7 Keys of STM32 F7 series 2 1 2 3 4 5 6 7 First. ST is first to sample a fully functional Cortex-M7 based 32-bit MCU : STM32
More informationAccelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs Ritchie Zhao 1, Weinan Song 2, Wentao Zhang 2, Tianwei Xing 3, Jeng-Hau Lin 4, Mani Srivastava 3, Rajesh Gupta 4, Zhiru
More informationUltra-low power wireless sensor networks: distributed signal processing and dynamic resources management
Ultra-low power wireless sensor networks: distributed signal processing and dynamic resources management Candidate: Carlo Caione Tutor: Prof. Luca Benini Compressive Sensing The issue of data gathering
More informationA New Configuration of Adaptive Arithmetic Model for Video Coding with 3D SPIHT
A New Configuration of Adaptive Arithmetic Model for Video Coding with 3D SPIHT Wai Chong Chia, Li-Minn Ang, and Kah Phooi Seng Abstract The 3D Set Partitioning In Hierarchical Trees (SPIHT) is a video
More informationFederal University of Pelotas UFPel Group of Architectures and Integrated Circuits Pelotas Brasil
Federal University of Pelotas UFPel Group of Architectures and Integrated Circuits Pelotas Brasil A VLSI Architecture for Reference Compression on High Definition Video Systems Guilherme Povala, Lívia
More informationMulti-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding
Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel Karlsruhe Institute
More informationDevelopment of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
Session 8D-2 Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi,
More informationCompression of RADARSAT Data with Block Adaptive Wavelets Abstract: 1. Introduction
Compression of RADARSAT Data with Block Adaptive Wavelets Ian Cumming and Jing Wang Department of Electrical and Computer Engineering The University of British Columbia 2356 Main Mall, Vancouver, BC, Canada
More informationMonolithic 3D IC Design for Deep Neural Networks
Monolithic 3D IC Design for Deep Neural Networks 1 with Application on Low-power Speech Recognition Kyungwook Chang 1, Deepak Kadetotad 2, Yu (Kevin) Cao 2, Jae-sun Seo 2, and Sung Kyu Lim 1 1 School of
More informationScalable and Modularized RTL Compilation of Convolutional Neural Networks onto FPGA
Scalable and Modularized RTL Compilation of Convolutional Neural Networks onto FPGA Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma Vrudhula School of Electrical, Computer and Energy Engineering School
More informationA Study of Image Compression Based Transmission Algorithm Using SPIHT for Low Bit Rate Application
Buletin Teknik Elektro dan Informatika (Bulletin of Electrical Engineering and Informatics) Vol. 2, No. 2, June 213, pp. 117~122 ISSN: 289-3191 117 A Study of Image Compression Based Transmission Algorithm
More informationUpcoming Video Standards. Madhukar Budagavi, Ph.D. DSPS R&D Center, Dallas Texas Instruments Inc.
Upcoming Video Standards Madhukar Budagavi, Ph.D. DSPS R&D Center, Dallas Texas Instruments Inc. Outline Brief history of Video Coding standards Scalable Video Coding (SVC) standard Multiview Video Coding
More informationFast Decision of Block size, Prediction Mode and Intra Block for H.264 Intra Prediction EE Gaurav Hansda
Fast Decision of Block size, Prediction Mode and Intra Block for H.264 Intra Prediction EE 5359 Gaurav Hansda 1000721849 gaurav.hansda@mavs.uta.edu Outline Introduction to H.264 Current algorithms for
More informationLow-Power Video Codec Design
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn : 2278-800X, www.ijerd.com Volume 5, Issue 8 (January 2013), PP. 81-85 Low-Power Video Codec Design R.Kamalakkannan
More informationA Hardware-Friendly Bilateral Solver for Real-Time Virtual-Reality Video
A Hardware-Friendly Bilateral Solver for Real-Time Virtual-Reality Video Amrita Mazumdar Armin Alaghi Jonathan T. Barron David Gallup Luis Ceze Mark Oskin Steven M. Seitz University of Washington Google
More information! Memory Overview. ! ROM Memories. ! RAM Memory " SRAM " DRAM. ! This is done because we can build. " large, slow memories OR
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 2: April 5, 26 Memory Overview, Memory Core Cells Lecture Outline! Memory Overview! ROM Memories! RAM Memory " SRAM " DRAM 2 Memory Overview
More informationImplementing Deep Learning for Video Analytics on Tegra X1.
Implementing Deep Learning for Video Analytics on Tegra X1 research@hertasecurity.com Index Who we are, what we do Video analytics pipeline Video decoding Facial detection and preprocessing DNN: learning
More informationDeep Learning Accelerators
Deep Learning Accelerators Abhishek Srivastava (as29) Samarth Kulshreshtha (samarth5) University of Illinois, Urbana-Champaign Submitted as a requirement for CS 433 graduate student project Outline Introduction
More informationAddressing the Memory Wall
Lecture 26: Addressing the Memory Wall Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2015 Tunes Cage the Elephant Back Against the Wall (Cage the Elephant) This song is for the
More informationXuena Bao, Dajiang Zhou, Peilin Liu, and Satoshi Goto, Fellow, IEEE
An Advanced Hierarchical Motion Estimation Scheme with Lossless Frame Recompression and Early Level Termination for Beyond High Definition Video Coding Xuena Bao, Dajiang Zhou, Peilin Liu, and Satoshi
More informationThe Path to Embedded Vision & AI using a Low Power Vision DSP. Yair Siegel, Director of Segment Marketing Hotchips August 2016
The Path to Embedded Vision & AI using a Low Power Vision DSP Yair Siegel, Director of Segment Marketing Hotchips August 2016 Presentation Outline Introduction The Need for Embedded Vision & AI Vision
More informationMulti-Mode Embedded Compression Codec Engine for Power-Aware Video Coding System
Multi-Mode Embedded Compression Codec Engine for Power-Aware Video Coding System Chih-Chi Cheng, Po-Chih Tseng, Chao-Tsung Huang, and Liang-Gee Chen DSP/IC Design Lab, Graduate Institute of Electronics
More informationIntroduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.
More informationEN2911X: Reconfigurable Computing Lecture 01: Introduction
EN2911X: Reconfigurable Computing Lecture 01: Introduction Prof. Sherief Reda Division of Engineering, Brown University Fall 2009 Methods for executing computations Hardware (Application Specific Integrated
More information05 - Microarchitecture, RF and ALU
September 15, 2015 Microarchitecture Design Step 1: Partition each assembly instruction into microoperations, allocate each microoperation into corresponding hardware modules. Step 2: Collect all microoperations
More information