A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias. David Kidd August 26, 2013
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1 A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias David Kidd August 26, HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
2 Agenda DDC transistor and PowerShrink platform overview ARM Cortex-M0 implementation and results Application of DDC technology to HKMG nodes 2 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
3 Deeply Depleted Channel (DDC) Transistor 1 Undoped/lightly doped region Improved matching (low RDF) Higher mobility ( I D,lin ) Higher analog gain ( g m ) Gate Gate 2 V T setting offset region Multiple V T on chip Source 1 2 Drain 3 Screening region Superior scalability Improved drive current ( I eff DIBL) Higher analog gain ( R out ) Strong body coefficient (corner pull-in) One example, not drawn to scale 3 3 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
4 PLVt NLVt Corner Pull-in with Body Bias No Body Bias With Body Bias Typical Fast Corners pull in to typical I O Slow I O I ON I ON Fast I O Typical I O Slow I ON 4 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved. I ON
5 Leakage Power Leakage Power Leakage Power DDC PowerShrink Platform: Save Active and Leakage Power Using Body Bias log DDC performance is superior at matched VDD DDC 1.2V POR Save active power Lower DDC VDD 1.2V log DDC performance degrades due to lowered VDD POR DDC 1.2V 0.9V Same VDD, similar V T,sat Delay log Body bias reduces leakage power Leakage power saving POR DDC 1.2V Lowered VDD, similar V T,sat Delay Match delay Lower DDC V T,sat 0.9V Matched delay V T shifted and corners pulled in by body bias Lowered VDD, lowered V T,sat Delay 5 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
6 NMOS Bias (mv) NMOS Bias (mv) ARM Cortex-M0 CPU Bias Targeting PMOS Bias (mv) Measured ARM Cortex-M0 Speed and power response to bias 375MHz 350MHz TARGET 325MHz Speed PMOS Bias (mv) Increasing Leakage Target 350MHz Many bias voltages achieve the target frequency but power is not optimal at all biases Too Slow Leakage (delta to optimal) 6 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
7 Digital Readout Process Monitor Bias Targeting (55nm Measured) Process Monitor Corner Detection PMOS target NMOS target PMOS measured NMOS measured Process Monitor independently measures NMOS and PMOS corners Digital readout correlates to corner Bias voltage is calculated from readout Bias Target from Monitor NMOS Bias (V) Bias target calculated from monitor readout PMOS Bias (V) 7 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
8 Relative Speed Relative Power Process Monitor Bias Targeting (55nm Measured) Performance Correction Leakage Correction 170% 160% 150% 140% 130% 120% 110% 100% Zero Bias Target Bias Target 1000% 800% 600% 400% 200% 0% Zero Bias Target Bias Performance is corrected to 13% faster than target Fast corner leakage is corrected to the same point as typical 8 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
9 Power (mw) PowerShrink Platform: ARM Cortex-M0 CPU 50% power vs baseline at (leakage and dynamic) Matched performance at Baseline Baseline DDC DDC 65nm CORTEX M0 1.2V 0.9 V Corner Variation 85 C 50% DDC corner variation pull-in with bias Frequency (MHz) 9 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
10 Power (mw) Tunable Power / Performance Matched performance at 50% power 0.9V +35% performance at matched power 1.1V +55% performance at matched voltage 1.2V V Baseline DDC 0.9V 100% power 1.2V Matched Performance 1.1V 1.0V 50% power Frequency (MHz) 1.2V 55% Performance Increase 35% Performance Increase at Matched Power 65nm CORTEX M0 85 C Performance: corner Power: corner 10 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
11 ARM Cortex-M0 Body Bias Network Implementation Minimal routing resources used for bias network Route in columns Double-space bias wires for reliability 1 PMOS wire, 1 NMOS wire Vertical Track Usage per Column Layer Available Tracks Bias Tracks M M Total (0.7%) Bias Columns 11 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
12 Yield (%) Lower SRAM V DD-min Enables Low-V DD Operation V DD-min of 8Mb SRAM lowered by 150mV at 125 C Production 55nm SRAM data Target Yield Voltage (V) 55nm silicon 12 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
13 Lower SRAM Retention Power 50% less leakage in Standby and Retention modes at nominal V BS More than 5X less leakage in Retention mode with V BS = -0.6V Baseline Retention Power 53% lower 87% lower DDC Retention Power 65nm silicon 13 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
14 DDC Technology in Silicon Gate and HKMG Silicon-Gate DDC PowerShrink Memory DRAM Other DDC PowerShrink 90nm, 65nm, 55nm, 40nm Imaging WiFi CPU RF Deeply Depleted Channel (DDC) Technology Metal-Gate DDC PowerShrink 28nm, 20nm CPUs + GPUs SoC Networking FPGA DDC DesignBoost 28nm, 20nm CPUs + GPUs Networking Mixed Signal Display Drivers GPS SoC FPGA Proven, Legacy Technology Nodes Advanced 14 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
15 DDC Technology Modular Implementation 15 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
16 Leakage Power Leakage Power DDC DesignBoost: Target Leakage Power Savings log DDC performance is superior at matched VDD log Recover Leakage by Trading off Performance DDC POR 0.9V Save Leakage Power Increase DDC V T,sat POR DDC Leakage power 0.9V 0.9V saving Improved performance 0.9V Matched performance Same VDD, similar V T,sat Delay Same VDD, higher V T,sat Delay DDC DesignBoost 16 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
17 Normalized Leakage DDC DesignBoost Motivation 100% 90% 80% 70% 60% 50% HVT SVT LVT SLVT C LVT SLVT 40% 30% 20% 10% HVT SVT 0% Low Performance Leakage Low Performance Usage High Performance Leakage High Performance Usage Normalized Speed LVT and SLVT devices contribute a large portion of the leakage power at advanced nodes Leakage power reduction is a key value adder for high performance designs 17 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
18 Relative Power Baseline DDC Baseline DDC DDC DesignBoost Power Savings in HKMG LVT Devices Active Power Leakage Power Small Dynamic Savings Due to better device capacitance Big Leakage Savings Speed Power DDC DesignBoost Target matched performance to reduce Ioff 18 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
19 Power Savings 0.9V DesignBoost 0.9V DesignBoost + Body Bias 0.8V PowerShrink HKMG Power Analysis 0.9V DesignBoost 0.9V with Body Bias 0.8V PowerShrink HKMG design 10% activity factor DDC DesignBoost No design change Body Bias improves power savings PowerShrink platfrom For active power dominated circuits Active Dominated Leakage Dominated 100% SVT 100% LVT All transistors are DDC transistors 125C Speed Power 19 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
20 Summary ARM Cortex-M0 validated at 65nm Matched performance at 50% power +35% performance at matched power +55% performance at matched voltage SRAM validated at 65nm and 55nm 150mV Vmin reduction in production 55nm SRAM Less than 50% static power in standby and retention DDC technology demonstrated at advanced HKMG nodes Lower static power at matched performance Lower active power with body bias 20 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
21 21 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
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