DP-8020 Hardware User Guide v1.10. DP-8020 Hardware User Guide V1.10

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1 DP-8020 Hardware User Guide V1.10 DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd

2 Copyright 2018 DeePhi Tech, Inc. A rights reserved. No part of this pubication may be reproduced or transmitted in any form or by any means without the prior written permission of DeePhi Tech, Inc. For more information, pease refer to the officia web site: DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd

3 Tabe of Contents 1 DP-8020 Introduction Board Setup and Configuration Board Component Location Defaut Switch and Jumper Settings Hardware Design Introduction ZU2 MPSOC Processor Introduction ZU2EG IO Banks ZU2EG IO Pin Assignment DDR4 Chips Fash Cock Reset I2C Bus USB Gigabit Ethernet Dispay Port PCIe Micro-SD Debugging UART CAN Bus JTAG GPIO Fan V Power Suppy Reference DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd

4 History Ver. Date Description October 2018 Initia Reease DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 1

1 DP-8020 Introduction DP-8020 is a standard haf-height & haf-ength PCIe board based on Xiinx XCZU2EG- 2SFVA625I MPSOC (mutiprocessor system-on-chip). DP-8020 with 2GB DDR4 and 8GB emmc Fash.

5 1 DP-8020 Introduction DP-8020 is a standard haf-height & haf-ength PCIe board based on Xiinx XCZU2EG- 2SFVA625I MPSOC (mutiprocessor system-on-chip). DP-8020 with 2GB DDR4 and 8GB emmc Fash. Externa interfaces are PCIe, USB 3.0, Gigabit Ethernet, Dispay Port, Micro SD card socket, Debug UART, JTAG, CAN, GPIO etc. a. DP-8020 can be used as PCIe daughter card or work independenty powered by DC-12V power adapter. Bock diagram of DP-8020 board is shown in Figure 1-1. USB Ethernet LED Dispay_Port _Aux(eMIO) PCIe x2 USB3.0 Dispay Port PL_GPIO DDR4 32-bit PS_REF_CLK JTAG,PS_MODE PS_POR HW_Version PL_GPIO SDIO,SPI1 UART0&1,I2C0 PS_GPIO 8GB emmc CAN,PS_GPIO Figure 1-1: DP-8020 Bock Diagram DP-8020 features are as foows: XCZU2EG-2SFVA625I MPSOC 2GB DDR4 (32bit) 8GB emmc Fash, support emmc boot Support SD card boot Support JTAG boot USB 3.0 PCIe 2.0 ( x2 ane) Dispay Port Gigabit Ethernet USB-UART Seria port CAN DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 2

6 GPIO LED DC-12V Power Suppy Board Size: 68.90mm x mm Work Temperature: 0 ~45 DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 3

2 Board Setup and Configuration 2.1 Board Component Location Figure 2-1 shows component ocations of DP-8020 board. Each numbered component shown in Figure 2-1 is keyed to Tabe 2-1.

7 2 Board Setup and Configuration 2.1 Board Component Location Figure 2-1 shows component ocations of DP-8020 board. Each numbered component shown in Figure 2-1 is keyed to Tabe 2-1. Figure 2-1: DP-8020 Board Components Tabe 2-1: DP-8020 Board Components and Functions Caout Ref. Des. Component/Function 1 U1 XCZU2EG-2SFVA625I 2 U5, U6 MT40A512M16JY-083E:B 2 pcs 8Gb DDR4, totay 2GB 3 U4 MTFC8GAKAJCN-1M WT, 8GB emmc Fash 4 J1 Micro SD card socket 5 J11 USB UART Interface (Micro-B USB connector, and CP2103 is the bridge IC) 6 J12 CAN BUS header 7 J14 JTAG header DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 4

8 Tabe 2-1: DP-8020 Board Components and Functions (Cont d) Caout Ref. Des. Component/Function 8 J13 Genera GPIO header 9 J15 DC-12V power connector 10 SW1 Switch(MPSOC boot mode seection) 11 J18 12V power header for Fan 12 J10 PCIe x4 Connector(DP-8020 supports x2 mode ony) 13 J6 USB3.0 Type-A socket 14 D8 Work status indicator LED(Red LED for 3.3V votage,green LED for board status) 15 J3 RJ45 socket 16 K1 Manua Reset button 17 J9 Dispay Port socket 18 U9 KSZ9031RNXIC,Gigabit Ethernet PHY 19 U10 USB3320C-EZK,USB PHY 20 J8 Power suppy header for USB Host mode 21 J17 USB port mode seect header. 22 D3 Error indicator LED for USB-5V power suppy 23 D1 LED connected with PS_MIO34 24 D5 Indicator LED for Dispay Port power suppy 25 D7 Indicator LED for DC-12 power input DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 5

9 2.2 Defaut Switch and Jumper Settings Pease refer to Tabe 2-2 for switch and jumper defaut settings. Tabe 2-2: Switch and Jumper Defaut Settings SW1 J8 Function FPGA boot Mode seection ON = pu down = 0 OFF = pu up = 1 SW1-4: Not used SW1-3: PS_MODE2 SW1-2: PS_MODE1 SW1-1: PS_MODE0 MODE [2:0] = 000=JTAG 101=SD1 110=eMMC USB power suppy Enabe/Disabe 1-2 Connection: Enabe 5V power suppy for USB device (Host mode) 1-2 Disconnection: No power suppy from USB Port (Device mode) Defaut Configuration MODE [2:0] = 110 (boot from emmc) SW1-3: OFF SW1-2: OFF SW1-1: ON Note:PS_MODE3 is fixed as 0 Host mode 1-2 Connection J17 USB port work mode configuration 1-2 Connection: Host mode Host mode 1-2 Connection 1-2 Disconnection:Device mode DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 6

3 Hardware Design Introduction This chapter introduces detaied hardware design on DP-8020. 3.1

10 3 Hardware Design Introduction This chapter introduces detaied hardware design on DP ZU2 MPSOC Processor Introduction Processor is XCZU2EG-2SFVA625I, which combines a powerfu processing system (PS) and user-programmabe ogic (PL) into the same device. Detaied resources are as foows: For detaied introduction of Xiinx Zynq UtraScae+ MPSoC devices, pease refer to: 1) Zynq UtraScae+ MPSoC Data Sheet: Overview (DS891) [Ref 1] 2) Zynq UtraScae+ MPSoC Technica Reference Manua (UG1085) [Ref 2] DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 7

11 3.1.2 ZU2EG IO Banks The periphera interfaces and Bank IO votage of ZU2EG are isted in Tabe 3-1 Tabe 3-1: The Periphera Interfaces and Bank IO Votage of ZU2EG Bank No. Periphera interface Votage PS Bank 500 emmc, CAN, PS_GPIO 1.8V PS Bank 501 SDIO, SPI1, UART0&1, I2C0, PS_GPIO 3.3V PS Bank 502 USB2.0(ULPI), Ethernet(RGMII) 3.3V PS PS Bank 503 PS_REF_CLK, JTAG, PS_MODE, PS_POR 1.2V PS Bank 504 DDR4 (32-bit) 3.3V PS Bank 505 PCIe x2(gtr0&1), USB3.0(GTR2), Dispay Port(GTR3) PL HD Bank 26 Dispay_Port _Aux(eMIO), LED 3.3V PL PL HP Bank V PL HP Bank 65 HW_Version, PL_GPIO 1.8V PL HP Bank 66 PL_GPIO 1.8V DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 8

12 3.1.3 ZU2EG IO Pin Assignment For ZU2EG IO Pin assignment, pease refer to Tabe 3-2 (PS_MIO) and Tabe 3-3 (PL_IO). Tabe 3-2: XCZU2EG PS_MIO Pin Aocation PS_MIO Definition PS_MIO Definition PS_MIO Definition MIO0 NC MIO26 FPGA_SELFRST_N MIO52 USB0 TX CLK. MIO1 NC MIO27 PS_GPIO5 MIO53 USB0 DIR MIO2 NC MIO28 PS_GPIO6 MIO54 USB0 Data 2 MIO3 NC MIO29 PS_GPIO7 MIO55 USB0 NXT MIO4 PS_GPIO1 MIO30 PS_GPIO8 MIO56 USB0 Data 0 MIO5 PS_GPIO2 MIO31 KSZ9031_RST_N MIO57 USB0 Data 1 MIO6 NC MIO32 NC MIO58 USB0 STP MIO7 PS_GPIO3 MIO33 PCIE RESET_N MIO59 USB0 Data 3 MIO8 PS_GPIO4 MIO34 PS_Debug_LED MIO60 USB0 Data 4 MIO9 NC MIO35 NC MIO61 USB0 Data 5 MIO10 CAN0 RX MIO36 NC MIO62 USB0 Data 6 MIO11 CAN0 TX MIO37 NC MIO63 USB0 Data 7 MIO12 NC MIO38 UART0 RX MIO64 GEM3 TX CCLK MIO13 MIO14 MIO15 Data 0 Data 1 Data 2 MIO39 UART0 TX MIO65 GEM3 TX Data 0 MIO40 UART1 TX MIO66 GEM3 TX Data 1 MIO41 UART1 RX MIO67 GEM3 TX Data 2 DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 9

13 Tabe 3-2: XCZU2EG PS_MIO Pin aocation (Cont d) PS_MIO Definition PS_MIO Definition PS_MIO Definition MIO16 MIO17 MIO18 MIO19 MIO20 MIO21 MIO22 MIO23 Data 3 Data 4 Data 5 Data 6 Data 7 CMD CLK RESET MIO42 IIC0 SCL MIO68 GEM3 TX Data 3 MIO43 IIC0 SDA MIO69 GEM3 TX CTL MIO44 USB3320_RST_N MIO70 GEM3 RX CCLK MIO45 SD CD MIO71 GEM3 RX Data 0 MIO46 SD Data 0 MIO72 GEM3 RX Data 1 MIO47 SD Data 1 MIO73 GEM3 RX Data 2 MIO48 SD Data 2 MIO74 GEM3 RX Data 3 MIO49 SD Data 3 MIO75 GEM3 RX CTL MIO24 NC MIO50 SD CMD MIO76 GEM3 MDC MIO25 NC MIO51 SD CLK MIO77 GEM3 MDIO Note: NC means this pin is not used on DP DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 10

14 Tabe 3-3: XCZU2EG PL_ IO Aocation Tabe PL Bank PL_IO Definition Bank26 E12 DP_AUX_OUT Bank26 D12 DP_HPD Bank26 B12 DP_OE Bank26 A12 DP_AUX_IN Bank26 B11 Green LED indicator for D8, ighting when D8 is ow Bank26 C11 PL_GPIO6 Bank65 R2 HW_VERSION1 Bank65 R1 HW_VERSION2 Bank65 U1 HW_VERSION3 Bank65 V1 HW_VERSION4 Bank65 K1 PL_GPIO9 Bank65 J1 PL_GPIO10 Bank66 H1 PL_GPIO7 Bank66 E1 PL_GPIO8 DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 11

15 3.2 DDR4 Chips DP-8020 with two DDR4 chips (MT40A512M16JY-083E:B 8Gb,DDR4-2400), totay 2GB memory (512M x 32bits). As DDR controer of XCZU2EG-2SFVA625I ony supports DDR4-2133Mbps, speed of DDR4 on DP-8020 is up to 2133Mbps. Two DDR4 chips are connected with XCZU2EG PS Bank504, whie no DDR4 chip connected on XCZU2EG PL side. 3.3 Fash DP-8020 board has an 8GB emmc Fash as MTFC8GAKAJCN-1M WT for fiesystem and user data storage. emmc is connected with XCZU2EG PS Bank501, and pease refer to Chapter for pin aocation information. 3.4 Cock Main cock for XCZU2EG s is MHz and is provided by crysta osciator. PCIe reference cock(ps_mgtrefclk0)is provided through PCIe goden finger interface. Reference cock for USB3.0 and DP dispay port(ps_mgtrefclk2, PS_MGTREFCLK3)is provided by difference cock chip Si5340A. Cock system design is as Figure 3-1. Osciator 33M Hz PS_RefCLK PS_RefCLK ZU2-SFVA625I Osciator 48M Hz Si5340A-D- GM USB3.0_REFCLK-26M DP_REFCLK-27M PS_GTR2 PS_GTR3 Figure 3-1: Cock System 3.5 Reset Reset of XCZU2EG is controed by TPS3808. During power-up phase, TPS3808 monitors the votage of D1V2. When D1V2 votage is norma, TPS3808 wi reease the reset signa with a time deay. DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 12

16 After power up, reset source of XCZU2EG is from manua reset (button K1) or PCIe reset(pcie_reset_n). Pease noted that PCIe reset signa is output through PS_MIO26 after input to XCZU2EG. Pease refer to Figure 3-2 for reset design on DP PS_MIO26 PS_MIO33 PCIE_RESET_N D1V2 Sense ZU2-SFVA625I FPGA_SELFRST_N Manua Reset & TPS3808 MR_N PS_POR_B Figure 3-2: Reset Design 3.6 I2C Bus On DP-8020, I2C0 bus is aocated to PS_MIO42 and 43, and there are two I2C devices: 1) INA226AIDGS is for measuring the power consumption of DC-12V input. I2C address is 0x ) Si5340A(cock chip) is for generating the PS-GTR reference cock for USB3.0 and Dispay Port. I2C address is 0x USB USB port on DP-8020 uses XCZU2EG PS-GTR2, with Type-A socket. USB2.0 PHY chip is USB3320, which is connected to XCZU2EG PS_MIO52~63 by ULPI bus (pease refer to Chapter 3.1.3). PS_MIO ULPI USB3320 USB3.0 Type-A Connector PS_GTR2 Figure 3-3: USB Design USB port supports Host mode and Device mode, which is configured by J8 and J17. DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 13

17 The defaut mode is Host mode(pease refer to Chapter 2.2). In host mode, USB device is powered by power chip MIC Gigabit Ethernet XCZU2EG PS side contains Gigabit Ethernet MAC, with PHY chip KSZ9031 (10/100/1000Mbps), DP-8020 provide one Gigabit Ethernet Port. KSZ9031 is connected to PS_MIO64~75 (pease refer to Chapter 3.1.3), and coud be controed by MDIO(PS_MIO76&77). The address of KSZ9031 is 5'b Dispay Port XCZU2EG provides a VESA DispayPort 1.2 source-ony controer. DP-8020 uses PS- GTR3 as the Dispay Port main ink, data rate can be 1.62Gb/s,2.7Gb/s or 5.4Gb/s. Dispay port auxiiary signa is output from EMIO (IO pins of PL Bank26, pease refer to Chapter 3.1.3), and transferred to LVDS signa DPAUX by FIN1019. Both Main ink and DPAUX are connected to Dispay Port socket J PCIe DP-8020 board impements the PCIe 2.0 x2 Lane through PS-GRT0&1. PCIe interface is physicay PCIe x4 (ony use Lane0&1 on DP-8020). PS_MIO33 is used as PCIE_RESET_N input IO pin Micro-SD DP-8020 has one Micro-SD card socket, so SD card can be used as fiesystem and user data storage. When Mode[2:0] (SW1) is set as 101, XCZU2EG wi boot from SD card. Micro-SD card socket is connected to XCZU2EG PS Bank 501. For more detais pease refer to Chapter Debugging UART0 UART0 (PS_MIO38&39)on XCZU2EG PS side is used for system debugging. It is transferred to USB interface by CP2103 and connected to USB Micro-B connector J11. DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 14

18 UART0 s baud rate is configured at CAN Bus The CAN Bus is aocated to PS_MIO10&11 (1.8V) of PS bank 500. It is connected to CAN bus transceiver SN65HVD232 through TXS0104E (1.8Vßà3.3V). Physica interface is J12. Tabe 3-4:Pin Definition of CAN Bus Connector J12 Pin Definition J12 Pin Definition 1 GND 2 GND 3 CAN0_CANH_TERM 4 CAN0_CANH 5 CAN0_CANL 6 CAN0_CANL_TERM 7 CAN0_CANL 8 CAN0_CANH Note: CAN0_CANH_TERM and CAN0_CANL_TERM are connected to 60ohm terminating resistor JTAG DP-8020 has the JTAG connector J14. XCZU2EG coud boot from JTAG by setting the Mode[2:0] as 000. DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 15

19 Tabe 3-5: Pin Definition of JTAG Connector J14 Pin Definition J14 Pin Definition 1 GND 2 3.3V 3 GND 4 PS_JTAG_TMS 5 GND 6 PS_JTAG_TCK 7 GND 8 PS_JTAG_TDO 9 GND 10 PS_JTAG_TDI 3.15 GPIO DP-8020 has 8 PS GPIO, one UART and 5 PL GPIO, which can a be accessed through connector J13. Aso, DC-12V power pin for externa power suppy is provided through J13. Tabe 3-6: GPIO Pin Definition J13 Pin Definition J13 Pin Definition 3 PS_GPIO5 22 PL_GPIO6 4 PS_GPIO7 23 PL_GPIO7 7 PS_GPIO6 24 PL_GPIO8 8 PS_GPIO8 25 PL_GPIO9 11 UART1 TXD 26 PL_GPIO10 12 UART1 RXD 29,30 12V 15 PS_GPIO1 16 PS_GPIO2 17 PS_GPIO3 18 PS_GPIO4 1,2,5,6,9,10,13,1 4,19,20,27,28,31,32 GND DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 16

20 3.16 Fan DC-12V Fan connection schematic is shown as Figure3-4. The Fan wi start to work when DP-8020 is power-up. Figure 3-4: DP V Fan Header V Power Suppy Two power suppy modes for DP-8020 are as foows: 1) As a deveopment board, it is powered through socket J15. DC-12V power adapter is used. 2) As a PCIe daughter card, it is powered through PCIe connector. Power consumption of DP-8020 coud be measured by current detection chip INA226AIDGS, which can be accessed through I2C bus. Reference 1. Zynq UtraScae+ MPSoC Data Sheet: Overview (DS891) 2. Zynq UtraScae+ MPSoC Technica Reference Manua (UG1085 DeePhi Proprietary Copyright Deephi Technoogies Co., Ltd 17

DP-8020 Hardware User Guide. UG1328 (v 1.20) December 6, 2018

DP-8020 Hardware User Guide. UG1328 (v 1.20) December 6, 2018 DP-8020 Hardware User Guide Revision History The following table shows the revision history for this document. Section General updates Revision Summary 12/06/2018 Version 1.0 Initial Xilinx release. DP-8020