CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory

CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory

Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits Before used in a circuit, it must be programmed SPLD (Simple Programmable Logic Device) CPLD (Complex Programmable Logic Device) FPGA (Field-Programmable Gate Array) SPLD CPLD FPGA

Simple PLD (SPLD) 3/32 Programmable Array Logic (PAL) Programmable Logic Array (PLA)

Complex PLD (CPLD) 4/32 Multiple PAL-like blocks on a single chip with programmable interconnect between blocks

Field-Programmable Gate Array (FPGA) 5/32 An array of programmable basic logic cells surrounded by programmable interconnect Xilinx XC4000 Configurable Logic Block (CLB).

Hardware Description Lang. (HDL) 6/32 Hardware Description Language (HDL) A software programming language used to model a piece of hardware Verilog-HDL, VHDL, SystemC, ABEL VHDL(VHSIC HDL) 1980 USA Department of Defence 1987 IEEE Standard 1076 Verilog HDL 1981 Gateway Design Automation 1995 IEEE Standard 1364

VHDL vs. Verilog 7/32 On the surface, not much Both can be used for designing ASICs and simulating systems Both are IEEE standards and are supported by all the major EDA vendors VHDL requires longer to learn and is not so amenable to quick-and-dirty dirty coding Many engineers will one day be bi-lingual in both HDLs

Introduction to VHDL 8/32 Designed to describe the behavior of digital systems Used as an input to commercial synthesis tools (only subsets of VHDL are synthesizable) VHDL is concurrent HDL which provides a wide range of levels of abstraction Architectural, Algorithmic, RTL, Gate, Switch VHDL has hierarchical design units

VHDL Structure 9/32 Circuit module Entity declaration + architecture body Circuit Module Ports Entity Declaration Architecture (Body) Sequential, Combinational Subprograms An entity is a simple declaration of a module s inputs and outputs. An architecture is a detailed description of module s internal structure or behavior.

Syntax of a VHDL entity declaration 10/32 entity example1 is port t( x1, x2, x3 : in std_logic ; --input signals in1 : in integer ; val1 : out std_logic ; -- output signals Signal Name val2 : out std_logic_vector(3 down to 0) ; end example1 ; Mode Type architecture sample1 of example1 is begin -- hello world ; end sample1 ; Entity-name User-defined identifier to name the entity Signal-names User-defined identifiers to name external-interface signal

Syntax of a VHDL entity declaration 11/32 Mode : specifying the signal direction In : the signal is an input to the entity. Out : the signal is an output of the entity. Inout: the signal can be read as an input or an output of the entity. This mode is typically used for three-state input/output pins. Buffer: the signal is an output of the entity, and its value can also be read and written inside the entity s architecture. In or Inout Out or Inout Upper Module In Lower Module Inout Inout Out Buffer Buffer

Syntax of a VHDL entity declaration 12/32 Signal types library IEEE ; use IEEE.std_logic_1164.all ; std_logic(bit) : U(Uninitialized), X(Forcing Unknown), 0(Forcing 0), 1(Forcing 1), Z(High Impedance), W(Weak Unknown), L(Weak 0), H(Weak 1), _(Don't Care) std_logic_vector(bit vector) for 8bit data type : std_logic_vector(7 downto 0) integer, real, character, boolean, etc.

Predefined Operators 13/32 Integer Operators: + addition - Subtraction * Multiplication / division mod modulo division rem modulo remainder Abs absolute value ** exponentiation Boolean Operators: and AND or OR nand NAND nor NOR xor exclusive OR xnor exclusive nor not complementation & concatenation

Sequential Statement 14/32 [LABEL:] if expr then {sequential_statement} [{elsif expr then {sequential_statement}}] [else {sequential_statement}] statement}] end if [LABEL]; [LABEL:] [while expr] loop {sequential_statement} end loop [LABEL]; [LABEL:] for ID in range loop {sequential_statement} statement} end loop [LABEL]; [LABEL:]] case expr is {when choice [{ choice}] => {sequential_statement}} end case [LABEL];

Process Statement 15/32 Logic circuit description in architecture body process sequential statement sequential statement concurrent statement concurrent statement Consists of concurrent statement and sequential statement Process contains several sequential statement Process itself is a sort of concurrent statement Process have three different state : suspended, active, running

Process Statement 16/32 What s the difference? architecture con of drv is begin A <= B; A <= C; end con; architecture seq of drv is begin Process(B, C) begin A <= B A<=C end process; end con2; Multiple l driver Several signal assignment to a single signal driver Signal driver A source which determines a value of each signal A signal is updated by the driver at every source update

Delta Delays (1/2) 17/32 Delta time is the time between two sequential events. The time to take from assigning g a value till updated The following VHDL code makes infinite delta delay and generates a synthesis error architecture con of some is begin A_Sig <= B_Sig ; B_Sig <= A_Sig ; end con;

Delta Delays (2/2) 18/32 Delta delays are used to order events.

Architecture Style (1/4) 19/32 Behavioral Style Describes a system in terms of what it does(or how it behaves)] IF, CASE, FOR, mainly within Process statement architecture BEHAVE of COMPARE is begin process (A, B) begin if (A = B) then C <= '1' ; else C <= '0' ; end if ; end process ; end BEHAVE ; architecture BEHAVE of MUX41 is begin case sel is when "00" => Z <= i0 ; when "01" => Z <= i1 ; when "10" => Z <= i2 ; when "11" => Z <= i3 ; end case ; end BEHAVE ;

Architecture Style (2/4) 20/32 Dataflow Style Specifies the relationship between the input and output signals AND, OR, NOT, XOR, etc. architecture of DATAFLOW of COMPARE is begin C<=not(Axor B) ; D <= A and not B ; end DATAFLOW ;

Architecture Style (3/4) 21/32 Structural Style Describes a system as interconnection of predefined components, hierarchical design consists of modules and interconnections ti Component, Port Map architecture STRUCTURE of COMPARE is signal I : BIT ; component XOR2 port (X, Y: in BIT; Z: out BIT) ; end component ; component INV port (X: in BIT; Z: out BIT) ; end component ; begin U0: XOR2 port map (A, B, I) ; U1: INV port map (I, C) ; end STRUCTURE ;

Architecture Style (4/4) 22/32 Example of Structural Style U1 I3 architecture structure of MUX41 is I2 component MUX21 port (D1, D0, S : in std_logic; Y : out std_logic); I1 end component; I0 signal A, B : std_logic; U0 begin U0 :MUX21portmap (D0 => I0, D1 => I1, S=>sel(0), Y=>A); U1 : MUX21 port map (D0 => I2, D1 => I3, S=>sel(0), Y=>B); U2 : MUX21 port map (D0 => A, D1=>B, S=>sel(1), Y=>Z); end structure; D1 Y D0 D1 Y D0 S sel(0) B D1 D0 A sel(1) U2 Y S Z

VHDL Source Code: Latch 23/32 VHDL Code for Latch Library IEEE; Use IEEE.std_logic_1164.all; Entity Latch is Port(LE, Din : in std_logic; Dout :outstd std_logic); End Latch; Architecture Latch_arch of Latch is Begin Process (Din, LE) Begin If (LE= 1 ) then Dout <= Din; End if; End process; End Latch_arch;

VHDL Source Code : D-Flip Flop 24/32 D-flip flop triggered by rising edge library IEEE; use IEEE.std_logic_1164.all; entity d-ff is port(clk, d: in std_logic; q : out std_logic); end d-ff; architecture d-ff_arch of d-ff is begin process(clk) Rising_edge(clk) begin if(clk'event and clk = '1') then q <= d; end if; end if end process; end d-ff_arch

VHDL Source Code : Register 25/32 8-bit register Library IEEE; use IEEE.std_logic_1164.all; entity Reg is port(clk : in std_logic; rst : in std_logic; ld : in std_logic; d : in std_logic_vector(7 t downto 0); q : out std_logic_vector(7 downto 0)); end Reg; architecture Reg_arch of Reg is begin process(clk, rst) begin if(rst = '1') then q <= (others => '0'); elsif(clk'event and clk ='1') then if(ld = '1') then q <= d; end if; end if; end process; end Reg_arch;

Typical Design Flow 26/32 HDL design : behavioral or structural description of design RTL Simulation verifies logic model & data flow. The simulation is typically performed to confirm that the code is functioning as intended. At this step, no timing information is provided. Post-Synthesis Simulation : SDF(standard delay format)- timing info. of each cell in the design. The place and route tools are used for layout generation. HDL Timing Simulation(Post- Layout Sim) : after the design has completed the PnR, simulation with backannotated information.

Synthesis 27/32 Synthesis = Translation+Optimization+Mapping pp

Mapping (1/2) 28/32 Original Netlist Possible Covering LUT Mapping from Covering

Mapping (2/2) 29/32 LUT0 LUT4 LUT1 LUT2 LUT5 FF1 LUT3 FF2

Typical Design Flow 30/32 HDL design : behavioral or structural description of design RTL Simulation verifies logic model & data flow. The simulation is typically performed to confirm that the code is functioning as intended. At this step, no timing information is provided. Post-Synthesis Simulation : SDF(standard delay format)- timing info. of each cell in the design. The place and route tools are used for layout generation. HDL Timing Simulation(Post- Layout Sim) : after the design has completed the PnR, simulation with backannotated information.

Placing 31/32 FPGA CLB SLICES

Routing 32/32 Programmable Connections FPGA