The Verilog Hrdwre Desription Lnguge Professor Don Thoms Crnegie Mellon University (CMU) thoms@ee.mu.edu http://www.ee.mu.edu/~thoms This is not one ohesive presenttion on Verilog. The slides ontined here re olleted from different CMU lsses t vrious demi levels. These slides re provided s n lternte id to lerning the lnguge. You my find them helpful. S ug reports to the ove ddress there re some! The Verilog Hrdwre Desription Lnguge, Fourth Edition is ville from Kluwer Ademi Pulishers, http://www.wkp.om. Phone: 78-87-6600. University fulty wnting ess to PowerPoint version of the slides should ontt the uthor t the ove ddress. Simultion of Digitl Systems Simultion Wht do you do to test softwre progrm you write? - Give it some inputs, nd see if it does wht you expet - When done testing, is there ny ssurne the progrm is ug free? NO! - But, to the extent possile, you hve determined tht the progrm does wht you wnt it to do Simultion tests model of the system you wish to uild - Is the design orret? Does it implement the inted funtion orretly? For instne, is it UART Stik in yte nd see if the UART model shifts it out orretly - Also, is it the orret design? Might there e some other funtions the UART ould do? 2 Simultion of Digitl Systems Simultion heks two properties funtionl orretness is the logi orret - orret design, nd design orret timing orretness is the logi/interonnet timing orret - e.g. re the set-up times met? It hs ll the limittions of softwre testing Hve I tried ll the ses? Hve I exerised every pth? Every option? Modern Design Methodology Simultion nd Synthesis re omponents of design methodology lwys lwys mumle mumle Synthesis lh lh lh lh Synthesizle Verilog Tehnology Mpping gtes, gtes, gtes, l l 2 Ple nd Route 3 4 Representtion: Struturl Models Representtion: Gte-Level Models Struturl models Are uilt from gte primitives nd/or other modules They desrie the iruit using logi gtes muh s you would see in n implementtion of iruit. - You ould desrie your l iruit this wy Identify: Gte instnes, wire nmes, dely from or to f. sel f module mux (f,,, sel); input,, sel; nd #5 g (f,, nsel), g2 (f2,, sel); or #5 g3 (f, f, f2); not g4 (nsel, sel); Need to model the gte s: Funtion Dely Funtion Generlly, HDLs hve uilt-in gte-level primitives - Verilog hs NAND, NOR, AND, OR, XOR, XNOR, BUF, NOT, nd some others The gtes operte on input vlues produing n output vlue - typil Verilog gte instntition is: optionl mny nd #dely instne-nme (out, in, in2, in3, ); 5 6 Pge
Four-Vlued Logi Four-Vlued Logi Verilog Logi Vlues The underlying dt representtion llows for ny it to hve one of four vlues, 0, x (unknown), z (high impedne) x one of:, 0, z, or in the stte of hnge z the high impedne output of tri-stte gte. Wht sis do these hve in relity? 0, no question z A tri-stte gte drives either zero or one on its output. If it s not doing tht, its output is high impedne (z). Tri-stte gtes re rel devies nd z is rel eletril ffet. x not rel vlue. There is no rel gte tht drives n x on to wire. x is used s deugging id. x mens the simultor n t determine the nswer nd so mye you should worry! BTW some simultors keep trk of more vlues thn these. Verilog will in some situtions. Logi with multi-level logi vlues Logi with these four vlues mke sense - Nnd nything with 0, nd you get. This inludes hving n x or z on the other input. Tht s the nture of the nnd gte - Nnd two x s nd you get n x Note: z treted s n x on input. Their rows nd olumns re the sme If you forget to onnet n input it will e seen s n z. At the strt of simultion, everything is n x. Input A Input B Nnd 0 x z 0 0 x x x x x x z x x x A 4-vlued truth tle for Nnd gte with two inputs 7 8 How to uild nd test module Another view of this Construt test enh for your design Develop your hierrhil system within module tht hs input nd output ports (lled design here) Develop seprte module to generte tests for the module ( test ) Connet these together within nother module ( testenh ) module testenh (); wire l, m, n; design d (l, m, n); test t (l, m); initil //monitor nd disply module test (q, r); output q, r; module design (,, ); input, ; output ; initil //drive the outputs with signls 3 hunks of verilog, one for eh of: TESTBENCH is the finl piee of hrdwre whih onnet DESIGN with TEST so the inputs generted go to the thing you wnt to test... Another piee of hrdwre, lled TEST, to generte interesting inputs Your hrdwre lled DESIGN 9 0 A Previous Design Module testadd generted inputs for module hlfadd nd displyed hnges. Module hlfadd ws the design module tbenh; wire su, o,, ; hlfadd testadd d(su, o,, ); t(,, su, o); module hlfadd (sum, Out,, ); output sum, Out; input, ; xor #2 nd #2 (sum,, ); (Out,, ); module testadd(,, sum, Out); input sum, Out; output, ; reg, ; initil $monitor ($time,, =%, =%, sum=%, Out=%,,, sum, Out); = 0; = 0; #0 = ; #0 = ; #0 = 0; #0 $finish; The test module It s the test genertor $monitor prints its string when exeuted. fter tht, the string is printed when one of the listed vlues hnges. only one monitor n e tive t ny time prints t of urrent simultion time Funtion of this tester t time zero, print vlues nd set ==0 fter 0 time units, set = fter nother 0, set = fter nother 0 set =0 then nother 0 nd finish module testadd(,, sum, Out); input sum, Out; output, ; reg, ; initil $monitor ($time,, =%, =%, sum=%, Out=%,,, sum, Out); = 0; = 0; #0 = ; #0 = ; #0 = 0; #0 $finish; 2 Pge 2
Other things you n do More thn modeling hrdwre $monitor give it list of vriles. When one of them hnges, it prints the informtion. Cn only hve one of these tive t time. e.g. - $monitor ($time,,, =%, =%, sum=%, Out=%,,, sum, Out); extr omms print spes - The ove will print: 2 =0, =0, sum=0, Out=0<return> % is inry (lso, %h, %d nd others) $disply() sort of like printf() - $disply ( Hello, world %h, hexvlue) disply ontents of dt item lled hexvlue using hex digits (0-9,A-F) Wht if wht you print hs the vlue x or z? newline utomtilly inluded Struturl vs Behviorl Models Struturl model Just speifies primitive gtes nd wires i.e., the struture of logil netlist You silly know how to do this now. Behviorl model More like proedure in progrmming lnguge Still speify module in Verilog with inputs nd outputs......ut inside the module you write ode to tell wht you wnt to hve hppen, NOT wht gtes to onnet to mke it hppen i.e., you speify the ehvior you wnt, not the struture to do it Why use ehviorl models For testenh modules to test struturl designs For high-level spes to drive logi synthesis tools (L 2) 3 4 How do ehviorl models fit in? How do they work with the list nd sheduler? Initil (nd lwys) exeuting t time 0 in ritrry order They exeute until they ome to #dely opertor They then susp, putting themselves in the list 0 time units in the future (for the se t the right) At 0 time units in the future, they resume exeuting where they left off. Some detils omitted...more to ome module testadd(,, sum, Out); input sum, Out; output, ; reg, ; initil $monitor ($time,, =%, =%, sum=%, Out=%,,, sum, Out); = 0; = 0; #0 = ; #0 = ; #0 = 0; #0 $finish; 5 Two initil sttements? initil = 0; = 0; #5 = ; #3 = ; initil out = ; #0 out = 0; #8 out = ; 0 0 out 0 0 0 8 Things to note Whih initil sttement strts first? Wht re the vlues of,, nd out when the simultion strts? These pper to e exeuting onurrently (t the sme time). Are they? 6 Wht do we men y Synthesis? An exmple Logi synthesis A progrm tht designs logi from strt desriptions of the logi - tkes onstrints (e.g. size, speed) - uses lirry (e.g. 3-input gtes) How? You write n strt Verilog desription of the logi The synthesis tool provides lterntive implementtions Verilog lh lh lh onstrints synthesis lirry or 7 Wht s ool? You type the left, synthesis gives you the gtes It used different lirry thn you did. (2-input gtes only) One desription suffies for vriety of lternte implementtions! Hmmm... ut this ssumes you know gte level implementtion tht s not n strt Verilog desription. module gte gte (f, (f,,,,, ); ); output f; input input,,,, ; ; nd nd A (, (,,,,, ), ), B (2, (2,,, ~, ~, ~), ~), C (3, (3, ~, ~, o); o); or or D (o, (o,,, ), ), E (f, (f,,, 2, 2, 3); 3); f 8 Pge 3
Wht Do We Wnt Here...? Gol To speify omintion kt, inputs->outputs in form of Verilog tht synthesis tools will orretly red nd then use to mke the right logi And... We know the funtion we wnt, nd n speify in C-like form... ut we don t now the ext gtes; we wnt the tool to do this. Behviorl Modeling Proedurl sttements re used Sttements using lwys Verilog onstrut Cn speify oth omintionl nd sequentil iruits Normlly don t think of proedurl stuff s logi They look like C: mix of ifs, se sttements, ssignments ut there is semnti interprettion to put on them to llow them to e used for simultion nd synthesis (giving equivlent results) A B C Comintionl Logi F Current tehnology You n do omintionl (nd lter, sequentil) design Sizle designs n tke hours dys to run Compnies py $50K - 80K per opy for suh softwre - This in t shrink-wrp softwre! The softwre we ll use is more like $0-5K 9 20 Behviorl Construts Sttements, Registers nd Wires Behviorl desriptions re introdued y initil nd lwys sttements Sttement Looks like Strts How it works Use in Synthesis? initil lwys initil lwys Strts when simultion strts Exeute one nd stop Continully loop while (power on) do sttements; Not used in synthesis Used in synthesis Points: They ll exeute onurrently They ontin ehviorl sttements like if-then-else, se, loops, funtions, 2 Registers Define storge, n e more thn one it Cn only e hnged y ssigning vlue to them on the left-hnd side of ehviorl expression. Wires (tully nets ) Eletrilly onnet things together Cn e used on the right-hnd side of n expression - Thus we n tie primitive gtes nd ehviorl loks together! Sttements left-hnd side = right-hnd side left-hnd side must e register Four-vlued logi module silly (q, r); reg [3:0], ; wire [3:0] q, r; lwys = ( & r) q; q = ; Multi-it registers nd wires Cn t do why? Logi with registers nd wires 22 Behviorl Sttements Behviorl Sttements if-then-else Wht you would expet, exept tht it s doing 4-vlued logi. is interpreted s True; 0, x, nd z re interpreted s Flse se Wht you would expet, exept tht it s doing 4-vlued logi If seletor is 2 its, there re 4 2 possile se-items to selet etween There is no rek sttement it is ssumed. Funny onstnts? Verilog llows for sized, 4-vlued onstnts The first numer is the numer of its, the letter is the se of the following numer tht will e onverted into the its. 8 00x0zx0 if (selet == ) f = in; else f = in0; se (seletor) 2 00: = + ; 2 0: q = r + s; 2 x: r = 5; defult: r = 0; se Loops There re restritions on using these for synthesis don t. They re mentioned here for use in test modules Two min ones for nd while Just like in C There is lso repet nd forever see the ook reg [3:0] testoutput, i; for (i = 0; i <= 5; i = i + ) testoutput = i; #20; reg [3:0] testoutput, i; i = 0; while (i <= 5)) testoutput = i; #20 i = i + ; Importnt: Loops must hve dely opertor (or s we ll see lter, n @ or wit(false)). Otherwise, the simultor never stops exeuting them. ssume f,, q, nd r re registers for this slide 23 24 Pge 4
Alternte: Test Module, ontinued Bit Selets nd Prt Selets This expression extrts its or rnges of its or wire or register The individul its of register i re mde ville on the ports. These re lter onneted to individul input wires in module design. module testgen (i[3], i[2], i[], i[0]); reg [3:0] i; output i; lwys for (i = 0; i <= 5; i = i + ) #20; module testgen (i); reg [3:0] i; output i; lwys for (i = 0; i <= 5; i = i + ) #20; module top; wire w0, w, w2, w3; testgen t (w0, w, w2, w3); design d (w0, w, w2, w3); module design (,,, d); input,,, d; mumle, mumle, lh, lh; module top; wire [3:0] w; testgen t (w); design d (w[0], w[], w[2], w[3]); 25 Conurrent Construts We lredy sw #dely Others @ Witing for hnge in vlue used in synthesis - @ (vr) w = 4; - This sys wit for vr to hnge from its urrent vlue. When it does, resume exeution of the sttement y setting w = 4. Wit Witing for vlue to e ertin level not used in synthesis - wit (f == 0) q = 3; - This sys tht if f is equl to zero, then ontinue exeuting nd set q = 3. - But if f is not equl to zero, then susp exeution until it does. When it does, this sttement resumes y setting q = 3. Why re these onurrent? Beuse the eing wited for n only our s result of the onurrent exeution of some other lwys/initil lok or gte. They re hppening onurrently 26 FAQs: ehviorl model exeution How does n lwys or initil sttement strt Tht just hppens t the strt of simultion ritrry order One exeuting, wht stops it? Exeuting either #dely, @, or wit(false). All lwys loks need to hve t lest one of these. Otherwise, the simultor will never stop running the model -- (it s n infinite loop!) How long will it sty stopped? Until the ondition tht stopped it hs een resolved - #dely until the dely time hs een rehed - @(vr) until vr hnges - wit(vr) until vr eomes TRUE Does time pss when ehviorl model is exeuting? No. The sttements (if, se, et) exeute in zero time. Time psses when the model stops for #, @, or wit. Will n lwys stop looping? No. But n initil will only exeute one. 27 A Comintionl Ciruit Using ehviorl onstruts Logi for simple MUX is speified proedurlly here This exmple is synthesizle module mux (f, sel,, ); input sel,, ; lwys @ (sel or or ) if (sel == ) f = ; else f = ; Red Red this this s s follows: Wit Wit for for ny ny hnge hnge on on,,,, or or,, then then exeute the the - lok lok ontining the the if. if. Then Then wit wit for for nother hnge. This This if if funtionlly desries the the MUX MUX sel Logi Synthesized f 28 Is it relly orret? Synthesis Templte Prolem? Where s the register? The synthesis tool figures out tht this is omintionl iruit. Therefore, it doesn t need register. The register is there s n rtift of the desriptions things on the lefthnd side hve to e registers. How does it figure out tht this is omintionl? - The output is only funtion of the inputs (nd not of previous vlues) - Anytime n input hnges, the output is re-evuted Think out the module s eing lk ox - Could you tell tht there is register in there? module mux (f, sel,, ); input sel,, ; lwys @ (sel or or ) if (sel == ) f = ; else f = ; f 29 Using proedurl sttements in Verilog Logi is speified in lwys sttements ( Initil sttements re not llowed). Eh lwys sttement turns into Boolen funtions module lh (f,,, ); input,, ; lwys @ ( or or ) stuff... stuff... stuff... You You hve hve to to delre delre the theomintionl outputs like like this, this, for for synthesis. i.e., i.e., tool tool needs needs to to think think you you re re putting putting these these omputed outputs someple. You You hve hve to to list list ll llthe lok s lok s inputs inputs here here in in the the sensitivity list list Atully do do logi logi in in here. here. There There re re unh unh of of sutle sutle rules rules to to ensure ensure tht tht synthesis won t won t mess mess this this up... up... We ll We ll see see how how 30 Pge 5
How? A Few Definitions There re some restritions on speifition Input set of n lwys sttement the set of ll vriles tht re used on the right-hnd side of proedurl ssignments or in onditionls. i.e. nything soured. Sensitivity list of n lwys sttement the set of ll nmes tht pper in the ( @ ) list. module mux (f, sel,, ); The elements in these lists re: input sel,, ; lwys @ (sel or or ) if (sel == ) f = ; else f = ; More Definitions... A ontrol pth of n lwys sttement sequene of opertions performed when exeuting the lwys sttement Comintionl output of n lwys sttement vrile (or vriles) ssigned to in every ontrol pth module mux (f, sel,, ); input sel,, ; lwys @ (sel or or ) if (sel == ) f = ; else f = ; Wht re they here... 3 32 The Bsi Rules The rules for speifying omintionl logi using proedurl sttements Every element of the input set must e in the sensitivity list The omintionl output must e ssigned in every ontrol pth Wht If You Mess Up? If you don t follow the rules...? you re ded met Verilog ssumes you re trying to do something lever with the timing It s legl, ut it won t e omintionl The rules for wht it does mke sense -- ut not yet for us. module mux (f, sel,, ); input sel,, ; lwys @ (sel or or ) if (sel == ) f = ; else f = ; So, So, we re we re sying sying tht tht if if ny ny input input hnges, then then the the output output is is reevluted. Tht s Tht s the the definition of ofomintionl logi. logi. re- Wlking this this nrrow nrrow line line llows llows you you to to speify speify nd nd synthesize omintionl logi logi module lh (f, g,,, ); output f, g; input,, ; reg f, g; lwys @ ( or or ) if ( == ) f = ; else g = ; This This sys: sys: s s long long s s ==, ==, then then f f follows follows.. (i.e. (i.e. when when hnges, so so does does f.) f.) But, But, when when ==0, ==0, f f rememers the the old old vlue vlue of of.. Comintionl iruits don t don t rememer nything! Wht s Wht s wrong? f f doesn t pper pper in in every everyontrol pth pth in in the the lwys lwys lok lok (neither does does g). g). 33 34 Typil Style A Diffiulty Your Verilog for omintion stuff will look like this: module lh (<output nmes>, <input nmes>); output <output nmes>; input <input nmes>; reg <output nmes>; Assigning in every ontrol pth If the funtion is omplex, you don t know if you ssigned to the outputs in every ontrol pth. So, set ll outputs to some known vlue (zero here) nd write the ode to set them to other vlues s needed. Synthesis tools will figure it out. lwys @ (<nmes of ll input vrs>) < LHS = RHS ssignments> < if... else sttements> < se sttements > Yes...it s pretty restrited suset of the lnguge... lwys @(oke or ol) if (oke) lh = ; else if (ol > 2 0) lh2 = oke; else if ( lwys @(oke or ol) lh = 0; lh2 = 0; if (oke) lh = ; else if (ol > 2 0) lh2 = oke; else if ( 35 36 Pge 6
Using se sttement How out Cse Sttement Ex? Truth tle method List eh input omintion Assign to output(s) in eh se item. Contention {,, } ontentes,, nd together, onsidering them s single item Exmple = 4 0 = 6 x000 = 2 zx then {,, } = 2 0x000zx module fred (f,,, ); input,, ; lwys @ ( or or ) se ({,, }) 3 000: f = 0; 3 00: f = ; 3 00: f = ; 3 0: f = ; 3 00: f = ; 3 0: f = 0; 3 0: f = 0; 3 : f = ; se Chek the rules 37 Here s nother version... module fred (f,,, ); input,, ; lwys @ ( or or ) se ({,, }) 3 000: f = 0; 3 00: f = ; 3 00: f = ; 3 0: f = ; 3 00: f = ; 3 0: f = 0; 3 0: f = 0; 3 : f = ; se Could put funtion here too hek the rules module fred (f,,, ); input,, ; lwys @ ( or or ) se ({,, }) 3 000: f = 0; 3 0: f = 0; 3 0: f = 0; defult: f = ; se Importnt: every ontrol pth is speified 38 Don t Cres in Synthesis Rules You n t sy if ( == x) this hs mening in simultion, ut not in synthesis. However, n unknown x on the right-hnd side will e interpreted s don t re. f ~ 00 0 0 0 x 0 x module seexmple(f,,, ); input,, ; lwys @ ( or or ) se ({,, }) 3 00: f = ; 3 00: f = ; 3 0: f = ; 3 00: f = ; 3 : f = ; 3 0: f = 0; defult: f = x; se The inverse funtion ws implemented; x s tken s ones. Alterntively module fred (f,,, ); input,, ; lwys @ ( or or ) f = ~( & & ~); 00 0 0 0 x 0 x These ren t quite equivlent to the previous slidewhy? module fred2 (f,,, ); input,, ; lwys @ ( or or ) f = ~ ~; module fred3 (f,,, ); input,, ; lwys @ ( or or ) if ( ==0) f = ~&; else f = ; 39 40 Two inputs, Three outputs Behviorl Model Sensitivity reg [:0] newj; reg out; input i, j; lwys @(i or j) se (j) 2 00: newj = (i == 0)? 2 00 : 2 0; out = 0; 2 0 : newj = (i == 0)? 2 0 : 2 0; out = ; 2 0 : newj = 2 00; out = 0; defult: newj = 2 00; out = 'x; se Works Works like like the the C onditionl opertor. (expr) (expr)? :: ; ; If If the theexpr expris is true, true, then then the the resulting vlue vlue is is,, else else it s it s.. 4 A Quik exmple Gte A hnges its output, gtes B nd C re evluted to see if their outputs will hnge, if so, their fnouts re lso followed The ehviorl model will only exeute if it ws witing for hnge on the D input Wht order will the gtes nd ehviorl model exeute in. D B C Behviorl model lwys @ (D) ydd ydd lwys @ (F) ydd ydd = D; Will this exeute? Will this exeute? 42 Pge 7
Wht out time dely Model Orgniztion Could we hve desried the module s shown here? Note the delys. There is different dely from the input thn from the input. Yes, you ould write this But, Synthesis tools will ignore the time delys. Generlly, they try to minimize the propgtion from ny omintionl input to ny omintionl output in the system. module mux (f, sel,, ); input sel,, ; lwys @ (sel or or ) if (sel == ) #5 f = ; else #88 f = ; 43 Here s n lwys lok for omintionl funtion. Wht Boolen funtions n it model? Cn I hve more thn one of these lwys loks in module? Yes Cn two seprte lwys lulte funtion f? No module xyzzy (ports); lwys @( or 2 or 3) f = ydd; lwys @(r or r2 or r3) f = ydd ydd; Nope! lwys @( or 2 or 3) ydd ydd Only those with inputs, 2, nd 3 (or suset) module xyzzy (ports); lwys @( or 2 or 3) q = 2 3 r = 2 3 lwys @(r or r2 or r3) s = ydd ydd ydd 44 Model Orgniztion Trde-Off Module prtitioning n ffet logi optimiztions Here re two modules The output of lo is onneted to lo2 The synthesis tool will optimize them seprtely - No ommon prime implints, et, will e shred or optimized etween the two modules. module lo(inputs, outputs) lwys @(inputs) outputs = lh & inputs; module lo2(inputs, outputs2) lwys @(inputs) outputs2 = lh & inputs; Alternte module lo_2(inputs, outputs) - Put everything in one module lwys @(inputs) - Now there s possiility outputs = lh & inputs; for optimiztion etween lwys @(outputs) funtions outputs = lh & outputs; 45 Verilog Overview Verilog is onurrent lnguge Aimed t modeling hrdwre optimized for it! Typil of hrdwre desription lnguges (HDLs), it: - provides for the speifition of onurrent tivities - stnds on its hed to mke the tivities look like they hppened t the sme time Why? - llows for intrite timing speifitions A onurrent lnguge llows for: Multiple onurrent elements An in one element to use tivity in nother. (An is n output or stte hnge t given time) - sed on interonnetion of the element s ports Further exeution to e delyed - until speifi ours 46 Disrete Event Simultion Contrst Quik exmple Gte A hnges its output. This uses gtes B nd C to exeute - But s we ll see, A doesn t ll B nd C (s in A funtion ll) - Rther, they exeute euse they re onneted Oservtion The elements in the digrm don t need to e logi gtes SimCity is disrete simultor, Verilog too Disrete Event Simultion Events hnges in stte our t disrete times. These use other s to our. Time dvnes in disrete (not ontinuous) steps B C Non-disrete Event Simultion Continuous systems ll elements nd stte re updted t every simultion time Could you do logi iruits tht wy too? - e.g. nlog iruits, numeril integrtion - differentil equtions to solve 47 48 Pge 8
Disrete Event Simultion Bsi models things not found in C gte level uilt-in models for AND, OR, - When n input to one of these hnges, the model exeutes to see if its output should hnge ehviorl level sort-of C-like progrms ut with few extr opertors - Exeutes until it loks for one of three resons #dely, wit(level), or @() when the reson for loking is resolved, it ontinues exeuting - Does C hve ny notion of these? Gte nd ehviorl models n dvne time How does it keep trk of time? Expliitly Events re stored in n list (tully 2-D list) ordered y time Events exeute t time nd possily shedule their output to hnge t lter time ( new ) When no more s for the urrent time, move to the next Events within time re exeuted in ritrry order time time +75 time +75492 Let s Let s sy sy A hnges to to 0 here. here. B nd nd C hve hve dely dely 2. 2. A B C 49 50 Approh to Simulting System Two piees of simultion The model n exeutle speifition inluding timing, interonnet, nd input vetors - Written in lnguge like Verilog or VHDL - Wht s VHDL? The simultion sheduler - keeps trk of when s our, - ommunites s to pproprite prts of the model, - exeutes the model of those prts, nd - s result, possily shedules more s for future time. Verilog Levels of Astrtion Gte modeling the system is represented in terms of primitive gtes nd their interonetions - NANDs, NORs, Behviorl modeling the system is represented y progrm-like lnguge D Q D Q lwys @posedge lok Q = #5 D - it mintins simulted time nd the list. gte-level model ehviorl model 5 52 Mixing Levels A Gte Level Model Generlly there is mix of levels in model e.g. prt of the system is t the gte level nd nother prt is t the ehviorl level. Why? - Erly in design proess you might not hve fully-detiled models you don t tully know ll the gte implementtions of the multipliers, dders, register files - You might wnt to think of the design t oneptul level efore doing ll the work to otin the gte implementtions - There might e fmily of implementtions plnned Levels swith, gte, funtionl lok (e.g. ALUs), register-trnsfer, ehviorl - for now, we ll del with gte nd ehviorl models These re ll modeled s disrete systems no ontinuous modeling of nlog ehvior A Verilog desription of n SR lth set reset g g2 q qbr 53 54 Pge 9
A Gte Level Model A Gte Level Model A Verilog desription of n SR lth A module is defined nme of the module nnd #2 g (q, qbr, set), g2 (qbr, q, reset); the module hs ports module nndlth (q, qbr, set, reset); output q, qbr; ports re set input set, reset; typed type nd dely of gtes reset primitive gtes with nmes nd interonnetions g g2 q qbr Things to note: It doesn t pper exeutle no for loops, if-then-else, et. - it s not in progrmming sense, rther it desries the interonnetion of elements A new module mde up of other modules hs een defined - softwre engineering spet we n hide detil module nndlth (q, qbr, set, reset); output q, qbr; input set, reset; nnd #2 g (q, qbr, set), g2 (qbr, q, reset); 55 56 Exeution model But, there is n exeution model Gte-level timing model Timing model how time is dvned, wht triggers new proessing in the model Here when ny of the inputs of primitive gte hnge, the output is re-evluted. If there is new result, it is pssed on to other gtes on its fnout. module nndlth (q, qbr, set, reset); output q, qbr; input set, reset; nnd #2 g (q, qbr, set), g2 (qbr, q, reset); Behviorl Modeling Why not desrie module s funtion nd dely using lnguge like C? Sound like fun, here goes reg reg delres one-it one-it register. Cn Cn e e thought module d_type_ff (q, lok, dt); of of s s eing eing similr similr to to output q; vrile in in progrmming. reg q; BTW, BTW, eh eh instntition input lok, dt; of of this this module will will hve hve seprte register q. q. lwys @(negedge lok) q = #0 dt; lwys lwys while while TRUE TRUE Continuously do do the the following sttement. @ wit wit for for negtive edge edge on on lok, lok, evlute dt dt now now nd nd wit wit 0 0 time time units. units. Then Then ssign ssign q to to tht tht vlue vlue nd nd wit wit for for the the next nextnegedge 57 58 Behviorl Modeling Comprison These two models re interhngle either ould hve een instntited into register - ports in sme order - sme dely from lok to q - one is strt, ler - one is speifi - there re sutle differenes module d_type_ff (q, lok, dt); output q; reg q; input lok, dt; lwys @(negedge lok) q = #0 dt; Behviorl module d_type_ff (q, lok, dt); input lok, dt; output q; wire q, qbr, r, s, r, s; nor #0 (q, qbr, r); nor (qbr, q, s), (s, r, lok, s), d (s, s, dt), e (r, r, lok), f (r, s, r); Struturl At first look, it is lot like C Most of the opertors re the sme s C ^ is XOR, et. mkes it esy to red But there re mjor differenes (quik list, we ll get to these) sttements like #dely, @, wit(level) - the lnguge is onurrent n speify mny things tht n hppen t the sme time. four-vlued logi (, 0, x, z) nd the opertors to go with them ritrry it width speifition there re ouple of proedurl ssignments (=, <=) with sutle differenes different timing model 59 60 Pge 0
Behviorl Timing Model (Not fully detiled here) How does the ehviorl model dvne time? # delying speifi mount of time @ delying until n ours ( posedge, negedge, or ny hnge) - this is edge-sensitive ehvior wit delying until n ours ( wit (f == 0) ) - this is level sensitive ehvior Wht is ehviorl model sensitive to? ny hnge on ny input? No ny tht follows, sy, posedge keyword - e.g. @posedge lok - Atully no here too. not lwys A Wht re ehviorl models sensitive to? Quik exmple Gte A hnges its output, gtes B nd C re evluted to see if their outputs will hnge, if so, their fnouts re lso followed The ehviorl model will only exeute if it ws witing for hnge on the A input A B C Behviorl model lwys @(A) B = ~A; lwys @(posedge lok) Q <= A; This would exeute This wouldn t 6 62 Order of Exeution Aritrry Order? Oops! In wht order do these models exeute? Assume A hnges. Is B, C, or the ehviorl model exeuted first? - Answer: the order is defined to e ritrry All s tht re to our t ertin time will exeute in n ritrry order. The simultor will try to mke them look like they ll our t the sme time ut we know etter. A A B C Behviorl model lwys @(A) ydd ydd Sometimes you need to exert some ontrol Consider the interonnetions of this D- FF At the positive edge of, wht models re redy to exeute? Whih one is done first? Oops The order of exeution n mtter! film t shiftin lok module dff(q, d, ); lwys @(posedge ) q = d; module sreg (); dff (q0, shiftin, lok), (q, q0, lok), (shiftout, q, lok); D Q D Q D Q shiftout 63 64 Some more gte level exmples An dder module dder (rryout, sum, Input, Input, rryin); output rryout, sum; input Input, Input, rryin; xor (sum, Input, Input, rryin); or (rryout,,, ); nd (, Input, Input), (, Input, rryin), (, Input, rryin); list list of of gte gte instnes of of sme sme funtion (nd) (nd) impliit impliit wire wire delrtions Input rryin Input no no instne nmes nmes or or delys delys sum rryout Adder with delys An dder with delys module dder (rryout, sum, Input, Input, rryin); output rryout, sum; input Input, Input, rryin; wht s this men? xor #(3, 5) (sum, Input, Input, rryin); or #2 (rryout,,, ); nd #(3, 2) (, Input, Input), (, Input, rryin), (, Input, rryin); eh eh AND AND gte gte nd nd #(3, #(3, 2) 2) (, (, Input, Input, Input), instne hs hs the the (, sme sme dely (, Input, Input, rryin); dely nd nd #(7, #(7, 3)(, 3)(, Input, Input, rryin); lternte timing 65 66 Pge
Adder, ontinuous ssign I m sik of this dder Using ontinuous ssignment Continuous ssignment llows you to speify omintionl logi in eqution form Anytime n input (vlue on the right-hnd side) hnges, the simultor re-evlutes the output No gte struture is implied logi synthesis n design it. - the desription is little more strt A ehviorl funtion my e lled detils lter module dder (rryout, sum, Input, Input, rryin); output rryout, sum; input Input, Input, rryin; ssign sum = Input ^ Input ^ rryin, rryout = (Input & Input) (Input & rryin) (Input & rryin); 67 Continuous ssignment ssigns ontinuously delys n e speified (sme formt s for gtes) on whole eqution no instnes nmes nothing is eing instntited. given the sme delys in this nd the gte-level model of n dder, there is no funtionl differene etween the models - FYI, the gte-level model gives nmes to gte instnes, llowing k nnottion of times. module dder (rryout, sum, Input, Input, rryin); output rryout, sum; input Input, Input, rryin; ssign #(3, 5) sum = Input ^ Input ^ rryin; ssign #(4, 8) rryout = (Input & Input) (Input & rryin) (Input & rryin); 68 Continuous Assign Using ontinuous ssign vs gte instntitions strt rndom logi drives wires detiled, speifi used for speifying unknowns lods registers multiit dtpth elements typilly no notion of wire delys Gte level timing model Exeution model exeution model how time dvnes nd new vlues re reted fundmentl onept in ny lnguge Gte level timing model pplies to oth primitive instntitions nd ontinuous ssigns Definition when n input hnges, the simultor will evlute the primitive or ontinuous ssign sttement, lulting new output if the output vlue is different, it is propgted to other primitive nd ssign inputs nothing sid yet out ehvior. whih goes with whih? 69 70 Gte level timing model Wht s n input? n input to gte primitive nything on the right-hnd side of the = in ontinuous ssign Wht s n output? the output of gte primitive nything on the left-hnd side of the = in ontinuous ssign Outputs on this side of the lnguge re ll wires no registers re lthed/loded, no need to know out lok i.e. the left-hnd sides re ll wires Contrst The left-hnd sides on the ehviorl side of the lnguge re ll registers Event-Driven Simultion How does the simultor exeute gte-level model Event-driven simultion Event vlue-hnge ours t given time The -driven simultor only exeutes models when s our - (some simultors exeute every model every time unit) time ordered list remove urrent s Gte Outputs updtes Sheduler looks t Network Connetions (fnouts) shedules new exeutes Gte Models 7 72 Pge 2
Events Two types of s Evlution s evlute, or exeute, gte model or ontinuous ssign. - produe updte s - i.e. if the output hnges, shedule n updte Updte s propgte new vlues long fnout. - produe evlution s - for eh element on the fnout, shedule n evlution We ll tret these s seprte types of s gte level simultors generlly omine them for effiieny i.e. when n output is updted, insted of sheduling n evlution, just do the evlution nd shedule ny updtes resulting from it. We ll keep them seprte for now it will help in the lter disussion of ehviorl models Event-Driven Simultion while something in time-ordered list { dvne simultion time to top s time retrieve ll s for this time } For eh in ritrry order If it s n updte Updte the vlue speified. Follow fnout nd evlute gte models. Shedule ny new updtes from gtes. Shedule evl s for ehviorl models else // it s n evlution evlute the model shedule resulting updte s u e e u 73 74 Event-Driven Simultion Event-driven simultion the list Updte A= t 25 init vlues s shown Updte init A= t vlues s 25 shown Updte A= t 25 init vlues s shown A=0 A= g #2 0 g #2 0 C=0 g2 #3 B= D= g3 #5 C=0 g2 #3 B=0 D= g3 #5 Updte init A= t vlues s 25 shown Updte init A= t vlues s 25 shown A= Updte init A= t vlues s 25 shown C= g2 #3 g #2 B=0 D= 0 g3 #5 finl 75 76 Gte level timing model Wht if n updte is lredy sheduled for n output? if the vlue eing sheduled is different, the urrently sheduled vlue is removed from the list; the new is not sheduled thus, ny input pulse shorter thn the propgtion dely will not e seen (inertil dely) Sheduling nd list mngement Cn think of the list s 2-D linked list One dimension links ll the s for given time The seond dimension links these lists in sing order Prolem ineffiient most s re ner in time to the urrent one, thus lots of linked list shing time = nnd #5 (,, ); time + updte sheduled time +2 propgtion dely = 5 updte removed, finl vlue wht hppens in four-vlued logi? time +3 time +99692 77 78 Pge 3
Sheduling nd list mngement Hk of the rih nd fmous Timing wheel M nerest time slots stored in n rry M is power of two Aess list y (time mod M) tle lookup Essentilly turned first linked list ess into n rry ess sving time Further out times re kept in linked list. As time is dvned, further out times re rought into wheel rry time Asides Cn gte model e exeuted severl times in time step? Does the order of exeution of the gtes in omintionl iruit mtter? time + time +2 time +3 time + M - timing wheel 79 80 Summry on gte evlution Timing model timing-exeution model - how time is dvned nd new vlues reted Any gte input or ssign righthnd-side hnge uses the model to e evluted during the time step - this is not the se for ehviorl models they hve different timing model Fnout list is stti design never hnges Gte level modeling detiled timing Continuous ssignment strt Wht if you don t like these models? e.g., inertil delys? use ehviorl models Review Stuff Updte Events A new vlue ppers t some simulted time Evlution Events A model is exeuted (evluted) t some simulted time Event List A time-ordered list of s Simultion sheduler Softwre progrm tht mnges the list y sheduling updte nd evlution s, tring fnouts to propgte vlues, nd mnges simulted time 8 82 Behviorl Timing Model Wit How does the ehviorl model dvne time? # delying speifi mount of time @ delying until n ours e.g. @v - posedge, negedge, or ny hnge - this is edge-sensitive ehvior - When the sttement is enountered, the vlue v is smpled. When v hnges in the speified wy, exeution ontinues. wit delying until n ours ( wit (f == 0) ) - this is level sensitive ehvior While one model is witing for one of the ove resons, other models exeute time mrhes on Wit wits for level on line How is this different from n @? Semntis wit (expression) sttement; - e.g. wit ( == 35) q = q + 4; if the expression is FALSE, the proess is stopped - when eomes 35, it resumes with q = q + 4 if the expression is TRUE, the proess is not stopped - it ontinues exeuting Prtil omprison to @ nd # @ nd # lwys lok the proess from ontinuing wit loks only if the ondition is FALSE 83 84 Pge 4
An exmple of wit module hndshke (redy, (redy, dtout, ) ) input input redy; redy; output output [7:0] [7:0] dtout; reg reg [7:0] [7:0] somevlueweclulted; lwys lwys wit wit (redy); dtout = somevlueweclulted; wit wit (~redy) Do you lwys get the vlue right when redy goes from 0 to? Isn t this edge ehvior? redy Wit vs. While Are these equivlent? No: The left exmple is orret, the right one isn t it won t work Wit is used to wit for n expression to eome TRUE - the expression ully eomes TRUE euse vrile in the expression is hnged y nother proess While is used in the norml progrmming sense - in the se shown, if the expression is TRUE, the simultor will ontinuously exeute the loop. Another proess will never hve the hne to hnge in. Infinite loop! - while n t e used to wit for hnge on n input to the proess. Need other vrile in loop, or # or @ in loop. module yes (in, ); input in; wit (in == ); module no (in, ); input in; while (in!= ); 85 86 Bloking proedurl ssignments nd # We ve seen loking ssignments they use = Options for speifying dely #0 = + ; = #0 + ; The differenes: The differene? Events @something Ation when first enountered, smple the expression wit for expression to hnge in the indited fshion This lwys loks Exmples lwys @(posedge k) q <= d; lwys @(hello or goodye) = ; Note the tion of the seond one: - n intr-ssignment time dely - exeution of the lwys sttement is loked (susped) in the middle of the ssignment for 0 time units. - how is this done? lwys @(hello) = ; lwys ydd = ydd; @(posedge hello or negedge goodye) = ; 87 88 Sensitivity Lists In the gte level timing model model exeution ws sensitive to ny hnge on ny of the inputs t ny time. sensitivity list list of inputs tht model is sensitive to - hnge on ny of them will use exeution of the model In the gte level timing model, the lists don t hnge. Ditto with ontinuous ssign In proedurl models the sensitivity list hnges s s funtion of time nd exeution module d_type_ff (q, lok, dt); input lok, dt; output q; nor #0 (q, qbr, r); nor (qbr, q, s), (s, r, lok, s), d (s, s, dt), e (r, r, lok), f (r, s, r); Struturl Fnout Lists Outputs of things re onneted to inputs of other things No surprise The simultor mintins list of inputs driven y eh output Why? When the output hnges, it s esy to figure out wht other models need (to e) evluted Wht s n output in the ove sense? Beuse of proedurl models Fnout lists hnge Fnout lists < > Sensitivity lists 89 90 Pge 5
Behviorl Timing Model Wht is the ehviorl model sensitive to? The ehviorl sttements exeute in sequene (one then the next) Therefore, wht ehviorl model is sensitive to is ontext speifi - i.e. it is only sensitive to wht it is urrently witing for - time, edge, level (#, @, wit) The model is not sensitive to hnge on y, or w. lwys @ (negedge lok) q = y; @ (negedge lok2) q = w; @ (posedge lok) /*nothing*/ ; @ (posedge lok2) q = 3; Here, Here, it it is is only only sensitive to to lok lok Here, Here, it it is is only only sensitive to to lok2. lok2. A posedge on on lok lok will will hve hve no no effet effet when when witing witing here. here. It It is is never never sensitive to to hnges on on y or or w 9 Sheduling #, @, nd Wit How re #, @, nd wit tied into the list? # dely - shedule the resumption of the proess put it in the queue dely units into the future. Essentilly n evlution sheduled in the future @ hnge - when susped for n @v, the ehviorl model is put on the fnout list of the vrile v. i.e., the ehviorl model is now sensitive to v. - When n updte for v ours, (e.g. posedge), then the ehviorl model is sheduled to resume t the urrent time n evlution. Wit (exp) - if exp is TRUE, don t stop - if exp is FALSE, then the ehviorl model is put on the fnout list(s) of the vrile(s) in exp. (it s now sensitive to the vrile(s)) - When there is n updte for ny of the vriles in exp, exp is evluted. If exp is TRUE, resume exeuting in the urrent time (shedule n evl ), else go k to sleep 92 Non-loking ssignments (<=) Two importnt spets to these n intr-ssignment time dely doesn t stop them (they re nonloking) they implement onurrent ssignment Exmple intr-ssignment time dely non-loking ssignments use <= <= #0 + ; Wht hppens? + is lulted n updte for is sheduled #0 in future exeution of the lwys ontinues in the urrent time - the exeution of the lwys is not loked y the dely there is lso sutle differene in how is updted - we ll get to it, ut first, n exmple Intr-Assignment Non-loking Exmple Wht s the differene? module proand (, (,,, ); ); input input,, ; ; output output ; ; lwys lwys @( @( or or ) ) = #5 #5 & ; ; module proand2 (2, (2,,, ); ); input input,, ; ; output output 2; 2; lwys lwys @( @( or or ) ) 2 2 <= <= #5 #5 & ; ; 2 5 ssume = Whih is similr to n AND primitive? 93 94 Non-Bloking Conurrent Assignment Edges in time onurrent ssignment Conurrent Assignment primry use of <= The ssignment is gurded y n edge All ssignments gurded y the edge hppen onurrently - All right-hnd sides re evluted efore ny left-hnd sides re updted - Like this module fsm (Q, Q0, in, lok); output Q, Q0; input lok, in; reg Q, Q0; lwys @(posedge lok) Q <= in & Q0; Q0 <= in Q; Q0 in Q lok D D Q Q Q Q0 module fsm (Q, Q0, in, lok); output Q, Q0; input lok, in; reg Q, Q0; lwys @(posedge lok) Q <= in & Q0; Q0 <= in Q; Vlues Vlues fter fterthe the lok lok edge edge (t (t + + )) lulted in in response to to the the lok lok edge, edge, using using vlues vlues t t the the lok lok edge edge Q0 in Q lok Vlues Vlues t tthe the lok lok edge. edge. (At (At tt - ) - ) D Q D Q Q Q0 95 96 Pge 6
Alterntes not ll equivlent module fsm (Q, Q0, in, lok); module fsm (Q, Q0, in, lok); output Q, Q0; output Q, Q0; input lok, in; input lok, in; reg Q, Q0; reg Q, Q0; How out these? module fsm (Q, Q0, in, lok); output Q; input lok, in, Q0; reg Q; module fsm (Q, Q0, in, lok); output Q; input lok, in, Q0; reg Q; lwys @(posedge lok) Q <= in & Q0; Q0 <= in Q; module fsm (Q, Q0, in, lok); output Q, Q0; input lok, in; reg Q, Q0; lwys @(posedge lok) Q0 <= in Q; Q <= in & Q0; lwys @(posedge lok) Q = in & Q0; Q0 = in Q; A very different niml? The sme? 97 lwys @(posedge lok) Q <= in & Q0; module fsm0 (Q, Q0, in, lok); output Q0; input lok, in, Q; reg Q0; lwys @(posedge lok) Q0 <= in Q; Will these work? lwys @(posedge lok) Q = in & Q0; module fsm0 (Q, Q0, in, lok); output Q0; input lok, in, Q; reg Q0; lwys @(posedge lok) Q0 = in Q; These? 98 The Importnt Aspet Non-Bloking Conurrent trnsfers Aross the whole design, ll right-hnd sides re evluted efore ny left-hnd sides re updted. Thus, the order of r-hs s evluted nd l-hs s updted n e ritrry (ut seprte) This llows us to hndle onurrent speifition in mjor systems redue the omplexity of our desriptions tth lots of tions to one the lok A Stte Chnge Clok Clok Find ll of your stte vriles Not just FSM stte, ut registers in dtpth too They re proly ll keyed to n edge of lok Use <= to ssign to them t the edge You re gurnteed they ll ll e smpled efore ny of them re updted. A hek: in mny ses, the only #dely opertor you need is in the lok (for funtionl speifition) 99 00 Event List: We told fi This is wht we told you efore: Differenes in the Event List Sheduling Previous piture of douly linked list time time time We lied! Issues In onurrent lnguge, there re some very dirty issues regrding the ritrry order of exeution. In softwre, suh issues re hndled y synhroniztion primitives - Some of you hve proly seen semphores in the OS or reltime (emedded systems) ourse - They only llow other onurrent prts of system to see full stte hnges, not prtil. Stte hnges pper tomi - These provide very len wy to enfore order (tully, mutul exlusion) within zero time time More detiled view Three lists per time time Regulr s, s, gte gte outputs, ontinuous ssign ssign outputs, updtes of of loking proedurl ssignments Non-loking proedurl updtes Monitor s s 0 02 Pge 7
Wht gets sheduled when/where A piture of the list Now While there re regulr s: - retrieve ll regulr s for urrent time nd exeute in r. order - Note: These my produe more regulr s for urrent time Retrieve ll non-loking s for the urrent time nd exeute - these my produe more regulr s for urrent time, if so When no more s, do monitor s. No new s produed = = Regulr s <= <= Non-loking s Monitors = <= Future Time time Monitor s s Regulr s, s, gte gte outputs, ontinuous ssign ssign outputs, updtes of of loking proedurl ssignments Non-loking proedurl updtes Current time Wht Wht hppens? <= <= + q $monitor ( q) 03 04 Follow the Exeution Follow the Exeution module fsm (Q, Q0, in, lok); output Q, Q0; input lok, in; reg Q, Q0; lwys #0 lok = ~lok; module dff (Q, D, lok); output Q; input lok, D; reg Q; Q0 in #3 D Q Q lwys @(posedge lok) Q <= in & Q0; Q0 <= in Q; lwys @(posedge lok) Q <= D; lwys #0 lok = ~lok; Q lok #3 D Q Q0 regulr lok eomes 0 regulr lok eomes 0 non-b non-b time 20 time 30 time 40 time 20 time 30 time 40 05 06 More Sheduling previous vlues: vlues: A = A B = 0 S = 0 B new new vlues vlues t t C time time 0: 0: A = 0 S B = S = D E Z More Sheduling previous vlues: vlues: x nd (,, ); lwys = 0; #0 q = ; #0 initil = ; regulr non-b U: A=0 B= S= regulr non-b 0 0 07 08 Pge 8
Other strnge things you n do A 4-stge pipelined multiplier every lok edge, the nd inputs re red nd their produt is sheduled to pper three lok periods lter module pipemult (produt,,,,, k); k); input input k; k; input input [9:0] [9:0],, ; ; output output [9:0] [9:0] produt; reg reg [9:0] [9:0] produt; lwys lwys @(posedge k) k) produt <= <= repet repet (3) (3)@(posedge k) k) ** ; ; Some ugly rmifitions You need to e reful when mixing loking nd nonloking ssignments loking you n red it like regulr C lnguge ssignments. The vlue of the vrile on the left-hnd side n e used in the next sttement on the right-hnd side non-loking the ssignment is sheduled to pper t lter time. The vlue on the left-hnd side is not ville in the next sttement. The Verilog Polie sy: reful on how you mix = 3 these! = 4 <= <= 3 + 4 Wht vlue is ssigned to? who res = Generl rule: for stte use <=. For intermedite vlues nd omintionl elements, use = 09 0 Closer Look t the Sheduler Advne time time while (there re s in the list) { if (there re no s for the urrent time dvne urrenttime to the next time if (there re no regulr s for the urrent time) Do if (there re non-loking ssignment updte s) Do loking, turn these into regulr s for the urrent time non-loking, else then then monitors if (there re ny monitor s) turn these into regulr s for the urrent time Unshedule (remove) ll the regulr s sheduled for urrenttime Mostly For eh of these s, in ritrry order { Mostly Updte if (this is n updte ) { Updte nd nd Updte the vlue speified gte gteevls evls Evlute gtes on the fnout of this vlue nd Shedule updte s for gte outputs tht hnge Shedule evlution s for ehviors witing for this vlue } else { // it s n evlution Evlute the model Mostly Mostly Shedule ny updte s resulting from the evlution Proedurl } evls evls } } Gte-Level Modeling Need to model the gte s: funtion dely Funtion Generlly, HDLs hve uilt-in gte-level primitives - Verilog hs NAND, NOR, AND, OR, XOR, XNOR, BUF, NOT, nd some others The gtes operte on input vlues produing n output vlue - typil Verilog gte instntition is: optionl mny nd #dely nme (out, in, in2, in3, ) - multi-level logi used in some models to represent: vlues, edges, unknowns, high impednes, 2 Logi Vlues Verilog Logi Vlues, 0, x (unknown), z (high impedne) x one of:, 0, z, or in the stte of hnge z the high impedne output of tri-stte gte. Generlly treted s n x on n input. Off-the-wll, ut importnt, vlues ( prtil list) rising edge posedge - 0->x; x->; 0-> flling edge negedge - ->x; x->0; ->0 swith-trnsistor vlues - strong ; wek ; Logi with multi-level logi vlues note: z treted s n x on input Nnd 0 x z 0 0 x x x x x x z x x x some lnguges llow you to define funtion sed on multi-level logi vlues (Verilog does) Dely Models Dely models for gtes: views nd definitions Bsi view: the funtion nd dely re seprte - The funtion is hndled y model exeution, the dely y the simultor sheduler An An evlution uses uses this this vlue vlue to to e e lulted nnd dely then then it s it s sheduled s s n n updte updte nd nd propgted here. here. 3 4 Pge 9
Kinds of delys Definitions Zero dely models funtionl testing - there s no dely, not ool for iruits with feedk! Unit dely models ll gtes hve dely. OK for feedk Trnsport dely input to output dely Inertil dely how long must n input spike e to e seen? - in Verilog, inertil == trnsport Dely Models Other ftors Dely n e funtion of output trnsition Need numer for eh of the rrowheds z Verilog exmple 0 x not # (3, 5, 7) (nr, n); τ trnsport dely Inertil dely too smll, no output hnge primitive gte instntition rising dely 0-> 0->x x-> z-> flling dely ->0 ->x x->0 z->0 dely to z (tristte gtes only) n nr 5 6 Dely Models Unknown Delys different simultors do different things d = rndomize (min, mx, distriution) - dely is determined per gte t simultor strtup time, sme time used for gte throughout - this might model TTL hips, ut not gtes on n IC Why? d = (min, typil, mx) - dely to use is determined y simultor ommnd t simultor strtup time (i.e. one is seleted) - for Verilog, eh of the three timing vlues n e repled y triple (min:typ:mx) Overridden Delys Delys Overridden Use tul delys to override speified model delys Most importntly, dely due to loding nd pth lengths is mde more urte - generlly, this dds to the wire dely ury RTL logi synthesis gtes Initil delys ple nd route tul delys not # (2:3:4, 4:5:6, 7:8:9) (nr, n) Simultor pli More urte, overriding vlues 7 8 Delys on Wires How do you drive wires? gte outputs n drive wires - gte outputs impliitely define wires wires n lso e defined with or without dely L M wire <size> <dely> nme; wire #5 LM; nd #6 (LM, L, M); not (MA, MB, LM); - The dely on wire is dded to ny dely in the gte(s) tht drive the wire Gte sees n input LM hnge time units fter hnge on L or M Model Evlution Gte evlution the design is mde up of primitive gtes nd ehviors we re only onsidering primitive gtes now Approh # Performing (A nnd B nnd ) is slow - espeilly in multi-vlued logi Use tle lookup tkes up memory, ut it s fst - Enode 0 s 00, s 0, x s 0, z s {A,B} Truth Tle result Truth Tle for Nnd 0000 0 000 0 000 0 00 0 000 0 00 00 00 0 0 0 000 0 00 0 00 0 0 0 00 0 0 0 0 0 0 A B Output 9 20 Pge 20