CS453 INTRODUCTION TO DATAFLOW ANALYSIS

Transcription

1 CS453 INTRODUCTION TO DATAFLOW ANALYSIS CS453 Leture Register llotion using liveness nlysis 1 Introdution to Dt-flow nlysis Lst Time Register llotion for expression trees nd lol nd prm vrs Tody Register llotion in GCC nd LLVM Control flow grphs 3-ddress ode Register llotion using liveness nlysis Reding for this week Ch 8 in online book These slides dpted from Clvin Lin nd E. Christopher Lewis. CS453 Leture Register llotion using liveness nlysis 2

2 Introdution to Dt-flow nlysis Previous leture: Register llotion for expression trees minimizing the register use. r1 r1 r2 r1 r2 r2 r3 r1 r2 r3 r4 To generte better ode (e.g. use fewer registers) we need to nlyze our progrms better 3-ddress ode Control flow nlysis nd ontrol flow grphs to determine dynmi hrteristis of the progrm Register llotion using liveness (live: still needed) nlysis CS453 Leture Register llotion using liveness nlysis 3 A Low-Level IR: 3-ddress ode We wnt to do nlysis on n Intermedite Representtion: 3-ddress ode Liner representtion: ssignments, lbels, (onditionl) jumps Typilly lnguge-independent nd nerly orresponds to mhine instrutions, differene: no stk ode, but (temporry) vribles There re nmed vribles (prmeters, vribles) nd temporries (expressions). We n nme the temporries ssuming unbounded number of (symboli) registers. Exmple opertions (Indexed) opy x = y[i], y[i] = x, x = z, t1 = t2 Unry / binry op x = op z, x = v op z, t1 = t2 op t3 Address of p = & v Dereferene x = *p, *p = x Pss prm prm t0 Cll t1 = ll f, 1 (onditinl) Brnh goto L1, if t1 goto L1 CS453 Leture Intermedite Representtions 4

3 Register Allotion in GCC nd LLVM Comprison between GCC nd LLVM Both used in ompiler reserh. GCC sine 1987, LLVM sine LLVM hs BSD-like liense nd GCC hs GPL liense. Both hve 3-ddress ode bsed IR (LLVM hs LLVM, GCC hs GIMPLE). Both rete stti single ssignment representtion for their 3-ddress ode intermedite representtion. GCC Register Allotion Lower GIMPLE into RTL (Register trnsfer lnguge) Regionl register llotor bsed on Chitin-Briggs (oloring pproh to register llotion tht is bsed on onept of live rnges) LLVM Register Allotion Fst (inside single bsi blok), Bsi, Greedy, PBQP All but Fst bsed on live rnges Show nd CS453 Leture Register llotion using liveness nlysis 5 Dt-flow Anlysis Ide Dt-flow nlysis derives informtion bout the dynmi behvior of progrm by only exmining the stti ode Exmple How mny registers do we need for the progrm on the right? Esy bound: the number of vribles used + expr temp (4) Better nswer is found by onsidering the dynmi requirements of the progrm 1 := 0 2 L1: b := := + b 4 := b * 2 5 if < 9 goto L1 6 return CS453 Leture Register llotion using liveness nlysis 6

4 Liveness Anlysis Definition A vrible is live t prtiulr point in the progrm if its vlue t tht point will be used in the future (ded, otherwise). To ompute liveness t given point, we need to look into the future Motivtion: Register Allotion A progrm ontins n unbounded number of vribles Must exeute on mhine with bounded number of registers Two vribles n use the sme register if they re never in use t the sme time (i.e, never simultneously live). Register llotion uses liveness informtion CS453 Leture Register llotion using liveness nlysis 7 Control Flow Grphs (CFGs) Definition A CFG is grph whose nodes represent progrm sttements nd whose direted edges represent ontrol flow Exmple 1 = 0 1 := 0 2 L1: b := := + b 4 := b * 2 5 if < 9 goto L1 6 return 6 return No b = + 1 = + b 4 = b * 2 <9 Yes CS453 Leture Register llotion using liveness nlysis 8

5 Terminology Flow Grph Terms A CFG node hs out-edges tht led to suessor nodes nd in-edges tht ome from predeessor nodes pred[n] is the set of ll predeessors of node n 1 su[n] is the set of ll suessors of node n = 0 Exmples Out-edges of node 5: su[5] = {2,6} pred[5] = {4} pred[2] = {1,5} (5 6) nd (5 2) b = + 1 = + b 4 = b * 2 <9 6 return No Yes CS453 Leture Register llotion using liveness nlysis 9 Liveness by Exmple Wht is the live rnge of b? Vrible b is red in sttement 4, so b is live on the (3 4) edge Sine sttement 3 does not ssign into b, b is lso live on the (2 3) edge Sttement 2 ssigns b, so ny vlue of b on the (1 2) nd (5 2) edges re not needed, so b is ded long these edges b s live rnge is (2 3 4) 6 return = 0 b = = b * 2 5 No = + b <9 Yes CS453 Leture Register llotion using liveness nlysis 10

6 Liveness by Exmple (ont) Live rnge of is live from (1 2) nd gin from (4 5 2) is ded from (2 3 4) 1 2 = 0 b = + 1 Live rnge of b b is live from (2 3 4) Live rnge of is live from (entry , 5 6) 6 return 3 4 = b * 2 5 No = + b <9 Vribles nd b re never simultneously live, so they n shre register Yes CS453 Leture Register llotion using liveness nlysis 11 Uses nd Defs Def (or definition) An ssignment of vlue to vrible def_node[v] = set of CFG nodes tht define vrible v def[n] = set of vribles tht re defined t node n = 0 Use A red of vrible s vlue use_node[v] = set of CFG nodes tht use vrible v use[n] = set of vribles tht re used t node n < 9? v live def_node[v] More preise definition of liveness A vrible v is live on CFG edge if use_node[v] (1) direted pth from tht edge to use of v (node in use_node[v]), nd (2) tht pth does not go through ny def of v (no nodes in def_node[v]) CS453 Leture Register llotion using liveness nlysis 12

7 The Flow of Liveness Dt-flow Liveness of vribles is property tht flows through the edges of the CFG Diretion of Flow Liveness flows bkwrds through the CFG, beuse the behvior t future nodes determines liveness t given node Consider Consider b Other properties flow forwrd 1 := b := + 1 := + b := b * 2 No 6 return < 9? Yes CS453 Leture Register llotion using liveness nlysis 13 Liveness t Nodes We hve liveness on edges How do we tlk bout liveness t nodes? = 0 edges progrm points just before omputtion just fter omputtion Two More Definitions A vrible is live-out t node if it is live on ny of tht node s out-edges n live-out out-edges A vrible is live-in t node if it is live on ny of tht node s in-edges n live-in in-edges CS453 Leture Register llotion using liveness nlysis 14

8 Computing Liveness Rules for omputing liveness (1) Generte liveness: If vrible is in use[n], it is live-in t node n Dt-flow equtions n live-in use (2) Push liveness ross edges: If vrible is live-in t node n then it is live-out t ll nodes in pred[n] live-out (3) Push liveness ross nodes: If vrible is live-out t node n nd not in def[n] then the vrible is lso live-in t n live-out n live-in n live-out live-in live-out pred[n] (1) in[n] = use[n] (out[n] def[n]) (3) out[n] = in[s] s su[n] (2) CS453 Leture Register llotion using liveness nlysis 15 Solving the Dt-flow Equtions Algorithm for eh node n in CFG in[n] = ; out[n] = repet for eh node n in CFG in [n] = in[n] out [n] = out[n] in[n] = use[n] (out[n] def[n]) out[n] = in[s] s su[n] until in [n]=in[n] nd out [n]=out[n] for ll n initilize solutions sve urrent results solve dt-flow equtions test for onvergene This is itertive dt-flow nlysis (for liveness nlysis) CS453 Leture Register llotion using liveness nlysis 16

9 Exmple node # 1 2 b 3 b 5 1st 2nd 3rd 4th 5th 6th 7th use def in out in out in out in out in out in out in out 4 b 6 b b b b b b b b b b b b b b b b b b b b b b b b b b 1 := 0 2 b := := + b 4 := b * 2 Dt-flow Equtions for Liveness in[n] = use[n] (out[n] def[n]) out[n] = in[s] s su[n] No 6 return 5 < 9? Yes CS453 Leture Register llotion using liveness nlysis 17 Liveness Anlysis in the MeggyJv ompiler Currently Prse into AST Allote spe on stk for lols nd prmeters nd spe in hep for member vribles Use stk for expression evlution Generte AVR ode from AST To perform dt-flow nlysis Need intermedite representtion like 3-ddress ode Use temporries/symboli registers for expression results Indite uses nd defs of temporries nd lols nd prmeters in eh 3- ddress ode instrution Crete ontrol-flow grph with eh 3-ddress ode instrution s node CS453 Leture Register llotion using liveness nlysis 18

10 A Low-Level IR: 3-ddress ode 3-ddress ode Liner representtion Typilly lnguge-independent nd nerly orresponds to mhine instrutions Eh vr is ssumed to hve bse + offset Assumes infinite temps (t#), or symboli registers, re vilble Exmple opertions Copy x = z, t1 = t2 Indexed opy x = y[i], y[i] = x, t1 = y[i] Unry op x = op z Binry op x = v op z, t1 = t2 op t3 Address of p = & v Lod x = *p Store *p = x, Pss prm prm t0 Cll t1 = ll f, 1 Brnh goto L1 Cbrnh if (x==y) goto L1 CS453 Leture Intermedite Representtions 19 Expression Exmple CS453 Leture Register llotion using liveness nlysis 20

11 Another MeggyJv Exmple int ; int b; int ; int d; int e; int [] v; int [] z; Foo r; = b + + (d+e); v[i] = z[i] * 3 + v.length; r.br(42); CS453 Leture Register llotion using liveness nlysis 21 MeggyJv Loop Exmple int ; int b; = 1; b = 0; while (<7) { = + 1; b = b + 3; } Meggy.setPixel((byte), (byte) b, Meggy.BLUE); CS453 Leture Register llotion using liveness nlysis 22

12 Register Allotion Problem Assign n unbounded number of symboli registers, or temporries, to fixed number of rhiteturl registers Simultneously live dt must be ssigned to different rhiteturl registers Gol Minimize overhed of essing dt Memory opertions (lods & stores) Register moves CS453 Leture Register llotion using liveness nlysis 23 Sope of Register Allotion Expression Lol Loop Globl Interproedurl CS453 Leture Register llotion using liveness nlysis 24

13 Grnulrity of Allotion Wht is lloted to registers? Vribles Live rnges/webs (i.e., du-hins with ommon uses) Vlues (i.e., definitions; sme s vribles with SSA) s 1 : x := 5 b 2 s 2 : y := x b 3 s 3 : x := y+1 b 4 b 1 s 6 :... x... s 4 :... x... s 5 : x := 3 Vribles: 2 (x & y) Live Rnges/Web: 3 (s 1 s 2,s 4 ; s 2 s 3 ; s 3,s 5 s 6 ) Vlues: 4 (s 1, s 2, s 3, s 5, φ (s 3,s 5 )) CS453 Leture Register llotion using liveness nlysis 25 Globl Register Allotion by Grph Coloring Ide [Coke 71], First llotor [Chitin 81] 1. Construt interferene grph G=(N,E) Represents notion of simultneously live Nodes re units of llotion (e.g., vribles, live rnges, vlues) edge (n 1,n 2 ) E if n 1 nd n 2 re simultneously live Symmetri (not reflexive nor trnsitive) 2. Find k-oloring of G (for k registers) Adjent nodes n t hve sme olor 3. Allote the sme register to ll llotion units of the sme olor Adjent nodes must be lloted to distint registers t2 t1 t3 CS453 Leture Register llotion using liveness nlysis 26

14 Interferene Grph Exmple (Vribles) :=... b :=... := d :=... := :=... e b e := e b... :=... d CS453 Leture Register llotion using liveness nlysis 27 Computing the Interferene Grph Use results of live vrible nlysis for eh symboli-register/temporry/vr t i do for eh symboli-register/temporry/vr t j (j < i) do for eh def {definitions of t i } do if (t j is live out t def) then E E (t i,t j ) Options tret ll instrutions the sme tret MOVE instrutions speil whih is better? CS453 Leture Register llotion using liveness nlysis 28

15 Alloting Registers Using the Interferene Grph K-oloring Color grph nodes using up to k olors Adjent nodes must hve different olors Alloting to k registers finding k-oloring of the interferene grph Adjent nodes must be lloted to distint registers But... Optiml grph oloring is NP-omplete Optiml register llotion is NP-omplete, too (must pproximte) Wht if we n t k-olor grph? (must spill) CS453 Leture Register llotion using liveness nlysis 29 Register Allotion: Spilling If we n t find k-oloring of the interferene grph Spill vribles (nodes) until the grph is olorble Choosing vribles to spill Choose rbitrrily or Choose lest frequently essed vribles Brek ties by hoosing nodes with the most onflits in the interferene grph Yes, these re heuristis! CS453 Leture Register llotion using liveness nlysis 30

16 Spilling (Originl CFG nd Interferene Grph) :=... b :=... := d :=... f := f :=... e b e := f e b... :=... f d CS453 Leture Register llotion using liveness nlysis 31 Spilling (After spilling b ) f :=... :=... b :=... *(Y+4) := b := d := f :=... e b e := f e... b = *(Y+4)... b... :=... f d CS453 Leture Register llotion using liveness nlysis 32

17 Simple Greedy Algorithm for Register Allotion for eh n N do { selet n in deresing order of weight } if n n be olored then do it { reserve register for n } else Remove n (nd its edges) from grph { llote n to stk (spill) } :=... r24 :=... *(Y+4):= r24 := d :=... (After spilling b ) e := f e... r24 = *(Y+4)... r24... CS453 Leture Register llotion using liveness nlysis 33 e f d Exmple Attempt to 3-olor this grph (,, ) e f b d Weighted order: b d f e Wht if you use different order? CS453 Leture Register llotion using liveness nlysis 34

18 Exmple Attempt to 2-olor this grph (, ) Weighted order: b b CS453 Leture Register llotion using liveness nlysis 35 Conepts Liveness Used in register llotion Generting liveness Flow nd diretion Dt-flow equtions nd nlysis 3-ddress ode nd Control flow grphs Register llotion sope of llotion grnulrity: wht is being lloted to register order tht llotion units re visited in mtters in ll heuristi lgorithms Globl pproh: greedy oloring CS453 Leture Register llotion using liveness nlysis 36

19 Liveness in the MiniJv ompiler CS453 Leture Register llotion using liveness nlysis 37