An Efficient Parallel Transparent Diagnostic BIST

An Efficient Parallel Transparent Diagnostic BIST D. C. Huang and W. B. Jone Department of CS & IE, National Chung-Cheng University, Taiwan, R.O.C. Abstract- In this paper, we propose a new transparent Built-In Self-Diagnosis ( BISD ) method to diagnose multiple embedded memory arrays with various sizes an parallel. A new tmnspamnt diagnostic interface has been proposed to perform testing in n m l mode. By tolerating redundant read/urite/shift operations, we develop a new mamh algorithm called TDiagRSMarch to achieve the ywls of low hardware overhead, lower test time, and hiyh test coverage. Experh"ea1 results demonstrate that the diagnostic eflciency of TDiagRSMamh is independent on mewry topology, defect-type distribution, and degree of pamllelism. Inda Words: Memory Test, Built-In Self-Diagnosis, II)ansparent diagnosis I. INTRODUCTION Because of the improvement of VLSI technologies, many components can be fabricated into a single chip. This induces various testing problems due to the inaccessibility of components; especially in memory modules, all transistors are so highly condensed that they are very vulnerable to fabrication defects. In general, some memory arrays are used to store some valuable data and the correctness of these also dominate the function of chip. For example in a superscalar CPU chip, the reorder buffer is a set of memory arrays used to control the execution order of instructions. Thus, the testing and diagnosis of memory buffers are very important. However, memory devices contained on a single chip might be defective during the normal operation. To resolve such a problem, an on-line repairing scheme is proposed. Thus, a more cost-efficient solution is to use transparent diagnosis by which memory devices on a chip is diagnosed periodically. The basic requirement of transparent diagnosis is that the memory contents must be restored to the initial state such that the normal operations can be resumed. Historically, several papers have discussed BISD and BISR of memory from different aspects[l][2][][4][5][6]. All these papers perform the diagnosis in an off-line mode. That is, the diagnosis of memory can not be performed in the normal operation mode. Thus, we need to stop the normal operation mode and to enter into the diagnostic mode. To test memory in normal mode, there are discussed in several papers [7][8][9][10][11][121 and a transparent testing concept has been proposed. In other words, the content of memory can be recovered to its original format after executing the testing. However, U U U Fig. 1. The serial interfacing technique for a memory array. these papers do not mention about the diagnostic issue. Most of these papers are related to the testing issue. In [1], a software method has been proposed to diagnose the memory in a transparent and a relocation scheme is also presented. Here, we develop an efficient method to concurrently diagnose and repair spatially distributed memory modules with different sizes. To save test data routing area, the serial interfacing technique is used. Also, a circular comparator is proposed to cope with the diagnosis and identscation of defective cell. Based on this test architecture, only a single test controller is required to sup port the BET and BISD functions for all memory modules. Further, only very limited number of test signals are required to be routed on the entire chip. After investigating the relationships between different fault types, a parallel diagnosis method called TDiagRSMarch is pre posed to generate test patterns and evaluate test output responses. The TDiagRSMarch algorithm guarantee the identification of all stuck-at, transition, coupling faults occurring at all memory modules. 11. BACKGROUND The serial interfacing technique shown in Figure 1 was proposed to test several embedded memory arrays using a BIST technique in which only two serial scan data signals are required for each memory module to access the memory contents [14]. Thus, considerable routing area can be saved. This technique is very useful for memory testing when many buffers are spaciously distributed on the entire chip. The basic idea of the serial interfacing technique is to synthesize the 1/0 port of each buffer as a scan chain where the test patterns can be provided and memory contents can be read (Figure 1). Based on 1081-775/00 $10.00 0 2000 IEEE 299

Fig. 2. A diagnostic serial interface. this test architecture, the SMarch algorithm is used to generate test patterns and to evaluate test responses for each memory array [14]. In [15], we proposed an efficient parallel BIST method called RSMarch to test a set of spatially distributed memory modules with various Sizes. The major component of each small buffer is the memory cell array which is generally implemented using SRAM. Thus, an appropriate memory cell array fault model must be used to deal with the SRAM faults [16]. Now, we give detailed explanations about the memory fault model used in this work. 1. Stuck-at fault (SAF): The logic value of a memory cell is always stuck-at 1 (SA1) or 0 (SAO). 2. Transition Fault (TF): A cell fails to undergo a 0-1 transition (TF O+l) and/or a 1+0 transition (TF 1-0).. Coupling Fault (CF): In this case, a write operation in one cell i can influence the value of another cell j, and cell i is called the coupling cell whereas cell j is called the coupled cell. As in [16], three types of coupling faults are considered below: State coupling fault (CFst): A coupled cell is forced to a certain value 5 if the coupling cell is in a given state Y. Indempotent coupling fault (CFid): A 0+1 and/or 1-0 transition in the coupling cell forces a certain value in the coupled cell. e Inversion coupling fault (CFin): A 0-1 and/or 1+0 transition in the coupling cell inverts the content of the coupled cell. 111. A NEW DIAGNOSTIC SERIAL INTERFACE AND ALGORITHM A. A New Diagnostic Serial Interface A new diagnostic serial interface has been proposed in our research to diagnose multiple embedded memories in r an on-line and parallel manner. In Figure 2, we propose a serial interface consisting of three parts: (1) test pattern scheme, (2) parallel testing scheme and () identification scheme. As mentioned above, we have SAF, TF and CF needed to be diagnosed. Hence, each cell must be toggled and different coupling excitation must be sensitized. To provide a test pattern having 1+0, 041, "0101...?-"lo10..." and "lolo..."+" OlOl...", we select Q or /Q as test pattern by switching the input of mu y. Thus, a SAF, TF and CF cm be sensitized and tested. Further, we also need to shift the tested result out. However, this will result in the changed content of memory if we adopt the traditional serial interface shown in the Figure 1 and this leads to the content of memory cannot be recovered to its original data after diagnosing. Thus, we propose a circular chain to latch and shift the tested result out. Based on this scheme, the content of current tested word cannot be changed and can be used as an excitation data to perform the test. To diagnose the faulty cell of various sizes of memory buffers, we propose a circular comparator to identify these faulty cells in a parallel manner. The basic concept of this circular comparator is that all tested result will be stored in the circular comparator without any overriding because of circular rotating. However, the location of each cell Iocated on the circular comparator might be different due to different widths. Conceptually, we illustrate an example as shown in the Figure (a) and we only take the M1 and M2 for convenience, In Figure (a), if the tested word ( i.e., middle word ) is "1001" after performing the M1 (i.e., /ai) and the data "1001" will be read out and be shifted into the Buffer A. Similarly, the tested word will become as "0110" after executing the M2 (i.e., ai) and the data will be stored into the Buffer B. Thus, the errorneous cells can be identified if there exist a "0" in the comparator, that is, the result is not identical to /ai XOR ai (i.e., "1" ) since there exist some errors. In other words, we can identify the defective cells by comparing the output data between every two successive marches (M1 to M7). Meanwhile, the benefit of this method is that only two buffers are required for each memory module and this leads an amount of hardware saved. Also, every comparing result can be predicated since the value of correct data are predictable. Here, we assume there do not exist two more faults for each cell, thus the fault masking effect will not occur while we compare two data of related bit from the two successive marches. In order to resolve the parallel diagnosis, we adopt a circular comparator as shown in the Figure (b) ( dash line ). That is, we are able to diagnose multiple memory with different width in parallel. In Figure (a) 00

MI MI Q m) Fig.. An idendify scheme and a circular comparator while performing a parallel diagnosis. Fig. 5. A seven march TDiagRSMarch algorithm. Teed ETOUT) -moly word /i'............... -1 i-... Fig. 4. A diagnostic group having three words. and (b), we have two memory width of 4 bits and bits accordingly. Clearly, we will shift the tested word out for four times since the maximum width is "4". However, one more shift operation is required for the smaller size one and the result on the most right side will be shifted out and this result in one result lost. This can be solved via a circular comparator. In Figure (b), we can shift the data from the latch for four times and the result in the Buffer C is "101" since the most right bit (i.e., 1) will rotate and shift into the most left bit of the Buffer C. Similarly, we can get the data of "010" from the Buffer D. B. Parallel 1ansparent Diagnostic March Algorithm B.l Basic Concept As previous section mentioned, we can identify the faulty cells by comparing the current tested word with the previous tested word. However, it might require many memory buffers to store the reference data. Here, we apply a method in which can perform the comparison for each word simultaneously and this has the advantage of saving memory, and the fault coverage still can be maintained. To achieve this, we adopt three words as an unit for each march operations as shown in Figure 4. In Figure 4, we can divide the memory into five tested group. The basic concept is to ensure that a test pattern can be sensitized for each cell and we only consider the neighbor cells surrounding a tested cell in realistic. Hence, we collect three words as a tested group and we perform all march operations on these three words un- til all words in memory have been diagnosed. Clearly, we only need to shift out the middle word because the middle word is surrounded by the other two words, and all excitations from other words and within the tested word can be sensitized after accomplishing all march o p erations on these three words. In Figure 4, the first word can be diagnosed after the first tested group has been diagnosed; similarly, the second to fifth word can be diagnosed after the second tested group to fifth tested group have been diagnosed. Because of reading the middle word in each operation, we should have a special method to deal with the first and last word. That is, we start from the position "-1" which is ahead one position for the first word; likewise, we stop on the position "6" which is over one position for the last word. Therefore, every word has the chance to be the middle word (i.e., read out ) and the designed diagnostic circuit can be regularity and simplicity. B.2 Diagnostic Algorithm To drive the new serial interface, we have proposed a new parallel diagnostic algorithm and it can diagnose multiple memories in parallel. The new diagnostic algorithm consists of seven march elements as shown in Figure 5. The march element includes read/shift part and test pattern generation part (i.e. read/ write) for the middle tested word. In contrast, the read/shift part will not be required for the other two words because only the middle word to be read for veri6cation. The read/shift operation is used to verify the correctness of tested word and it will not change the data in the memory. Here, we illustrate an example and have two memory buffers with size of 4x5 and 6x5 (i.e., width x length) to be diagnosed. The r(ai)w(/ai) operations are used to sensitize the coupling fault between word 1, 2,, 4 and 5, accordingly. Also, the operations r(ai)s(ai) are used to read and move out the result for the middle word (i.e. word j+l). The buffer A will induce two redundant operations for the middle word due to smaller width (i.e. ai)^-*). The redundant operation will not have any influence on the 01

memory content because the shift operation occurring on the shifter. Also, the operation r(ai)s(ai) is used to verify the correctness of the word 1. Thus, the word 1 can be verified thoroughly by performing the M1 to M7. Similarly, the word 2,, 4 and 5 can be verified while j varies from 1 to 4. In general, the j varies from -1 to n-1 and this results in that all words (i.e. word 1 to n) can be verified successively. In RSMarch, besides horizontally redundant operations, vertically redundant operations are allowed for memory arrays with smaller word numbers to simplify the test control design. But, vertically redundant operations must be avoided in TDiagRSMarch because of the disparity between both march methods. In RSMarch, the vertically redundant operations do not change the memory contents for memory arrays which are excessively tested. Thus, there is no side-effect existent and this good property can be used to save test hardware. However, the w(/ai) operations in TDiagRSMarch will cause trouble if they are excessively applied to shallow memory arrays. For example, if vertically redundant o p erations are allowed to be applied to memory array A, then the first round of vertically redundant operations will complement the entire memory contents back to the original values. Further, the second round of vertically redundant operations will drive part of array A complemented while part of A uncomplemented. Thus, this side-effect makes the test pattern generation process extremely diflicult to control. Fortunately, this problem can be easily solved by terminating the march operations temporarily, every time when a shallow memory array has been completely scanned by a specific march element. Thus, the testing of shallow arrays will be terminated until the deepest memory array finishes the current march element. The terminating circuit can be easily designed by using the selection line of the last word in each shallow memory array. Conceptually, the middle word of each tested group is the word under diagnosis. For a fault between different word we will generate a test pattern from the upper or lower word of the tested group. Thus, the influenced result will be left in the middle word and this result can be verified via the operation of r(ai)s(ai), where the r and s denote the read and shift, respectively. For example in the Figure 6, we select the word 0,l and 2 as a tested group and the word 1 ( middle word ) is selected as a tested word. Thus, for the M1, we perform the r(ai)w(/ai) for the word 0 and then execute the r(ai)s(ai) for the word 1. After that, the content of word 0 will become to 110 and the original data of word 1 (i.e., 101) will be read into the latch and then shift the latched data into comparator. Finally, the value of *** Or&?.i.il ; 2 M ( p B WI 0 0 M4 ( 9 M5 ( p Fig. 6. A transparent diagnostic example. M6( p Em El 0 0 H word 1 become to 010 due to perform the r(ai)w(/ai) operation. Next, we perform r(ai)w(/ai) for the word 2 and we have found that 001 left in the word 2 after performing the M1. Similarly, we will perform the M2 to M7 for the word 0, 1 and 2 repeatedly. Moreover, we know the M1 to M4 is used to diagnose the fault between different words. To diagnose a fault within a word, we will perform M5 to M7 and we have to ensure that the pattern of OO, 01, 10 and 11 can be existing for any two neighbor cells. Clearly in the TDiagRSMarch, a CFst fault can be diagnosed by the pattern of di, where the di represents the data with format of Q/QQ and the Q means the data in the memory currently. Thus, the word 1 will become to 111 after the M5 since the we perform r(ai)s(ai) and r(ai)w(di) and the di is the format of Q/QQ, that is, 101 ( i.e. the word 1 in the M4 ) to 111 ( the word 1 after performing the M5). Iv. EXPERIMENTAL RESULTS In this section, we will perform some experiments to demonstrate the seven march TDiagRSMarch algorithm. To evaluate this experiment, we have three configurations proposed here to emulate some memory structures such as Configuration 1 consists of three memory modules: A (120x40), B (50x70), and C (45~55)~ where notation (U x v) represents that the memory array has U words while each word contains v bits. Configuration 2 consists of memory arrays: D (2x70), E (5Ox56), and F (120x4). Moreover, there are five memory modules: G (2x70), H (5Ox56), I (120~4)~ J (45x2), and K (65x4) for configuration. First, we assume there are 5 % cells defective without loss of generality. Further, we assumed that five different fault types (SAF, TF, CFst, CFid, and CFin) can occur in the memory arrays. Each time, we randomly injected one fault into one 02

memory module of each configuration and then used TDiagRSMarch to diagnose the fault. The simulation process was repeated for 1000 times for each fault type and the results are shown in Figure 7. From the diagnostic statistics, it can be found that SAF, TF and CFst can be completely detected. However, the fault coverage for CFid and CFin is about 60%. The reason is due to the fact that TDiagRSMarch is a word-based diagnostic method, and many coupling faults occurring in the same word cannot be detected. Fortunately, in the case of write-dominating coupling effects, CFid and CFin disappear so both can be treated as detected as shown in Figure 7; the required numbers of read operations, write operations, and shift operations for each execution of TDiagRSMarch are also presented. In fact, the numbers are exactly those required for each memory configuration when it is physically tested on the chip. Here, we require 104 read operations, 2266 write operations and 840 shift operations for each configuration. Clearly, the diagnostic time is dependent only on the maximum width and the maximum length among all memory modules in each configuration because of parallel testing. The advantage of our method will be more obvious while the number of memory modules contained in one memory configuration increases. In Figure 7, we show two results for each memory configuration for the purpose of avoiding the statistical bias. For the writing dominate, we know the CFid and CFin occurring in the same word can be considered diagnosed. V. CONCLUSIONS In this paper, we have developed an efficient and online method to diagnose the defects for memory arrays which are spatially distributed on the chip. To reduce the test data routing area, the serial interfacing technique has been used to test all memory arrays simultaneously. An efficient diagnosis algorithm, called TDiagRSMarch, has been proposed to generate test patterns and to identify the faulty cells. Instead of using MIS&, the test outputs are evaluated using a circular comparators. Based on the circular comparator, we are able to identify the faulty cell without any overriding and thus the multiple memmy arrays can be diagnosed in parallel. Finally, we emphasize that the proposed method is mainly applied to buffers spatially distributed on the chip. REFERENCES [l] M. F. Chang, W. K. Fuchs and J. H. Patel, Diagnosis and Repair of Memory with Coupling Faults, IEEE Trans. on [2] [] Computers, vol. 8, no. 4, pp. 49-499, April 1989. P. Mazumder and J. S. Yih, A Novel Built-In Self-Repair Approach to VLSI Memory Yield Enhancement, IEEE, Proc. of Int 1 Test Conf., pp. 8-841, 1990. A. Tanabe et d., A 0ns 64-Mb DRAM with Built-In Self- Fig. 7. Fault coverage and diagnostic time for each fault type. Test and Self-Repair Function, IEEE J. Solid-State Circuits, vol. 27, pp, 1525-151, Nov. 1992. T. Chen and G. Sunada, A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories, IEEE, Proc. of Int l Test Conf., pp. 62-61, 1992. R. Treuer and V. K. Agrarwal, Built-In Self-Diagnosis for Repairable Embedded RAMs, IEEE Design and Test of Computers, pp. 24-, June 199. I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. Higgins, and J. Lewandowski, Built-In Self-Repair for Embedded High Density SRAM,. IEEE, Proc. of Int l Test Conf., pp. 1112-1119, 1998. B. Koeneman, DFT Workshop, Vail, Colorado, April, 1986. M. Nicolaidis, TRansparent BIST for RAMs, IEEE, Proc. of Int l Test Conf., pp. 598-607, 1992. M. Nicolaidis, Theory of Transparent BIST for RAMs, IEEE Trans. on Computers, vol. 45 no. 10, pp. 1141-1156, Oct., 1996. Karpovsky, M. G. and Yarmolik, V. N. Transparent memory BIST, Memory Technology, Design and Testing, records of IEEE International Workshop, 1994, pp. 106-111. B. F. Cockburn and Y. -F. N. Sat, Synthesized transparent BIST for detecing scrambled pattern-sensitive faults in RAMs IEEE, Proc. of Int l Test Conf., pp. 2-2, 1996. V. N. Yarmolik, S. Hellebrand, and H. -J. Wunderlich, Symmetric Transparent BIST for RAMS. Proceeding of IEEE Design, Automation and Test in Europe, pp. 702-707, 1999. Janusz Sosnowski, In System Transparent Autodiagnostics of RAMs.IEEE, Proc. of Int l Test Conf., pp.85-844, 199. B. Nadeau Dostie, A. Silburt and V. K. Agarawal, Serial Interfacing Technique for Embedded Memory Testing, IEEE Design and Test of Computers, pp. 52-6, April 1990. W. B. Jone, D. C. Huang, S.C. Wu and K. J. Lee An Efficient BIST Metho for Small Buffers, IEEE, Proc. of Int l VTS, pp. 246-251, 1999. A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley and Sons, New York, NY. 1991. 0