Engineer-to-Engineer Note EE-272 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t processor.support@nlog.com nd dsptools.support@nlog.com Or visit our on-line resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors Contributed by Mnik Arypdi Rev 1 July 11, 2005 Introduction This ppliction note describes how to mnge the booting of multiple executbles from externl memory t run-time, thus providing the flexibility to dynmiclly switch mong them. This project ws implemented on the ADSP- BF561 EZ-KIT Lite evlution system (ADDS-BF561-EZLITE, Rev 1.1) nd pplies to the ADSP-BF561 Blckfin processors with silicon revision 0.2 nd beyond. The softwre code ccompnying this project ws tested using VisulDSP++ 4.0 tools. Synopsis This ppliction note ddresses the following topics: The ADSP-BF561 Blckfin processor booting process Multi-ppliction (multi-dxe) mngement for the ADSP-BF561 Blckfin processors Reconfiguring the C/C++ run-time heder Second-stge loder (SSL) memory mngement Booting multiple DXE files from 16-bit flsh memory nd swpping them t run time without hving to reset ADSP-BF561 Booting Mechnism The ADSP-BF561 Blckfin processor consists of multiprocessor configurtion feturing two Blckfin cores. Since the core rchitectures of the ADSP-BF561 processor nd the ADSP- BF533 processor re like, there re no significnt differences in the booting mechnism between the two devices. The booting process of the ADSP-BF533 processor is documented in ADSP-BF533 Blckfin Booting Process (EE-240) [1] ; therefore, only those detils unique to the ADSP-BF561 processor re detiled in this ppliction note. Boot modes supported on vrious silicon revisions nd the pproprite jumper nd DIP switch settings for ech re elucidted in the Appendix. The ADSP-BF561 Blckfin processor hs two cores: core A nd core B. After reset, the on-chip Boot ROM, which is locted t 0xEF00 0000, is executed. The first step in creting the boot code involves compiling nd linking the ppliction code into n executble file. The elfloder utility then converts the executble into boot strem file (.LDR), which is then burned into flsh or nother externl memory device (e.g., PROM, EEPROM, etc.). After reset, the Boot ROM reds the boot strem file from n externl memory device, prsing the heders nd moving blocks of dt to specified memory loctions. After the blocks re loded, Copyright 2005, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.
the Boot ROM jumps to the strt of core A s L1 instruction SRAM (0xFFA0 0000) nd executes the code. This procedure is summrized in Figure 1. Source Files.ASM,.C,.CPP Assembler nd/or Compiler.DOJ(s) Linker.DXE(s) Loder.LDR Trget System ADSP-BF561 Processor Externl Memory Figure 1. ADSP-BF561 Booting Sequence Multi-Executble Mngement The ADSP-BF561 processor ppliction cretes two executble files (p0.dxe nd p1.dxe), one for core A nd one for core B, respectively. the SSL switch -l user kernel in the commnd line option or by chnging the Lod:Kernel pge settings in the Project Options dilog box. To fcilitte multi-dxe loding, the executble files must be included in the Additionl options box in the Lod:Kernel pge settings. The executbles re loded in the order specified in the commnd line. Figure 3. Additionl Options in the Lod:Kernel Pge Figure 2. Kernel Options for ADSP-BF561 Processor At ny given instnce, the Boot ROM cn lod only single executble before it jumps to the strt of core A s L1 instruction SRAM. In order to lod two or more executbles, second-stge loder (SSL) must be incorported. The SSL is used for pre-boot initiliztion nd multi-dxe mngement. The defult SSL, locted in the \ldr directory of the VisulDSP++ 4.0 tools suite, cn be selected. Alterntively, customized kernel cn be utilized by invoking Booting The into core A scrtchpd memory (0xFFB0 0000 0xFFB0 0FFF) nd core B scrtchpd memory (0xFF70 0000 0xFF70 0FFF) is not supported by the processor Boot ROM..LDF file cn be modified to combine both cores into single executble. This is not recommended for projects tht utilize shred memory or use the C/C++ run-time heders. Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 2 of 11
The lst 1024 bytes of L2 memory re llocted to the SSL by defult. This prt of memory must be reserved while in the booting mode. Loder Opertions The loder utility converts the executble into boot-lodble formt (.LDR) tht is redble by the processor Boot ROM. It lso configures the output.ldr file ccording to user-specified boot formt (Intel hex-32, binry, ASCII) nd output width (8- or 16-bit). The loder utility is run by chnging the project type from n executble to loder file in the Project Options dilog box. Figure 6. Output File on the Lod:Options Pge ADSP-BF561 processors nd ADSP-BF533 processors shre the sme loder file structure. Refer to EE-240 for detiled description of the loder file structure. The ADSP-BF561 boot strem begins with 4-byte globl heder tht contins informtion bout the externl memory device nd signture tht prevents the Boot ROM from reding blnk device. The ADSP-BF533 processor s boot strem does not contin globl heder. Figure 4. Project options for ADSP-BF561 processors In order to ensure tht the boot strem file (.LDR) incorportes the SSL s well s the individul executbles, the elfloder commnd-line option in the Post-Build pge of the Project Options dilog box must be used. For further instructions regrding how to use the elfloder commnd-line option, refer to the VisulDSP++ 4.0 Loder Mnul [2]. Figure 5. ADSP-BF561 Post-build Pge The file nme nd destintion of the loder file must lso be specified in the Lod:Options pge settings. Flsh Progrmmer Utility After the loder file is built, it cn then be progrmmed into flsh memory using the flsh progrmmer utility. Perform the following steps to burn the loder file into flsh: 1) In VisulDSP++ 4.0, choose Tools->Flsh Progrmmer to ctivte the flsh progrmmer utility. 2) Select the flsh progrmmer driver from the defult loction: C:\Progrm Files\Anlog Devices\ VisulDSP 4.0\ Blckfin\Flsh Progrmmer Drivers\ADSP-BF561 EZ-Kit Lite\BF561EzFlsh.DXE 3) After the driver hs been loded (sttus indictor turns green), the loder file present t the specified loction is loded into flsh nd verified. For more detils on flsh-bsed pplictions, plese refer to Running Progrms from Flsh on ADSP-BF533 Blckfin Processors (EE-239) [3]. The reminder of the ppliction note discusses how to switch between two or more executbles t runtime. Tsks include modifying the C/C++ run-time heder nd plcing memory sections Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 3 of 11
into specific loctions using the Expert Linker. The softwre code ccompnying the project consists of the SSL nd two progrms tht scroll different sets of LEDs. 1 st Boot Strem 2 nd Boot Strem 3 rd Boot Strem 4-Byte Globl Heder 10-Byte Count Heder 4-Byte Next DXE Pointer Second Stge Loder (SSL) 10-Byte Count Heder 4-Byte Next DXE Pointer 1 st DXE Appliction 10-Byte Count Heder 4-Byte Next DXE Pointer 2 nd DXE Appliction ADSP-BF561 only 10-Byte Heder Block 1 10-Byte Heder Block 2 10-Byte Heder Block 3.. Loder File Figure 7. ADSP-BF561 Multi-DXE Loder File Structure Figure 8. Flsh Progrmmer Utility Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 4 of 11
Reconfiguring the C/C++ Run- Time Heder Attched to this EE-Note is multi-dxe boot exmple (see ssocited ZIP file). The ZIP file contins n SSL project nd two LED scroll ppliction projects. Upon RESET, the on-chip Boot ROM boots in the SSL. The SSL then wits until PF5 (SW6 push button) or PF6 (SW7 push button) re sserted. If PF5 is sserted, the first executble tht scrolls LEDs 13-20 is booted in. If PF6 is sserted, the SSL skips the first executble nd boots in the second executble, which scrolls on LEDs 5-12. Either of these executbles cn then be booted into the device, without resetting, by pressing the push-button switches. The 561_prom16 directory (in the ZIP file) consists of two sub-directories, blink_lower nd blink_upper, which contin the subprojects. Before the SSL is built, ech of these sub-projects must be built. These sub-directories contin project groups BF561_Blink1.dpg (to scroll LEDs 13-20) nd BF561_Blink2.dpg (to scroll LEDs 5-12). When the project groups re compiled nd built, they yield four executbles (p0.dxe nd p1.dxe for blink_lower nd p0.dxe nd p1.dxe for blink_upper). The C/C++ run-time heder (CRT) hs been included in ech of these projects. The CRT is used in projects tht re coded in the C/C++ progrmming lnguge nd, mong other tsks, initilizes stndrd librries such s stdio (stndrd input/output). Another of the primry functions of the CRT is to cll _min upon completion of execution. In ddition, the CRT lso sets up defult event hndlers, enbles interrupts, nd sets reserved registers to known vlues. For more detils on the CRT, refer to Configuring the C/C++ Run-Time Heder for Blckfin Processors-(EE-238) [4]. The CRT must be included in ech of the subprojects (tht generte the executbles) s prt of core A nd core B, s shown in Figure 9. Figure 9. CRT File Inclusion in the Sub-Project The Reconfigurtion Process By defult, the CRT sets ll the interrupt vector ddresses (except the supervisor mode interrupt, IVG15) locted in the Event Vector Tble (EVT) to generic hndler s ddress. For the purposes of booting executbles dynmiclly, this behvior compromises the vector ddress mpped to the flg interrupt used to switch pplictions. If the CRT overwrites the vlue ssigned to the selected interrupt (IVG11) with the generic hndler s ddress, it results in subsequent button-pushes vectoring to the defult hndler insted of the hndler instlled in the originl ppliction. To work round this, the bsiccrt.s file must be dded to ech of the sub-projects nd modified. Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 5 of 11
// Initilize the Event Vector tble. P0.H = IVBh; P0.L = IVBl; // Instll unknown_exception_occurred in EVT so tht // there is defined behvior. P0 += 2*4; // Skip Emultion nd Reset // P1 = 13; R1.L = unknown_exception_occurred; R1.H = unknown_exception_occurred;.ivt2: [P0++] = R1;.ivt3: [P0++] = R1;.ivt4: [P0++] = R1;.ivt5: [P0++] = R1;.ivt6: [P0++] = R1;.ivt7: [P0++] = R1;.ivt8: [P0++] = R1;.ivt9: [P0++] = R1;.ivt10: [P0++] = R1; //.ivt11: [P0++] = R1; // Not needed for mintining IVG 11 P0+=4; // Skipping IVG 11.ivt12: [P0++] = R1;.ivt13: [P0++] = R1;.ivt14: [P0++] = R1; Listing 1. EVT Modifiction in the bsiccrt.s File As noted in Listing 1, commenting out the code tht overwrites IVG11 nd, insted, skipping to IVG12 solves this problem nd mintins the originl vector ddress for IVG11. Additionlly, s shown in Listing 2, the IMASK register must lso be mnully preserved. By defult, the CRT enbles only the Supervisor mode interrupt (IVG15). For this ppliction, the IVG11 interrupt must lso remin enbled before clling _min (ppliction progrm). Since no reset event is tking plce, the System Interrupt Controller register context will be preserved through the executble switch. The core s IMASK register nd the EVTx registers, on the other hnd, re written by the CRT, nd thus, must be preserved. The steps shown in Listing 1 nd Listing 2 gurntee tht the processor s Core Event Controller register context is lso preserved. // At long lst, cll the ppliction progrm. cli r0; //disble interrupts bitset (r0,11); //copying the contents of IVG11 into r0 (user specified register) sti r0; //restoring the previous stte of the interrupt system CALL.X _min; Listing 2. Disbling nd Re-enbling Interrupts in the bsiccrt.s File SSL Memory Mngement The 561_prom directory contins the project group bf561_prom16.dpg, which consists of bf561_prom16.dsp (contining the min SSL code) nd cmds.c. Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 6 of 11
cmds.c is used to pss n rgument to the SSL. Since C file is included in the project, the C Appliction Binry Interfce (ABI) must be dhered to nd globl dt must be declred nd initilized ccording to C/C++ stndrds. cmds.c enbles prticulr.dxe file to be loded without specifying its ddress. The SSL will index into the boot strem to find the specified.dxe file. The cmds.c module lso gives the user the flexibility to lod, execute, nd switch.dxe files in prticulr order. The next step involves building the SSL nd creting the loder file with the multiple executbles (built in the previous step). This procedure is described on pge 2. Before building the SSL, the vrious sections need to plced into pproprite memory loctions. None of the executbles should hve ccess to these loctions nd, t the sme time, cores A nd B should be ble to ccess this prt of memory. This cn be ccomplished by reconfiguring the Linker Description File (.LDF) of ech of the executbles by using the Expert Linker to ensure tht there is no memory conflict with the SSL. As noted in Listing 3, L2 shred memory fulfills both these criteri nd, therefore, the interrupt sections in the cmds.c file were plced into this memory spce. #include <cdefbf561.h> #include <sysreg.h> #include <ccblkfn.h> #include <sys/exception.h> void loder_commnds(void); extern int SECOND_STAGE_LOADER(int, int); void Init_Interrupts_A(void); EX_INTERRUPT_HANDLER(A_ISR); /* plcing the Interrupts in L2 Shred memory */ /* plese note tht the following progrms re running on single core-core A */ section ("l2_shred") EX_INTERRUPT_HANDLER(A_ISR) { if(*pfio0_flag_c & 0x0020) //SW 5 is pressed { SECOND_STAGE_LOADER(0, 1);//(0-> indictes lod executble, 1-> DXE number) SECOND_STAGE_LOADER(1, 0);//(1-> execute the DXE) } else if(*pfio0_flag_c & 0x0040) //SW 6 is pressed { SECOND_STAGE_LOADER(0, 2);//lod the 2nd DXE in the boot strem SECOND_STAGE_LOADER(1, 0);//execute the 2nd DXE } } // end section ("l2_shred") void loder_commnds() { *pfio0_dir = 0x0000; *pfio0_inen = 0x01E0; *pfio0_maska_d = 0x01E0; Init_Interrupts_A(); Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 7 of 11
} while(1); section ("l2_shred") void Init_Interrupts_A(void) { *psica_imask1 = SIC_MASK(15); register_hndler(ik_ivg11, A_ISR); } Listing 3. cmds.c Source File Reconfiguring the SSL.LDF File After the sections of the cmds.c module hve been plced into L2 SRAM, the sme must be done for the bf561_prom16.dsp file. This file contins the min SSL code, consisting of two min sections (see Listing 4). The SSL must lwys strt in L1 memory of core A (0xFFA0 0000), hence jump to the min progrm is plced t 0xFFA0 0000 to execute the code from nother destintion in memory. Therefore, the JMP_LDR section needs to be plced t the top of core A s L1 memory. The SEG_LDR section is lso plced t loction in L2 SRAM for resons outlined bove. The Expert Linker cn be used to view nd modify the.ldf source file to plce the pproprite sections in memory. #define HederBuffer GPStorge -12.extern _loder_commnds; // The 2nd stge boot loder must strt in Core A L1 // A jump to the progrm is plced t FFA00000, so we my execute in L2..section JMP_LDR; P0.L = START_OF_LOADER; P0.H = START_OF_LOADER; JUMP (P0); /////////////////////////////////////////////////////////////////////////////////.section SEG_LDR; MEM_DMA: // R0 = source ddress // R1 = destintion ddress // R2 = count // R3 = source config // R4 = dest config // modify registers hve lredy been set up Listing 4. bf561_prom16.dsp Source File The Expert Linker is powerful utility tht llows you to plce sections into memory grphiclly by drgging nd dropping the specified section. The SECTIONS {} commnd cn lso be used to plce the specified sections by mnully modifying the source file. For more Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 8 of 11
detils on the syntx, refer to the description of LDF commnds in the VisulDSP++4.0 Linker nd Utilities Mnul [5]. After incorporting the chnges detiled bove, compile nd execute the project group fter loding the desired executbles. Appendix: Boot Modes Supported on Silicon Revisions Silicon Revision 0.2 Silicon revision 0.2 supports true 16-bit flsh/prom mode. BMODE[2:0] Description 000 Reserved. Executes from externl 16-bit memory connected to ASYNC Bnk0 ( Bypss mode ) 001 Boot from 8/16-bit flsh/prom 010 Boot from 8-bit ddressble SPI0 seril EEPROM in SPI Mster mode 011 Boot from 16-bit ddressble SPI0 seril EEPROM in SPI Mster mode Tble 1. Silicon Revision 0.2 Boot Modes Silicon Revision 0.3 Silicon revision 0.3 introduced SPI slve booting. BMODE[2:0] Description 000 Bypss 001 Boot from 8/16-bit flsh/prom 010 Boot from n SPI host in SPI Slve mode 1 011 Boot from 16-bit ddressble SPI0 seril EEPROM in SPI Mster mode Tble 2. Silicon Revision 0.3 Boot Modes 1 In silicon revision 0.3, the 8-bit SPI ws replced with slve SPI mode, but it ws non-functionl due to n nomly; therefore, only silicon revision 0.3 supports 16-bit SPI nd 8/16 flsh. Silicon Revision 0.4 BMODE[2:0] Description 000 Bypss 001 Boot from 8/16-bit flsh/prom 010 Boot from n SPI host in SPI Slve mode 2 011 Boot from 16-bit ddressble SPI0 seril EEPROM in SPI Mster mode Tble 3. Silicon Revision 0.4 Boot Modes 2 Silicon revision 0.4 includes support for slve SPI booting, nd the bug tht ws found in rev 0.3 ws fixed; therefore, silicon revision 0.4 supports slve SPI booting, 16-bit SPI nd 8/16 flsh prt from bypss mode. Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 9 of 11
Appendix: Jumper nd DIP Switch Settings This section describes jumper nd DIP switch settings on the ADSP-BF561 EZ-KIT Lite evlution system. The softwre code ccompnying this ppliction note will run successfully only if these settings re implemented. Figure 10. DIP Switch Loctions on the ADSP-BF561 EZ-KIT Lite Evlution System As observed in Figure 10, the switch settings control different modes of opertion for push buttons, video configurtions, nd PPI clock selections. There is no need to chnge ny of the defult settings for these switches; however, you must modify SW3, which controls the boot mode settings to ccommodte this project. Boot Mode Reserved Flsh memory 8-bit SPI PROM 16-bit SPI PROM Position OFF ON ON ON or OFF Tble 4. Boot Mode Select Switches for Current Project. Positions 1 nd 2 set the boot mode, wheres position 3 sets the processor s PLL in bypss mode, which is essentil for this project. Position 4 cn be ON or OFF, s it does not ffect the functionlity of the softwre. Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 10 of 11
References [1] ADSP-BF533 Blckfin Booting Process (EE-240) Rev 3.0, Jnury 2005. Anlog Devices, Inc. [2] VisulDSP++ 4.0 Loder Mnul. Rev 1.0, Jnury 2005. Anlog Devices, Inc. [3] Running Progrms from Flsh on ADSP-BF533 Blckfin Processors (EE-239). Rev 1, My 2004. Anlog Devices Inc. [4] Configuring the C/C++ Run-time heder for Blckfin Processors (EE-238). Rev 1, My 2004. Anlog Devices Inc. [5] VisulDSP++ 4.0 Linker nd Utilities Mnul. Rev 1.0, Jnury 2005. Anlog Devices, Inc. Document History Revision Rev 1 July 11, 2005 by M.Arypdi nd J. Beuchemin Description Initil Relese Mnging Multiple DXEs on ADSP-BF561 Blckfin Processors (EE-272) Pge 11 of 11