Elettronica T moduli I e II Docenti: Massimo Lanzoni, Igor Loi Massimo.lanzoni@unibo.it igor.loi@unibo.it A.A. 2015/2016
Scheduling MOD 1 (Prof. Loi) Weeks 39,40,41,42, 43,44» MOS transistors» Digital electronics MOD 2 (Prof. Lanzoni) Weeks 45,46,47,48,49,50,51,52» OPAMPS» Analog electronics
What is this class all about? to digital integrated circuit design engineering» Key concepts needed to be a good digital IC designer» Design creativity Models and techniques that allow reasoning about circuit behavior» Allow analysis and optimization of the circuit s performance, power, cost, etc.» Understanding circuit behavior is key to making sure it will actually work Teach you how to make sure your circuit works» Do you want your transistor to be the one that screws up a 1 billion transistor chip?
MOD1: What you ll learn... Understanding, designing, and optimizing digital circuits for various quality metrics:» Performance (speed)» Power dissipation» Cost» Reliability
Detailed Topics CMOS devices and manufacturing technology CMOS gates Combinational and sequential circuits Arithmetic building blocks Interconnect Memories Propagation delay, noise margins, power Design methodologies
Logistics Instructor s office hours» By appointment (e-mail) Textbook» J. Rabaey, A. Chandrakasan, B. Nikolic, Circuiti integrati digitali," 2a edizione, Prentice-Hall 2005 (http://bwrc.eecs.berkeley.edu/icbook/)» N. Weste, D. Harris, CMOS VLSI Design 4th Ed., Addison-Wesley 2011 (http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html) Lecture notes» WEB site http://www-micrel.deis.unibo.it/elet1/2015
Written Exam Open book (you can bring book, notes etc) No electronic devices allowed (only calculators) No more penalties if the score is less than 14/30 Dont cheat!! 6 exam per year» 3 exams during Jan-Feb 2016» 2 exams during June-July 2016» 1 exam during September 2016 Exam info: 2 open questions, 1 execise, 75min available.
Exam and Grades Witten final exam» 1 + 1 hrs (Mod1 + Mod2)» Mod1 and Mod2 are independent» Written_grade = (Mod1_grade + Mod2_grade)/2 Oral exam is optional» Final grade = Written_grade» or» (Written_grade + Oral_grade)/2
Digital integrated circuits revolution
Digital Integrated Circuit Design: The past, the present and the future» What made Digital IC design what it is today» Why is designing digital Ics different today than it was before?» Will it change in the future?
The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470
ENIAC - The first electronic computer (1946) Balistic calculator (Used during 2 World War) 18000 valves 1500 relais 30 tons 200 KW $ 486.804,22 (1946) During 10 years of opeating life 19000 valves had to be replaced
The transistor revolution First transistor Shockley, Brattain, Bardeen Bell Labs, 1948 Same Functionality of vacuum tubes but less power and compact, reliable and fast.
The first Integrted Circuit Improvement on technology process :» Planar Transistors (BJT) Integration of many transistors on the same semiconductor substrate Phase shift oscillator Jack Kilby (1958)
The first integrated circuit ECL 3-input Gate Technology: bipolar Motorola 1966 Noyce Fairchil Co-Founder Idea: Planar transistor Process in a single shot several transistor Manufactoring steps Doping Oxidation Lithografy Etching Deposition Etc Beginning of the IC REVOLUTION!!!
Transistor Transistor Logic TTL is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. Became very popular after 1963 (Texas) 7400 and 5400 series Main issue:» Speed» Power
MOS transistor Patented : 1935 (IGFET)...Reinvented in late 60. First working device : 70
Microprocessors Intel 4004 (1971) 2300 transistors 3x4mm 10um process PMOS <1 MHz operation
Microprocessors Intel 4004 (1971) 2300 transistors 3x4mm 10um process PMOS <1 MHz operation
Intel Core 2 Microprocessor Intel Core 2 (2006), 291M transistors, 65CMOS, 143mm² 3GHz
Transistor Counts
Intel SRAM Prototype Chip (2009) 22nm 364MB SRAM > 2.9B transistor 3rd generation High-K + Metal Gate
Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months He made a prediction that semiconductor technology will double its effectiveness every 18 months 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Electronics, April 19, 1965. 1 95 9 1 96 0 1 961 1 96 2 1 96 3 1 96 4 1 96 5 1 96 6 1 96 7 1 96 8 1 96 9 1 97 0 1 97 1 1 97 2 1 97 3 1 97 4 1 97 5 L O G2 O F T H E N U M B E R O F C O M P O N E N T S P E R IN T E G R A T E D F U N C T IO N
Cost per Transistor cost: -per-transistor 1 0.1 Fabrication capital cost per transistor (Moore s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
Scaling Transistor count is the most common measure of integrated circuit complexity.» Intel's 10-core XeonWestmere-EX 2.5 Billion» Xilinx currently holds the "world-record" for an FPGA containing 6.8 Billion transistors. More integration due transistor scaling:» More compact devices» faster» Less power hungry
65nm CMOS Technology PMOS (gate 65nm) 8 Metal Layers for local/global interconnects
Evolution in Complexity memories
Frequency Frequency (Mhz) 10000 Doubles every 2 years 1000 100 486 10 8085 1 0.1 1970 8086 286 Now it s over! P6 Pentium proc Courtesy, Intel 386 8080 8008 4004 1980 1990 Year 2000 2010 Lead Lead Microprocessors Microprocessors frequency frequency doubles every 2 years
Power Dissipation Prediction (2000)
Power density Power Density (W/cm2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 Courtesy, Intel 8086 10 4004 Hot Plate P6 8008 8085 Pentium proc 386 286 486 8080 1 1970 1980 1990 Year 2000 2010 Power density too high to keep junctions junctions at at low temp
Not enough cooling
Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But» How to design chips with more and more functions?» Design engineering population does not double every two years Hence, a need for more efficient design methods» Exploit different levels of abstraction
Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ D n+
Not Only Microprocessors (cell phone ) Small Signal RF Power RF Power Managemen t Analog Baseband Digital Baseband (DSP + MCU) 34
Challenges in Digital Design Macroscopic Issues Microscopic Problems Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability Verification Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different and There s a Lot of Them!?