What's new in MATLAB and Simulink for Model-Based Design

What's new in MATLAB and Simulink for Model-Based Design Magnus Jung Application Engineer 2016 The MathWorks, Inc. 1

What s New? 2

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 3

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 4

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Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 6

Messages, Functions and Scheduling 7

New SimEvents Discrete-event simulation engine for multidomain system models 8

New SimEvents Discrete-event simulation engine for multidomain system models 9

New SimEvents Discrete-event simulation engine for multidomain system models How does communication delays effect your system performance? 10

CAN simulation with Simulink and SimEvents 11

CAN simulation with Simulink and SimEvents 12

CAN simulation with Simulink and SimEvents 13

CAN simulation with Simulink and SimEvents 14

CAN simulation with Simulink and SimEvents 15

CAN simulation with Simulink and SimEvents Without background noise Vehicle stops after 14.2 seconds 16

CAN simulation with Simulink and SimEvents Without background noise With background noise Vehicle stops after 14.2 seconds Vehicle stops after 15 seconds 17

Scheduler Example 18

Scheduler Example 19

Scheduler Example 20

Scheduler Example 21

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 22

Fast Restart Run consecutive simulations more quickly 23

Fast Restart Run consecutive simulations more quickly 24

Fast Restart Run consecutive simulations more quickly 25

Simulink - Faster consecutive simulations Fast Restart 26

Automatic Solver Selection 27

Understanding the selected solver 28

Understanding the selected solver 29

Understanding the selected solver - Solver Profiler 30

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 31

Three-Way Model Merge 32

Report Generation 33

Report Generation 34

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 35

New Product! Simulink Test Develop, Manage, and execute simulation-based tests 36

New Product! Simulink Test Automatically generate Test Harness 37

New Product! Simulink Test Automatically generate Test Harness Test Sequence block 38

New Product! Simulink Test Automatically generate Test Harness Create Test Sequences Manage and Reporting 39

New Product! Simulink Test Automatically generate Test Harness Create Test Sequences Manage and Reporting 40

Real-Time testing with Simulink Real-Time 41

Real-Time testing with Simulink Real-Time 42

Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 43

Questions! 44

Thanks! 45