Addressable Test Chip Technology for IC Design and Manufacturing Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03
IC Design & Manufacturing Trends Both logic and memory technologies continue to scale aggressively with very low k 1 factors As technology scales, design rules and design-process interactions become more complex 10,000 test structures may be needed to fully monitor the design-process windows of of 1,000 complex design rules Source: Mentor Graphics
IC Industry Faces New Models
Latest Challenges of IC Yield Learning Yesterday Today Characteristics Random defects Unknown systematics Layout hot spots Parametric yield loss Yield models Characterization methods Critical area yield model Defect monitors New systematic & parametric yield models need to be developed Need varieties of test structures for new problems
Challenge #1 Parametric Yield Loss Yield of AD converter vs. input transistor pair mismatch
Challenge #2 Layout-dependent Yield Loss, aka DFM, Hot Spot.. SRAM layout-dependent mismatch Poly Tails Local Lithographi c Hot Spot Un-symmetric shift of contacts Pass NMOS P diffusion boundaries right left PMOS Type B
Challenge #3 New Systematic Issues (Example) Factors with performance/yield trade off Cavity depth Disposable spacer thickness Cavity etch esige fill amount Too many process factors to optimize for performance and yield trade off By designing a early testable structure, yield learning is significantly shortened Importance of first time right design: Thick oxide Layout DOE to cover a range of layout configurations
Pressing Questions for Test Chips How to detect these numerous issues with extremely limited test chip area? How to insure design quality of these complex test chips? How to increase test speed?
About Semitronix Semitronix is a leading provider of yield/variability solutions for semiconductor fabs and fabless companies. Product and service includes: 1).Smart test chip system 2).Customized yield/variability improvement service.
Our Answer to Challenges Electrical Data Focused
Solutions in Technology Cycles Early Development Technology Transfer Mass Production Define design rules and DFM rules Optimize process specifications Evaluate process margins and robustness Provide basic look-ahead information (i.e., fail rates, defect densities, etc.) Process matching Yield debug and enhancement Process window check Fine tune process recipes Baseline yield monitoring and enhancement Yield excursion monitoring Equipment matching and monitoring o o o Solutions Solutions Solutions Short flow test chip MPW addressable chip Transistor array o o o MPW addressable chip Transistor array Scribeline addressable chip o o o Scribeline transistor array Scribeline addressable chip Product yield models
Addressable Methodology Intro High-throughput Mapping of Short-Range Spatial Variations Using Active Electrical Metrology, Xu Ouyang, et al., IEEE Transactions on Semiconductor Manufacturing, Vol.15, No.1, Feb. 2002, pg.108-117. Row Decoder I= f(cd,overlay, ) Cell can be SRAM or other custom design Array Column Decoder Mux current measurement Although not a new concept, addressable test chips have not been widely adopted by the industry due to 3 primary reasons: Accuracy for I off, I leakage Design complexity Test and analysis complexity
Proprietary ATCompiler Approach Critical Layout Configurations /Clips System takes smart pcells or any critical layout configurations, and automatically generates addressable test chips and test programs Test pattern Pcell/GDSII Pin connection Auto Test Pattern Generation Pcell from Semitronix or customers Auto place and routing Auto floorplan Auto creation of testing related files Addressable Compiler IP Periphery circuits and routing resources of addressable test chip Customization Tapeout & documentation
Proprietary Addressable Method MPW addressable test chip Highly efficient in mask area and testing speed Real silicon data shows one-to-one correspondence of a same transistor measured via addressable array approach and direct probing Ioff from Array (A) 1.00E-08 1.00E-09 1.00E-10 1.00E-11 Ioff: array vs single 1.00E-12 1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-08 Ioff from single device (A) Resistance Measurement Results Scribe-line test chip: 22 pads, ~200 blocks of test structures, each block ~same size as pad Resistance ranging from milliohms to mega ohms can be accurately measured for detecting hard/soft open defects.
Application for Capacitance Characterization CBCM test items can be placed in addressable arrays Benefits High area-efficiency many different flavors of capacitors can be placed in a very small area High accuracy CBCM provides higher accuracy than traditional LCR method 22 Pads, 869 CBCM(Charged- Based Capacitance Measurement) Array Modules Potential for model data collection and verification
Application for RO Model Verification Ring Oscillators can be placed in addressable arrays Benefits Characterization of signal delays; circuit level verification of SPICE models RO can be designed to be sensitive to different process parameters High area-efficiency using arrays 22 Probe Pads(8 address pads, several pairs VDD/GND, Frequency_out...), 200 RO s
Auto Test program generation Users can define how to test each type of test keys Then the software automatically extract the test key addresses and other info, and create the test table, which can be exported as Agilent or other formats of test plan Test definitions for test keys Created test table
Proprietary Tester We built a proprietary tester that dramatically reduced the test time for DC measurements when combined with our addressable test chip solutions. It is tailored for addressable test chip design with parallel testing, fast switch matrix and SMU, and a flexible & smart software system Same test items Improvement due to tester Improvement due to parallel testing Addressable Test Task Traditional Tester SMT-1(with one measurement SMU) SMT-1(with 3 measurement SMUs) # of test keys per die 464 464 464 # of test items per wafer 80990 80990 80990 Average time per item 120 ms 10 ms 10 ms Total time (130 dies) 164 mins 16 mins 7 mins
Sample Customer Projects 130nm identified top yield issues (eg., silicide, Cu BEOL) using Semitronix technology 40nm quantified transistor variability using addressable transistor test chip 28nm quantified yield and variability issues of high-k metal gate process 14nm FinFET Device and standard cell evaluation using addressable technology Addressable test chip service
Example 28nm Tape Out TOP Cell Type Purpose Total top cells Total Area (mm^2) # of unique test keys # of total test keys LPE transistor second order effects (WPE,LPE,LOD,etc.) 18 3.6 440 ~ 4200 Logic mismatch transistor Logic mismatch 15 3 150 3600 SRAM mismatch transistor SRAM mismatch 3 0.6 6 720 Design rule checking transistors transistor check FEOL design rules, process window 29 5.8 2369 ~4700 Addressable yield array yield array FEOL/BEOL design rules, process margin, random defects, etc. 12 40 8437 ~13000 Short flow short flow test chip BEOL defect size, CT/Via open 1 (12 modules) 3.1 83 83 A 28nm test chip was designed using ATCompiler Total mask area (before shrink) is about 60 mm^2. If conventional passive test chip is used, the required area will be more than 700 mm^2, requiring a full reticle!
Verification: direct probing vs array testing Following are Vtsat and Idsat from single device vs from array The plots confirm that the array results match very well with single device data Vtsat Idsat Vtsat: array vs single 0.6 0.4 0.0007 0.0006 array vs single device Vtsat from array (V) -0.8-0.6-0.4-0.2 0 0.2 0.4 0.6 0.2 0-0.2-0.4 Idsat from Array (A) 0.0005 0.0004 0.0003 0.0002 0.0001-0.6-0.8 Vtsat from single device (v) 0 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 Idsat from single device (A)
Verification: direct probing vs array testing Following are Ioff from single device vs from array The plots confirm that the array results match very well with single device data with Ioff current down to the pa level Ioff 1.00E-08 Ioff: array vs single 1.00E-09 Ioff from Array (A) 1.00E-10 1.00E-11 1.00E-12 1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-08 Ioff from single device (A)
Background Current Verification Background current of Ioff measurement is ~1pA This is consistent with direct probing verification results
Conclusions Addressable test chip technology addresses the challenges of IC industry Semitronix methodology overcomes the 3 challenges of addressable test chips: accuracy; design complexity; test and analysis complexity Abundant data of addressable test chips opens up possibilities for - Fabs: staticial-data-driven yield and variability improvement, accurate layout-depending and variability device modeling - Fabless: better model-hardware correlation for optimized design, on-wafer monitoring of critical designs and devices
Thank You! Dr. David Ouyang david.ouyang@semitronix.com davidouyang@zju.edu.cn