Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid

Transcription

1 Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid Sheng-En David Lin and Dae Hyun Kim Presenter: Dae Hyun Kim (Assistant Professor) School of Electrical Engineering and Computer Science Washington State University ISPD 8, Seaside, CA (3/26/208)

2 Sponsors DARPA YFA D6AP009 Washington State University /72

3 Overview and Motivation Rectilinear Steiner Minimum Tree (RSMT) Shortest wire length On the Hanan Grid or NP-complete 3/72

4 Overview and Motivation All Rectilinear Steiner Minimum Trees on the Hanan Grid Applications Congestion-aware routing Congestion estimation Congested Minimization of the source-to-critical-sink length and the total wire length critical sink critical sink source source 4/72

5 Overview and Motivation Goal All RSMT Construction All RSMT DB Query RSMTs Application software Application software 2 Application software 3 5/72

6 Outline Review Chris Chu, FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design, TCAD 08. Goal Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid Example Simulation Results Conclusion 6/72

7 FLUTE Lookup-Table-Based RSMT Construction Edge decomposition Pin yy 4 yy 3 Vertical edge Horizontal edge vv 3 yy 2 vv 2 vv yy h h 2 h 3 xx xx 2 xx 3 xx 4 7/72

8 FLUTE Wire length computation LL = h + 2 h 2 + h 3 + vv + vv 2 + vv 3 = (,2,,,,) (h, h 2, h 3, vv, vv 2, vv 3 ) Wirelength Vector Coordinate-dependent (Topology-dependent, constant) (variable) yy 4 yy 4 yy 3 vv 3 yy 3 vv 3 vv 2 vv 2 yy 2 yy 2 vv vv yy h h 2 h 3 yy h h 2 h 3 xx xx 2 xx 3 xx 4 xx xx 2 xx 3 xx 4 8/72

9 FLUTE Observation The topology-dependent vectors of some topologies cannot generate RSMTs. Example (a, b, c, d, e, f): LL = aa h + bb h 2 + cc h 3 + dd vv + ee vv 2 + ff vv 3 (a, b, c+, d, e, f): LL 2 = aa h + bb h 2 + (cc + ) h 3 + dd vv + ee vv 2 + ff vv 3 LL 2 LL = h 3 > 0 (,2,,,,) Potentially YES optimal? (,,,,2,) YES (,,,, 33, ) NO (,,,,2, 33) NO 9/72

10 FLUTE Optimal topology (,2,,,,) (h, h 2, h 3, vv, vv 2, vv 3 ) OR (,,,,2,) (h, h 2, h 3, vv, vv 2, vv 3 ) 0/72

11 FLUTE Find all potentially optimal wirelength vectors for each set of relative pin locations. 2 (,2,,,,) (,,,,2,) 2 For given pin locations, compute LL and obtain a shortest-length topology. /72

12 FLUTE Example LL = (,2,,,,) (h, h 2, h 3, vv, vv 2, vv 3 ) LL 2 = (,,,,2,) (h, h 2, h 3, vv, vv 2, vv 3 ) LL LL LL =,2,,,, 2,3,2,2,4, = 7 LL 2 =,,,,2, 2,3,2,2,4, = 8 LL =,2,,,,,5,,3,,3 = 9 LL 2 =,,,,2,,5,,3,,3 = 5 LL =,2,,,, 5,,,,,5 = 5 LL 2 =,,,,2, 5,,,,,5 = 5 2/72

13 FLUTE Position sequence (pin group) Pin yy 4 yy 3 Vertical edge Horizontal edge vv 3 Position sequence ss 4 = 2 ss 3 = 4 vv 2 yy 2 ss 2 = yy h h 2 h 3 vv ss = 3 xx xx 2 xx 3 xx 4 Sort the pins in the increasing order of the y-coordinates (yy, yy 2, yy 3, yy 4 ). Obtain their x-coordinates (xx 3, xx, xx 4, xx 2 ). Obtain the indices (3,,4,2). 3/72

14 FLUTE Example (position sequence) /72

15 FLUTE Potentially Optimal Wirelength Vector (POWV) For each position sequence Example for position sequence (342) ( 2 ) ( 2 ) Potentially Optimal Steiner Tree (POST) For each POWV (,2,,,,) (,,,,2,) 5/72

16 FLUTE Database structure Pin count Multiple position sequences for a pin count ( 2 3 4) ( 2 4 3) ( 3 2 4) ( 3 4 2) Multiple POWVs for a position sequence ( 2 ) ( 2 ) One POST for each POWV 6/72

17 FLUTE How to find POWVs and POSTs Please see the FLUTE paper. Chris Chu and Yiu-Chung Wong, FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue, Jan. 2008, pp /72

18 Goal Database structure Pin count Multiple position sequences for a pin count ( 2 3 4) ( 2 4 3) ( 3 2 4) ( 3 4 2) Multiple POWVs for a position sequence ( 2 ) ( 2 ) All POSTs for each POWV 8/72

19 Brute-Force Algorithm Binary-tree-based (enumeration) ee h,0,2 O ee h,0,0 X ee h,0, ee h,0,0 O ee h,0, ee h,0, O X O X ee h,0,2 ee h,0,2 ee h,0,2 ee h,0,2 X O X O X O X Whenever a leaf node is reached, evaluate the branch to check All the pins are connected. Shortest # Leaf nodes to check (nn: # pins) 2 2nn(nn ) We develop a faster algorithm. 9/72

20 Terminologies Assume nn distinct pins For any two pins pp ii = (xx ii, yy ii ) and pp jj = (xx jj, yy jj ), xx ii xx jj and yy ii yy jj. Edges, vertices Horizontal edge ee vv,0,nn 2 ee vv,0,2 ee h,0,nn Non-pin vertex Vertical edge ee vv,0, ee h,0,2 Pin vertex ee vv,0,0 ee h,0, ee vv,,0 ee vv,2,0 ee vv,3,0 ee vv,nn,0 ee h,0,0 ee h,,0 ee h,2,0 ee h,nn 2,0 20/72

21 Terminologies Neighboring edges of a vertex NNNN dd = {ee, ee 2, ee 3, ee 4 } dd ee 2 ee 3 ee 4 ee Neighboring vertices of an edge NNVV ee = {dd, dd 2 } dd dd 2 ee dd ee dd 2 Neighboring edges of an edge NNNN ee = NNNN(NNNN ee ) = {ee 2, ee 3, ee 4, ee 5, ee 6, ee 7 } ee 2 ee 3 ee 4 ee ee 5 ee6 ee 7 2/72

22 Terminologies Dangling edges If a non-pin vertex is connected to only one edge, the edge is dangling. Not dangling Dangling edge Theorem A POST cannot have dangling edges. 22/72

23 Terminologies Status of an edge Used Removed Available (not used nor removed) Removed Available Used 23/72

24 Terminologies POWV of an edge POWV element corresponding to the edge Example POWV = ( 2 ) pppppppp(ee h,0,0 ) = pppppppp(ee h,,2 ) = 2 pppppppp(ee vv,0, ) = ee h,,2 ee vv,0, ee h,0,0 2 24/72

25 Construction of All POSTs for a Given POWV We apply speed-up techniques to reduce the search space size. Pruning by Zero POWV elements Pruning by must-use and must-remove edges POST evaluation Intermediate connectivity check 25/72

26 Construction of All POSTs for a Given POWV Pruning by zero POWV elements If we decide to use an edge ee, reduce pppppppp(ee) by. If pppppppp(ee) becomes 0, remove all the available edges in the column/row. Remove Remove Remove 2 Use /72

27 Construction of All POSTs for a Given POWV Pruning by must-use and must-remove edges Must-use (remove) edges: Edges that must be used (removed) Using or removing an edge forces us to use or remove some of its neighboring edges. Use Must-use (to avoid dangling edges) Must-use Use 27/72

28 Construction of All POSTs for a Given POWV Pruning by must-use and must-remove edges Use Must-remove (zero POWV) Must-remove Must-remove Use 0 28/72

29 Construction of All POSTs for a Given POWV Pruning by must-use and must-remove edges Remove Must-use (to connect the pin at a dead end) Remove Must-use 29/72

30 Construction of All POSTs for a Given POWV Pruning by must-use and must-remove edges Remove Must-remove (to remove dangling edges) Must-remove Remove 30/72

31 Construction of All POSTs for a Given POWV POST evaluation Evaluation of a topology checks whether the topology connects all the pins. We evaluate a topology only when all the POWV elements become zero. We can evaluate a topology even if we do not reach a leaf node in the binary tree. 2 3/72

32 Construction of All POSTs for a Given POWV Intermediate connectivity check In some cases, a topology is disconnected, especially after using and/or removing edges consecutively. In this case, it is meaningless to proceed further. Thus, we sometimes check whether a topology still connects all the pins through used and available edges. Connected: Proceed further Disconnected: Roll-back Criterion # consecutively used and removed edges threshold Breadth-first search 32/72

33 Construction of All POSTs for a Given POWV Algorithm FLUTE DB POWV data for each position sequence Construct all POSTs for each POWV All POST DB 33/72

34 Construction of All POSTs for a Given POWV 34/72

35 Example # Pins = 4 Position sequence = (4 2 3) POWV = ( 2 ) 2 35/72

36 Example Use ee h,0,0 (later, we will also try removing ee h,0,0 ) 2 36/72

37 Example Decrease pppppppp(ee h,0,0 ) by /72

38 Example Must-use and must-remove edges /72

39 Example Use the must-use edges and remove the must-remove edges /72

40 Example Decrease pppppppp(ee vv,0, ) by /72

41 Example Must-remove edges /72

42 Example Remove the must-remove edges /72

43 Example Must-use and must-remove edges /72

44 Example Use the must-use edges and remove the must-remove edges /72

45 Example Decrease pppppppp(ee h,,0 ) and pppppppp(ee h,2,0 ) by /72

46 Example Must-remove edges /72

47 Example Remove the must-remove edges /72

48 Example Must-remove edges /72

49 Example Remove the must-remove edges /72

50 Example Intermediate connectivity check. Check the connectivity through the used and available edges. # consecutively used and removed edges = 8 BFS 0 Starting point /72

51 Example Roll-back Remove ee h,0,0 2 5/72

52 Example Roll-back Remove ee h,0,0 2 52/72

53 Example Must-remove edges 2 53/72

54 Example Remove the must-remove edge. 2 54/72

55 Example Solution space size is reduced by 4X. Before: 2 24 After: /72

56 Simulation Results POST DB Construction. Time: Construction time 2. Eff.: Construction efficiency (# POSTs found/second) 3. Size: Table size (file size) # pins # pin groups (n!) # POWVs in a group # POSTs for a POWV Min. Avg. Max. Min. Avg. Max. Total # POSTs Time Eff. 2 Size s s 80K s 8K ,260 0.s 54K 0.MB ,22 3.7s 32K 3.5MB 7 5, ,920, s 5K 4MB 8 40, ,558 78,33,96 9hr 5.5K 7.7GB 9 362, ,020 0,33,050,02,700hr.7K 525GB 56/72

57 Effectiveness of the Speed-Up Techniques Runtime comparison (in seconds) 6 pins 7 pins with All w/o Zero POWV elements w/o must-use edges w/o mustremove edges w/o intermediate connectivity check , Ratio (.00) 3.65, ,837 6, Ratio (.00) /72

58 Statistics # Edges Used in POSTs XXXXXX /72

59 Statistics # Edges Used in POSTs XXXXXX /72

60 Statistics # Edges Used in POSTs XXXXXX /72

61 Statistics # Edges Used in POSTs XXXXXX /72

62 Statistics # Edges Used in POSTs X47X6X /72

63 Statistics # Edges Used in POSTs (randomly chosen) /72

64 Statistics # Edges Used in POSTs (POWV having the fewest POSTs) /72

65 Statistics # Edges Used in POSTs (POWV having the most POSTs) /72

66 Application Congestion-aware RSMT generation (finding RSMTs avoiding specific edges) Congested All POST DB Congested Congested Congested 66/72

67 Application Source-to-critical-sink length minimization All POST DB critical sink critical sink source source 67/72

68 Application Source-to-critical-sink length minimization Position sequence: source critical sink 68/72

69 Application Non-preferred routing path (finding RSMTs avoiding specific edges) Preferred routing path (finding RSMTs using specific edges) Source-to-critical-sink length optimization Fast routing estimation (placement, routing, ) 69/72

70 For High-Degree Nets FLUTE generates an RST. FLUTE Wirelength Vector (WV) Obtain all RSTs satisfying the WV (Use the proposed algorithm) 70/72

71 For Non-Distinct Pins lim h 0 LL OR h h 7/72

72 Conclusion We proposed an efficient algorithm to construct a database of all POSTs for up to nine pins. The DB can be used for various purposes. Placement Routing The algorithm can also be used to find RSTs for high-degree nets (more than nine pins). 72/72

73 Thank you (Please me for the POST DB)