OpenAccess In 3D IC Physical Design

Transcription

1 OpenAccess In 3D IC Physical Design Jason Cong, Jie Wei,, Yan Zhang VLSI CAD Lab Computer Science Department University of California, Los Angeles Supported by DARPA and CFD Research Corp

2 Outline 3D IC Background Motivation Different technologies Thermal-Aware 3D Physical Design Flow Thermal-aware aware 3-D 3 D floorplanning Thermal-aware aware 3-D 3 D routing Using OpenAccess for 3D IC Designs OA-based 3D Physical Design flow Extending OA to 3D Designs UCLA VLSICAD LAB 2

3 3D IC Background Interconnect Delay Reduction of k Layers D k = 1 D1 k Integration of Different Technologies to Implement System-on on-a-chip System-in in-a-package Source: Proc. of IEEE, Vol. 89, No. 5, May UCLA VLSICAD LAB 3

4 3D IC Technology Alternatives Different 3D technologies [Stern, et. al, TCPM96] chip level integration (3DMCM) vertical interconnect pitch>50µm vertical interconnect density< 20/mm (400/mm 2 ) [Chiang, et. al, IEDM01] block level integration vertical pitch>5µm vertical density<40k/mm 2 cell level integration vertical pitch>200nm vertical density<25m/mm 2 [Scientific American 2002] UCLA VLSICAD LAB 4

5 Thermal Challenges in 3-D 3 D ICs High Temperature Effects: Longer interconnect delays Functional failure Temperature increases dramatically along the Z direction Z Key Challenge of 3-D 3 D IC Design: Higher power density due to the higher device density Inter-layer dielectric layers are poor thermal conductors UCLA VLSICAD LAB 5

6 Through-the the-silicon Vias (TS-Vias) New in 3-D 3 D IC designs Usually large and expensive to make Number and distribution will affect the temperature and wirelength Effective heat dissipating pipe Two types of TS-vias Signal TS-vias, connecting the signal nets Dummy TS-vias, with no connections, inserted to reduce temperature [Alam, et. al, ISQED02] UCLA VLSICAD LAB 6

7 UCLA 3D Physical Design Flow w/o OA Netlist (LEFDEF) Design constraints Technology Thermal-Driven 3D Floorplanner Timing Analysis HDM Thermal-Driven 3D Placement Thermal-Driven 3D Router FILE I/O Thermal Simulation Parasitic Extraction CIF/GDSII Layout Verification UCLA VLSICAD LAB 7

8 Thermal-Aware 3D Floorplanning Simulated Annealing Engine Easy to handle multiple constraints Cost function cost = α nwl + β narea + γ nvc + η nwl normalized wirelength narea normalized chip area nvc normalized interlayer via number C T temperature cost Hybrid Thermal Evaluation Use both the resistive model and the simplified model to get a good g tradeoff between accuracy and runtime At each move simplified thermal model At each SA temperature drop the resistive model to correct the accumulated errors by the simplified model UCLA VLSICAD LAB 8 c T L1 L2 L3 j b f h e d k g a c i

9 Thermal-Aware 3D Routing Problem Input 3-D D floorplanning/placement result Technology Netlist Required temperature, such as 80 O C Output Routed nets Dummy TS-via number and locations Objectives Minimum wirelength Minimum TS-via number Challenges and Solutions More routing layers, large search space - MARS Handle the temperature constraints - MARS Large obstacles on device layers Via Planning UCLA VLSICAD LAB 9

10 TMARS Multilevel Routing Framework level 0 G 0 G i Compact Thermal Model G i G 0 level 0 G k Downward Pass level i level i Upward Pass (1) Power Density Calculation (2) Plug Position Estimation (3) Heat Flow Map Updates (1) Power Density Coarsening (2) Heat Flow Map Coarsening level k (1) 3-D Steiner Tree Generation (2) Plug Number Estimation (3). ADPP (4). Plug Number Adjustment (1) Plug Refinement by ADPP (2) Signal Plug& Dummy Plug Assignment (3). Plug Number Adjustment (4) Wire Refinement UCLA VLSICAD LAB 10

11 A simple example Base design provided by Irvine Sensor: #Chips: 6 #Stack Layers: 3 #Pins: 520 #Connections: 268 #Routing Layers: 9 (with 3 metal layers attached to each device) Chip B 12cmx8cm Cache Memory Chip A 15cmx15cm Processor Chip A 15cmx15cm Chip Processor B 12cmx8cm Cache Memory Chip C 12cmx8cm DRAM Chip C 12cmx8cm DRAM UCLA VLSICAD LAB 11

12 Final Layout Runtime: 76s #Vias: 1384 Wirelength: 2.54m (1 layer:3.2m, 4 layer: 2.5m) UCLA VLSICAD LAB 12

13 Motivation of Using OpenAccess Industrial-level level data model Efficient data sharing between different tools Stable, efficient, well-maintained Use the existing tools on OA Parsers: verilog,, LEF/DEF, GDSII, Timer GUI Tool sharing Ongoing project: save the effort of code rewriting UCLA VLSICAD LAB 13

14 OpenAccess in 3D IC Physical Design Flow Netlist (LEFDEF) Design constraints Technology Thermal-Driven 3D Floorplanner Thermal-Driven 3D Placement Thermal-Driven 3D Router Open Access CIF/GDSII Timing Analysis Thermal Simulation UCLA VLSICAD LAB 14

15 Basic 3D IC Circuit Structure Multiple Multiple Device Layer Structure Each with multiple metal routing layers Blocks/cells can be located at different device layers Interlayer vias going through device layer M M D M M D M M D UCLA VLSICAD LAB 15

16 Special 3D IC Circuit Structures Blocks can occupy multiple layers Device layer can be put upside down Interlayer vias can be very tall [Deng, et. al, ISPD01] [Alam, et. al, ISQED02] UCLA VLSICAD LAB 16

17 Extending OpenAccess to 3D IC Design OpenAccess Assumptions One device layer Blocks/cells move in x and y directions No interlayer vias 3D Circuit Structure Description Vertical structure: materials, thermal conductivities, height, etc. e Blocks/cells: multiple layers, Z positions Special structures: up-side side-down down device layers, tall vias, etc UCLA VLSICAD LAB 17

18 Our Implementation of Extending OA Alternatives to OA Extensions Add new objects to the data model: oaappobjectdef Add new fields to the current objects: oaappdef Add simple name/value pair: oaprop New properties oalayer: : tier, height, thickness, thermal conductivity oainstheader: : power density oainst: : tier UCLA VLSICAD LAB 18

19 Current Status of OA Integration Netlist (LEFDEF) Design constraints Technology Thermal-Driven 3D Floorplanner Thermal-Driven 3D Placement Thermal-Driven 3D Router Open Access CIF/GDSII Timing Analysis Thermal Simulation UCLA VLSICAD LAB 19

20 Summary Our view of OpenAccess The ultimate way of tool integration Enable efficient tool sharing Reliable, efficient, well-maintained, complicated data model OpenAccess in 3D IC Designs Necessary extensions to handle 3D IC design Vertical layer structure: can be very complicated Power/temperature information Current status and plan Finished the router interface with OA Working on a whole flow on top of OA UCLA VLSICAD LAB 20