Challenges of FPGA Physical Design

Transcription

1 Challenges of FPGA Physical Design Larry McMurchie 1 and Jovanka Ciric Vujkovic 2 1 Principal Engineer, Solutions Group, Synopsys, Inc., Mountain View, CA, USA 2 R&D Manager, Solutions Group, Synopsys, Inc., Mountain View, CA, USA Notice of Copyright This material is protected under the copyright laws of the U.S. and other countries and any uses not in conformity with the copyright laws are prohibited. Copyright for this document is held by the creator authors and sponsoring organizations of the material, all rights reserved. This document has been submitted to, and reviewed and posted by, the editors of DAC.com. Please recycle if printed.

2 Page 2 of 8 ARTICLE: FPGA Physical Design Challenges of FPGA Physical Design Larry McMurchie 1 and Jovanka Ciric Vujkovic 2 1 Principal Engineer, Solutions Group, Synopsys, Inc., Mountain View, CA, USA 2 R&D Manager, Solutions Group, Synopsys, Inc., Mountain View, CA, USA Abstract Today s FPGAs are able to satisfy the design requirements of a larger percentage of the market that had previously only been served by ASICs. At each successive process node, FPGAs become more attractive alternatives to ASICs for many low- and medium-volume applications because of their lower cost per gate, shorter time to market and lower development risk. Unique features such as programmability and partial re-configuration are advantages that allow better return on investment, power reduction, and access to new application domains. In this article, we will address the challenges in physical design (placement, packing, routing) for FPGAs. Such challenges include the inevitable improvements in performance and power as well as runtime reduction, enabling of incremental changes with design preservation, and partitioning to support team design. Index Terms Physical design, FPGA.

3 Page 3 of 8 I. INTRODUCTION Modern FPGAs have heterogeneous architectures that consist of regularly spaced logic elements covering the whole die. Typically, columns spanning the height of the chip contain memories, DSPs, clock buffers and IOs. Some devices contain processor cores that occupy part of the die. Logic elements contain lookup tables, sequential elements, adders and multiplexers. An example of an FPGA is depicted in Figure 1. Logic Block DSP Memory Processor core Figure 1: FPGA architecture. The FPGA design flow (Figure 2) starts with RTL descriptions and design constraints, and the result is a netlist that is mapped onto the library elements in the FPGA device. After logic synthesis and mapping, a designer can use an FPGA vendor s (Actel, Altera, Lattice, Xilinx, etc.) place and route (P&R) tool to do placement, routing and bit stream generation. Physical synthesis tools from third-party vendors, such as Synopsys Synplify Premier, perform physical synthesis steps such as global placement, optimizations, detailed placement and routing. The optimized netlist is annotated with placement and routing information and forwarded to the FPGA vendor s P&R tool to finish the flow and generate the bit stream. The benefits of using physical synthesis are better timing performance, timing correlation and timing closure.

4 Page 4 of 8 Logic Synthesis Physical Synthesis Global Placement Detailed Placement Partial Routing Vendor Placement Vendor routing, DRC, Bitstream generation Figure 2: Physical design flow for FPGAs. II. PLACEMENT CHALLENGES FOR FPGAS Because of the heterogeneous architectures of FPGAs, traditional ASIC tools such as analytic placers need to be modified and adapted to FPGA architectures. The heterogeneity in FPGAs is reflected in discrete locations for big macro blocks such as DSPs, memories, etc., as shown in Figure 1. The placement algorithms need to be resource-aware: flip-flops, LUTs, carry chains, and macro blocks need to be placed at the corresponding sites on the device. Another difference that arises from the ASIC world is delay modeling. Unlike ASICs, FPGA routing architectures are very granular, typically consisting of fast, short wires that are scarce, followed by medium-length wires spanning a few rows and/or columns, and long wires that span a large number of rows and columns. A given net delay can vary dramatically depending on which type of wire is selected for routing the signal. Placement algorithms that were successfully used in ASIC design can be adapted for use in the global placement stage for FPGAs [1] [2] [3] [4] [7]. To reduce routing congestion, proven successful ASIC approaches such as white-space handling [10] [11] can be used in FPGA global placement. Simulated annealing is used widely in FPGAs because of its capability to model complex cost functions that can capture the heterogeneous delay model in FPGAs, packing cost and congestion [5]. For example, VPR placement and routing [12] was used in the Altera P&R tool and has at its core a simulated annealing algorithm. Interesting work that models the placement problem as a graphembedding of the netlist on the metric space representing FPGA delays is presented in [8], with promising results on Xilinx devices. Partitioning-based placement for FPGAs is another available technique [13]. A comprehensive survey of FPGA design automation techniques is provided in [15].

5 Page 5 of 8 In our experience, the best placement approach is a hybrid of ASIC techniques and methods that account for the granularity of FPGA architectures. The role of global placement is to obtain a coarse placement with architecture-independent optimizers and smoothened cost functions that include wire length, timing and congestion factors. Predicting accurate timing at this level is difficult because delay estimation is crude, placement can have overlaps, and legalization is not guaranteed. Integration of packing in the global placement stage is crucial to alleviate some of these problems. The role of the packing algorithm is to pack the logic cells (LUTs, flip-flops, carry chain, and muxes) into the logic block, while satisfying the legalization rules inside the logic block. Timing and performance improvement can be accomplished with multiple iterations of architecture-dependent optimizations, fast legalization and the global solver. The challenge is to carry over the improvements in worst and total negative slack in the global placement phase through legalization steps and detailed placement to the final timing signoff. The role of the detailed placer is to take advantage of the FPGA architecture in the packing strategy, wire usage and integration with physical synthesis optimizations such as replication, rewiring, retiming and logic restructuring. Efficient reservation and management of routing resources during detailed placement can ensure good timing correlation, optimization of critical paths and better congestion handling, all of which translate into better design performance [14]. An example of the importance of managing routing resources in the detailed placer is shown in Figure 3. The fastest route to the LUT input pin A6 is through a bounce programmable interconnect point (pip) AX. This pip AX is also the only pip to connect to a D input of a flip-flop in the same slice. If the flip-flop is not occupied, the fastest connection to the LUT is achieved. But if a FF is placed in the same slice such that it needs the AX pip to route to its input, the net to the LUT will take a detour with noticeable delay increase. If the FF was not critical, then placing it in the same slice was not a good choice by the detailed placer. switch matrix switch matrix slice Net1 slice A6 LUT A6 LUT FF AX AX Net1 Net2 Figure 3: Physical example of bounce routes effect on placement.

6 Page 6 of 8 III. ROUTING CHALLENGES FOR FPGAS Routing in FPGAs is similar to ASIC routing; however, there are important differences. Routing resources in FPGAs are discrete switches at fixed locations, whereas in ASICs the resources are relatively continuous and non-directional. Thus, FPGA routing architectures are more appropriately modeled as directed graphs. The first challenge is to represent the directed routing graph (which today contains billions of elements) in a compact structure that can be efficiently accessed. There are numerous examples of mature design databases in EDA that might be used to compactly represent the routing graph. One particular open-source effort is OpenAccess (OA) [16]. OA can be used to represent a wide variety of architecture-related data, from structural RTL down to layout. It utilizes IC-specific data compression techniques that reduce disk and memory usage. Efficient access of the graph is required by the innermost loops in all routers, which traverse the directed graph and compute costs of the nodes in the graph. Although a database such as OA could reduce the memory footprint, it is doubtful that access of the elements of a directed graph would be fast enough to be incorporated into the innermost loop of the router. Hence, hand-crafted structures and access methods are required. The routing problem itself is one of finding conflict-free routes and meeting timing constraints. Routers today use a variety of approaches to satisfy these goals. Some perform a congestion-based route first to find a conflict-free routing, and then attempt to optimize routes on critical paths. Others attempt to satisfy both (i.e., conflict and criticality) objectives simultaneously. In this latter category, the Pathfinder algorithm [9] has been used with considerable success for the last two decades to solve this problem. Pathfinder starts with a delay-optimal route for all nets, ignoring conflicts caused by multiple signals occupying the same nodes. During subsequent reroutes, Pathfinder introduces costs for conflicts, but in a gradual fashion. Such costs are determined by the number of rerouting attempts as well as the criticality of the nets vying for the same node. The fundamental idea is to give priority to critical nets and force less-critical nets to find alternate routes. A key element in the implementation is the gradual change in routing costs, so that a semi-equilibrium state is maintained between rerouting attempts, and sufficient alternate routes are attempted. The plus side is that quality of the final routes is high: clock periods determined by timing analysis using the final routing delays are typically only a few percent degraded from those obtained during the initial route. On the other hand, the multiple rerouting attempts and gradual introduction of costs for conflicts can require substantially longer runtimes than other methods. As a result, the innermost loop of the router must be carefully constructed so that graph traversal and cost calculation are very efficient. Efficient graph queries and methods such as A* are critical for tolerable runtimes. Looking to the future, routing algorithms must adapt to increasingly complex logic blocks. Such complex logic blocks produce more compact (and higher-performance) circuit implementations. Fast local routes are often provided for nearest-neighbor connections. Often, however, algorithms have difficulty allocating such fast local routes and making the tradeoff between delays/slacks of nets that compete for these routes. In the future, special treatment of local routes will be needed. For example, such routes may be determined by the detailed placer and preset for the router, as might be the case for the route shown in Figure 3. IV. RUNTIME CHALLENGES IN PHYSICAL DESIGN Runtime is increasingly one of the main challenges in physical design for FPGAs. Physical synthesis, placement and routing are typically runtime-intensive when they are geared for achieving best performance. For Xilinx Virtex6 devices with more than 300,000 LUTs, and designs with 85% LUT and flip-flop utilization, the runtime from physical synthesis through Xilinx place and route is

7 Page 7 of 8 typically more than 24 hours. Multi-threading and multiprocessing are used to speed up parts of the flow that are inherently parallelizable, such as force calculation in global placement [2] or moves in simulated annealing [6]. In our experience, speedups of 2.4X on eight cores are obtained by parallelizing the conjugate gradient solver used in the global placer. The best speedups are achieved at the highest levels of the algorithms or by partitioning the design and running each partition on separate cores. Unfortunately, logical hierarchies are typically not appropriate for physical design partitioning because instances from different hierarchies must be placed close or packed together to achieve best performance. The challenge is therefore to partition the design such that physical synthesis can be run on each partition separately without a significant sacrifice in QoR. Speedups of up to 30 percent in logic synthesis can be achieved by partitioning the design into modules and mapping each module onto a separate thread or processor. In the physical synthesis step this is much harder, because the place and route steps for the modules are intertwined unless the design is partitioned into non-overlapping regions. If place and route for each module is done separately on a different processor, with the results stitched back together, speedups of the physical design part of the flow could be achieved to a similar degree as in logic synthesis. V. INCREMENTAL PHYSICAL DESIGN FLOWS With increased design size, incremental flows are a very important aspect of reducing runtime and maintaining timing closure when only a small part of the design is changed. The goal here is to preserve the performance of the parts of the design that were not modified. The problems of incremental design performed by a single designer are magnified in team design, where designers across multiple geographies and time zones work on different modules that share the same FPGA die. In some applications, floorplanning can easily divide the real estate into separate regions. But in most applications, the locations of macro blocks such as memories and DSPs require that partitions be defined with overlapping regions, requiring sharing of regions between team members. Finding a way to partition the physical design across multiple team members, while preserving resource and timing constraints, will be increasingly important as FPGA designs are created by teams. FPGA vendor tools from Altera and Xilinx have features that allow designers to make changes to a critical block and iterate through logic synthesis and place and route just for that block until timing is closed. Partitions that have not changed are frozen for both placement and routing in order to guarantee timing on that partition. This can result in unroutable placements when changes in other parts of the design require routing resources that were locked for the frozen partition. As some of these problems are addressed in the next generation of incremental flows, practical use by designers will reveal how well the incremental tools have matured and how well they help designers to rapidly close timing when making changes to their designs. VI. CONCLUSION The traditional view of FPGA CAD tools has been that they should be easy to use and pushbutton, with reasonable compile time to enable at least 1-2 compilations per day. As FPGAs move to 32nm process nodes and beyond, the challenges of modeling delay, power consumption and congestion, as well as controlling compile time and turnaround time, will necessitate innovation in physical synthesis. Innovation will come from placement, floorplanning, packing and routing algorithms, as well as delay modeling and design methodology. Meeting these challenges, while maintaining physical design tool ease-of-use and high quality-of-results, is the continuing task before us.

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