Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Transcription

1 Diagnosis and Layout Aware (DLA) Scan Chain Stitching Jing Ye 1,2, Yu Huang 3, Yu Hu 1, Wu-Tung Cheng 3, Ruifeng Guo 3, Liyang Lai 3, Ting-Pu Tai 3, Xiaowei Li 1 (yejing@ict.ac.cn; yu_huang@mentor.com; huyu@ict.ac.cn; {wu-tung_cheng; ruifeng_guo; liyang_lai; ting-pu_tai}@mentor.com; lxw@ict.ac.cn) Weipin Changchien 4, Daw-Ming Lee 4, Ji-Jan Chen 4, Sandeep C. Eruvathi 4, Kartik K. Kumara 4, Charles Liu 4, Sam Pan 4 Abstract 1 1 State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS, Beijing , P. R. China. 2 University of Chinese Academy of Sciences, Beijing , P. R. China. 3 Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA. 4 Taiwan Semiconductor Manufacturing Company, Hsinchu Science Park, Hsinchu, Taiwan. measuring signal change frequency, these techniques normally provide good chain diagnostic resolution. However, due to their long diagnostic time and high cost, they may be not suitable for volume diagnosis. Without appropriate stitching of chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) chain stitching method, which is pattern independent and supports embedded compaction. It is based on three ideas: (1) increasing the number of sensitive, which can capture useful diagnostic information; (2) properly distributing the sensitive along the chains to enhance the overall resolution; (3) stitching based on their placement at layout to preserve the chip performance. Experiments on ISCAS 89/ITC 99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method. 1. Introduction Scan chains are widely used in digital circuits as a Design- For-Test (DFT) technique to increase the fault coverage. As reported in [1], elements and clocking circuitry occupy about 30% of silicon area. In [2], it reports that 10~30% of defects could cause chains to fail. In [3], it reports that of chip failures are caused by chain defects. Hence, diagnosing chain faults with good resolution is important to guide silicon debug, Physical Failure Analysis (PFA), and yield learning process. Scan chain fault diagnosis techniques can be classified into three categories [4]: tester-based techniques, hardwarebased techniques, and software-based techniques. In the tester-based diagnosis techniques [5]-[9], a tester, cooperated with some PFA equipments, is used to locate faulty. Based on the equipment functions such as 1This work is supported in part by National Natural Science Foundation of China (NSFC) under grant No and , and in part by National Basic Research Program of China (973) under grant No. 2011CB302503, and in part by the cooperative project with Mentor Graphics Corp.. Hardware-based and software-based diagnosis techniques are suitable for volume diagnosis. In the hardware-based techniques [10]-[15], dedicated cell structures or chain designs are proposed. In [10], multiplexers are added to propagate data from one chain to another chain. In [11]-[14], some global signals and specific circuitries such as XOR gates are added. They enable certain to be either set or reset after shift-in, and then faulty are identified by analyzing the shiftout bits. In [15], a helix cell structure is proposed to keep test data from being distorted by chain faults. Though they can effectively identify faulty, the extra diagnostic signals and circuitries usually incur prohibitive hardware overhead. Software-based techniques [1]-[3] [16]-[27] analyze the observed failing and passing responses to narrow down the suspects of faulty. Diagnostic patterns can also be generated to improve the chain diagnostic resolution. In this paper, we first observe that without diagnosis aware chain stitching, even with good diagnosis algorithms and diagnostic patterns, it may still result in bad chain diagnostic resolution. Then we propose the Diagnosis and Layout Aware (DLA) chain stitching method, which can effectively improve the chain diagnostic resolution. It has following advantages: (1) It belongs to hardware-based technique because the DLA chain stitching is determined during layout generation. However, it does not add any extra signals or circuitries as other hardware-based techniques. (2) The chain fault diagnosis is still performed by the state-of-the-art software-based techniques, as proposed in [27], which is already well established in industry. (3) It takes the cell placement into consideration such that it has negligible impact on chip performance. (4) It is pattern independent, so it can be accommodated in the current design flow, where chains are stitched during DFT or layout generation before Automatic Test Pattern Generation (ATPG). (5) It supports embedded compaction, which is widely used in large industrial designs nowadays. Paper 15.1 INTERNATIONAL TEST CONFERENCE /13/$ IEEE

2 Diagnosability is not the first objective of chain stitching. The techniques in [28]-[30] stitch chains to reduce the test power dissipation. Since they are pattern dependent, they are not suitable for the current design flow. In [31][32], pattern independent chain stitching techniques are proposed to improve the system logic transition fault coverage with heuristic algorithms. As our target is to improve the chain diagnostic resolution, we will not specify how to deal with the transition fault coverage in our heuristic algorithms. However, we will evaluate the impact of the proposed method on transition fault coverage, test power dissipation, embedded compaction, and chip performance in the experiments. For the cell structure based test power reduction [33]-[35] and transition fault coverage improvement [36], our method can still be applied because we only change the ordering without caring their structure. The rest of the paper is organized as follows. Section 2 defines some terminologies. Section 3 reviews the previous software-based diagnosis techniques and points out the root causes of bad chain diagnostic resolution. In Section 4, the DLA chain stitching method is proposed. Experimental results are shown in Section 5, followed by conclusions. 2. Terminologies Chain Flush Pattern: A chain flush pattern consists of shift-in and shift-out operations without pulsing capture clocks. It is used to test chains in -based designs. Scan ATPG Pattern: Scan ATPG patterns consist of shiftin, capture(s), and shift-out operations. They are generated by ATPG tools to test system logic. Scan Chain Fault Model: There are six common singlesided fault models, used to characterize chain defects: Stuck-At-0 (SA0), Stuck-At-1 (SA1), Slow-To-Rise (STR), Slow-To-Fall (STF), Fast-To-Rise (FTR), and Fast- To-Fall (FTF). As an example illustrated in Fig.1, a chain flush pattern 0110 is applied. The fault effects of six fault models are given. We can see that the chain flush pattern does not only tell whether a chain is faulty, but also tell the fault type. However, it is insufficient for locating the faulty cell. To figure out where a fault occurs, analysis of failing and passing responses under ATPG patterns is necessary. Fig.1 Fault Effects of Scan Chain Fault Models 3. Motivation In this section, we will use an example illustrated in Fig.2 to briefly review one of the software-based diagnosis techniques, and then explain the root causes of bad chain diagnostic resolution and our key ideas to improve it. 3.1 Review of Chain Diagnosis Method The circuit in Fig.2 contains two chains S 1 and S 2 with totally nine from C a to C i. Assume there is one SA0 fault on S 2. A ATPG pattern is shifted into S 2. If no faults occur on S 2, after capture, assume should be shifted out. The software-based diagnosis technique normally contains three steps: Step-1: For each ATPG pattern, X-mask all the sensitive bits shifted into the faulty chain. The bit X means, during shift-in, the bit of a cell may be contaminated by the chain fault. In Fig.2, as a SA0 fault occurs on S 2, bits shifted into C f and C i are masked to X s. Step-2: Simulate X-masked ATPG patterns to get the bits captured by the. In Fig.2, under the pattern C e C f C g C h C i = 0X00X, C e, C f, C g, C h, and C i capture 111X1. The X captured by C h means that C h may capture either 0 or 1, which depends on whether C i is contaminated during shift-in. Hence, among the five on S 2, only C h may not capture a sensitive bit. Step-3: Compare the simulated captured bits with the observed shift-out bits to locate the faulty cell. For instance, in Fig.2, if the actual SA0 fault occurs at C f, bits are observed. Comparing the simulated captured bits 111X1 with the observed bits 00101, we find that, Sensitive Bit: The sensitive bit(s) of a chain fault is the bit(s) which can sensitize the fault [27]. For stuck-at faults SA0 and SA1, the sensitive bits are 1 and 0, respectively. For timing faults STR, STF, FTR, and FTF, instead of a single bit, only a specific transition in a bitpair can sensitize them. For example, a transition from 0 to 1 is called the sensitive bits of a STR fault. Sensitive Cell: For a specific fault model, a cell is a sensitive cell if it captures a sensitive bit during capture cycle under at least one ATPG pattern, otherwise, the cell is a Non-Sensitive Cell. Fig.2 Diagnosing Scan Chain Fault Paper 15.1 INTERNATIONAL TEST CONFERENCE 2

3 during shift-out, the sensitive bits of C e and C f are contaminated, but the sensitive bit of C g is not, so we can infer that the actual SA0 fault occurs at C f. From the above example, we can see that it got good chain diagnostic resolution because the faulty cell and its neighboring happened to be sensitive. If the faulty cell happens at a different location, as we will see in the next subsection, the resolution may drop. 3.2 Number of Sensitive Cells Considering another fault in Fig.2, if the SA0 fault occurs at C g, the observed bits are Comparing 111X1 with 00001, we can only infer that the SA0 fault occurs at C g or C h. However, we cannot tell which one is the actual faulty cell. This is because the simulated bit captured by C h is X. If C h can capture the sensitive bit 1 instead of X, and if we observe 1 at it, we can infer the SA0 fault occurs at C g not C h. On the other hand, if C h can capture 1, but we observe 0, we can infer the SA0 fault occurs at C h not C g. From this example, we can see that one of the root causes why SA0 faults at C g and C h cannot be distinguished is that C h is a non-sensitive cell. Therefore, increasing the number of sensitive is critical in improving the overall chain diagnostic resolution. In general, to increase the number of sensitive, we need to reduce the number of X s captured into the faulty chain. Some previous works [21][22] tried to generate extra specific diagnostic patterns to increase the number of sensitive. However, without diagnosis aware chain stitching, many non-sensitive cannot become sensitive by generating diagnostic patterns. For instance, in Fig.2, to make C h a sensitive cell under SA0 fault, the diagnostic pattern should satisfy the following constraints. First, C h should capture the sensitive bit 1. Secondly, the that are in the C h s system logic fanin cone and are also on the same chain as C h are identified: C g and C i. These two should have shift-in value 0, so they will not be masked to X. Obviously, no diagnostic patterns can satisfy these constraints simultaneously, and hence no diagnostic patterns can be generated to make C h become a sensitive cell. We run experiments on ISCAS 89 and ITC 99 benchmark circuits (whose chains are stitched by a commercial tool) to see the percentage of that cannot become sensitive for SA0 fault by generating such diagnostic patterns. The experimental results are illustrated in Fig.3. On average, 71.5% of cannot become sensitive by generating such patterns. Instead of generating diagnostic patterns, to increase the number of sensitive, our key idea is to assign to appropriate chains. In Fig.2, C g, C i, and C h are all on one chain S 2. Also, C g and C i are in the system logic fanin cone of C h. Since the bit of C i is masked to X during shift-in, C h captures X. If we swap C i and C d, as shown in Fig.4-(1), C i will not be masked to X because Percentage of Scan Cells that Cannot Become Sensitive Cells by Generating Diagnostic Patterns 40% 30% 20% 10% 0% s13207 #S=2 s13207 #S=4 s15850 #S=2 s15850 #S=4 s35932 #S=2 s35932 #S=6 s38417 #S=2 s38417 #S=6 b20 #S=2 b20 #S=4 b17 #S=2 b17 #S=6 Fig.3 Percentage of Scan Cells that Cannot Become Sensitive Cells by Generating Diagnostic Patterns (#S: Number of Scan Chains) Fig.4 Increasing Number of Sensitive Cells C i is no more on the faulty chain S 2. Hence, C h becomes a sensitive cell. Therefore, without adding any extra signals or circuitries, or generating any extra diagnostic patterns, we have been able to increase the number of sensitive. In practice, chains are stitched during DFT or layout generation before ATPG. Hence a pattern independent method is a must. As shown in Fig.4-(2), in addition to swapping the C d and C i, C c and C g are also swapped. In this way, no matter under what ATPG patterns, the cell C h will never capture X. We call this kind of, like C h, as potential sensitive : For a cell C, if all the in C s system logic fanin cone are on different chains from C, C is a potential sensitive cell, otherwise, C is a non-potential sensitive cell. Potential sensitive have very high chance to be the actual sensitive, especially when the number of faulty chains is limited. To simplify the terminologies, we will drop the potential and just use Sensitive Cell and Non-Sensitive Cell from now on. 3.3 Distribution of Sensitive Cells Average Distribution of sensitive and non-sensitive along the chains also determines the chain diagnostic resolution. If there are 6 consecutive non-sensitive between C g and C i, as shown in Fig.5-(1), the 7 SA0 faults cannot be distinguished. If we simply move C g to the middle of these consecutive non-sensitive, as shown in Fig.5-(2), we can partition the 6 non-sensitive into Paper 15.1 INTERNATIONAL TEST CONFERENCE 3

4 (1) (2) C e C f C g C h C j C k C l C m C n C i X X X X X X 1 SA0 Faults Cannot Be Distinguished C e C f C h C j C k C g C l C m C n C i 1 1 X X X 1 X X X 1 Cannot Distinguished Cannot Distinguished Fig.5 Minimizing Consecutive Stitching of Non-Sensitive Cells 2 non-consecutive groups, and each group has only 3 nonsensitive. Therefore, only 4 SA0 faults cannot be distinguished in each group. As a rule of thumb, when stitching, the sensitive should be distributed evenly along each chain such that the maximum size of consecutive non-sensitive is as small as possible. 3.4 Layout Aware Scan Chain Stitching In general, given a netlist of a design, a layout generation tool will do the placement first to determine the locations of logic and at layout. Next, the placement of can be fixed, and the chains can be restitched for different purposes such as reducing the overall chain routing distance. Finally, the layout generation tool will do the routing to connect logic and based on the re-stitched chains. No matter assigning to appropriate chains to increase the number of sensitive or adjusting ordering on each chain to enhance the distribution of sensitive, once the chains are restitched, the routing of a layout will be changed. If two are far away at layout, but are stitched on the chain, a long wire is needed between them at the layout. Such long wires for stitching chains may impact the routing of system logic and result in serious routing congestion. High routing congestion may require an increased die size and create new and unpredictable critical paths that degrade the chip performance. Consequently, when running diagnosis aware chain stitching, the cell placement at layout must be taken into accounts. Therefore, the proposed methodology in this paper is called Diagnosis and Layout Aware Scan Chain Stitching, or DLA Scan Chain Stitching in short. At layout, if the non-sensitive and the sensitive are close, we can utilize the nearby sensitive to break the consecutive non-sensitive without too much routing overhead. If sensitive are far away from nonsensitive at layout, long wires have to be used at some points. Therefore, to preserve the chip performance, when assigning to chains, we not only increase the number of sensitive, but also ensure that there are sensitive nearby non-sensitive at layout. 4. The Proposed Methodology The overview of the proposed DLA chain stitching method is shown in Fig.6. A simulated annealing algorithm is proposed to assign to appropriate chains, followed by an ant colony optimization algorithm to stitch the on each chain. The two algorithms are explained in the next two subsections. 4.1 Simulated Annealing Algorithm Simulated annealing is a heuristic methodology of locating a good approximation to the global optimum of a given function in a large search space [37]. The input of our simulated annealing algorithm includes the layout placement and the system logic fanin relation of. The target is to assign the to appropriate chains so that (1) there are as many sensitive as possible, and (2) there are sensitive nearby nonsensitive at layout. The flowchart of the proposed algorithm is illustrated in Fig.7. First, the layout is divided into grids. The grids are used to judge whether there are sensitive nearby nonsensitive at the layout. For example, assume a chain s has 10 inside a grid g. If all the 10 are non-sensitive, it may cost large wiring to break the consecutive stitching of these 10 non-sensitive by using some sensitive from other grids. To quantify the status of the chain s inside the grid g, we calculate the Percentage of Sensitive Cells (denoted by P SC (s,g)) for the chain s inside the grid g. For example, when there are 5 sensitive among the 10 of the chain s inside the grid g, the P SC (s,g) is 5/10=0.5. A higher P SC (s,g) implies a better distribution of sensitive and non-sensitive (and consequently smaller routing cost) of the chain s inside the grid g at the layout. If the average P SC of all chains inside all grids is high, normally, the total number of sensitive is large too. Fig.6 Overview of Diagnosis & Layout Aware Scan Chain Stitching Fig.7 Flowchart of Simulated Annealing Algorithm Paper 15.1 INTERNATIONAL TEST CONFERENCE 4

5 Secondly, are randomly assigned to chains to obtain initial sensitive and non-sensitive. The initial P SC of each chain inside each grid is then calculated. In practice, the number of chains and the number of on each chain are normally specified by DFT engineers during insertion. Thus, to maintain the length of chains, we iteratively swap to increase the average P SC instead of directly assigning a cell to a different chain. For the previous example in Fig.2, assume that in one iteration, the nonsensitive cell C h is targeted. As shown in Fig.4-(1), by swapping C i, which is randomly selected from C h s fanin, with another randomly selected cell C d, C i and C h are assigned to different chains. If in another iteration, C g and C c are also swapped, as shown in Fig.4-(2), C h becomes a sensitive cell. The inside a grid with lower P SC have higher probability to be chosen as the target of an iteration such that the average P SC can be increased. After each iteration of swapping, the new average P SC is calculated. Due to the swap, some nonsensitive may become sensitive or vice versa. The new average P SC after swap and the old average P SC before swap are compared. If the average P SC becomes worse, the swap is only accepted with the probability e Δ I/τ (τ is a user-defined variable, and I is the current iteration number). Otherwise, the swap is always accepted. When the number of iterations or the number of continuous rejection of swap achieves a certain threshold, the iterative swap stops. The optimal assignment of to chains so far will be used as input to the next ant colony optimization algorithm for determining the ordering on each chain. 4.2 Ant Colony Optimization Algorithm The input of the ant colony optimization algorithm includes the cell layout placement and the chains with assigned. The target is to determine the ordering on each chain such that (1) the overall routing distance of chains is as small as possible, and (2) consecutive stitching of non-sensitive is minimized. The flowchart of the algorithm to stitch a chain is given in Fig.8. Fig.8 Flowchart of Ant Colony Optimization Algorithm First, according to the number of sensitive on a chain, we can calculate the optimized maximum number of non-sensitive allowed to be consecutively stitched on the chain. For example, assume there are 11, and among them there are 3 sensitive. In the best case, when we evenly distribute the sensitive among the non-sensitive, at most 2 non-sensitive are consecutively stitched. Hence, the optimized maximum number of consecutive non-sensitive can be set to 2, which is used as a constraint in the later steps. Next, iterative procedures are performed to determine the ordering. In each iteration, one path stitching all the on the chain is formed. The cell that is closer to the layout edge is selected as the start of the path, and the are stitched to the path one at a time. For a previously stitched cell C P on the path, the cell to be stitched next to it should not only satisfy the constraint of the optimized maximum number of consecutive non-sensitive, but also guarantee that there are enough un-stitched sensitive left to make the un-stitched non-sensitive satisfy the constraint too. Then the probability PROB P-N of selecting a cell C N (satisfying above constraints) to stitch next to C P is calculated as shown in Fig.8. The d P-N represents the layout distance between C P and C N, and the w P-N refers to the pheromone between C P and C N. Pheromone is an important element in ant colony optimization [38]. It represents the information derived from stitched paths and guiding the future path stitching. In other words, the paths stitched in preceding iterations guide the paths stitched in the succeeding iterations through the pheromone. In the first iteration, for any two C x and C y, w x-y is 1, so the PROB x-y is totally dependent on the layout distance between these two. After the first iteration, the overall layout distance of the stitched path is calculated. If C P and C N are indeed stitched on the path, then the w P-N is updated according to the overall layout distance of the path. A longer distance will result in a smaller w P-N, so in the next iteration, the probability of stitching C P with C N decreases; A shorter distance will result in a larger w P-N, so in the next iteration, the probability of stitching C P with C N increases. When the number of iterations achieves a certain threshold, or when the overall layout distances of paths are longer than the previously shortest distance for certain number of continuous iterations, the iterative procedure stops. The shortest path stitched so far will then determine the ordering on the chains. In addition, the objective of this paper is improving the chain diagnostic resolution, but as mentioned before, there are also some other stitching objectives. To consider them, the equation of PROB P-N could be modified. For instance, the previous work [32] points out that avoiding connection two with overlapping fanout cones can effectively improve the system logic transition fault Paper 15.1 INTERNATIONAL TEST CONFERENCE 5

6 coverage. To consider this factor, we can add a multiplier to the equation to control the probability of connecting with overlapping fanout cones. 4.3 Embedded Scan Compaction Since embedded compaction techniques are widely used in large industrial designs nowadays, in this subsection, we will introduce how to stitch chains when there are Embedded Deterministic Testing (EDT) compactors [16]. The proposed method is also suitable for other space compactors. For instance, in Fig.9, there are six chains: S 0 and S 1 are compacted into the channel 0, and S 2 and S 3 are compacted into the channel 1, and S 4 and S 5 are compacted into the channel 2. Assume we know S 0 has SA0 fault by applying EDT masking chain patterns [16]. According to our definition, C 01 is a sensitive cell if all the in its fanin cone are on S 1, S 2, S 3, S 4, or S 5. However, due to the compactor, even if C 01 does capture the sensitive bit 1, but if C 11 captures X, C 01 still has no contribution in improving the diagnostic resolution. This is because, when shifting out the captured data, 1 captured in C 01 is masked by X captured in C 11. Thus, with compactors, a cycle can contribute to the chain diagnosis, if none of the compacted at the cycle captures X. In Fig.9, to make both C 01 and C 11 in channel 0 useful for chain fault diagnosis, one way is to put the in their fanin cones to other channels (channel 1 or channel 2) rather than channel 0. In such way, neither C 01 nor C 11 will capture X when the fault occurs in channel 0. Obviously, the proposed simulated annealing algorithm and ant colony optimization algorithm are both orthogonal with this method for EDT compaction. 5. Experimental Results The proposed DLA chain stitching method is implemented in C++ language. Experimental circuits include some large benchmark circuits of ISCAS 89 and ITC 99, and one real industry test chip manufactured with 20nm technology. The embedded compaction used in our experiments is the EDT compaction [16]. The experiments are conducted on a Linux server with eight 2.33GHz CPUs and 16G memory. Scan Chain S 0 Scan Chain S 1 Scan Chain S 2 Scan Chain S 3 Scan Chain S 4 Scan Chain S 5 1 C 02 1 C 01 1 C 00 C 12 X Channel 0 C 11 C 10 EDT Scan C 22 C C 20 Compactor C 32 C 30 Channel 1 C 31 C 41 C 42 C 01 C 40 C 52 C 51 C 50 Channel 2 Fig.9 EDT Scan Compaction For every experimental circuit, we generate three versions: (1) DLA version with Diagnosis-and-Layout-Aware stitched chains. It is generated by the proposed method with the simulated annealing algorithm and the ant colony optimization algorithm. (2) DAO version with Diagnosis-Aware-Only stitched chains. It is generated by using the proposed simulated annealing algorithm to assign to appropriate chains, but not using the ant colony optimization algorithm to stitch the based on their placement at layout. To stitch the, sensitive are randomly selected to break the consecutive stitching of non-sensitive. (3) LAO version with Layout-Aware-Only stitched chains. It is generated by a commercial tool, not considering the chain diagnosis quality, but only considering the chain routing distance. It is worth noting that, when generating DLA or DAO, the layout area is constrained the same size as LAO. For each version of every circuit, ATPG patterns are generated by a commercial tool, and for each cell, six failure log files are created by injecting one of the six chain fault types: SA0, SA1, STR, STF, FTR, and FTF. Then a commercial tool is used to diagnose the failing logs and report the suspect. The chain diagnostic resolution for diagnosing one failure log is calculated as: Diagnostic Resolution = Number of Suspect Scan Cells Meanwhile, with the design netlist and layout, we also use commercial tools to do the following evaluations: (1) The chip performance, which is measured by the maximum chip clock frequency. (2) Under EDT compaction, the system logic stuck-at fault coverage and the number of ATPG patterns. (3) The system logic transition fault coverage. (4) The test power dissipation, which is measured by the percentage of cell transitions during capture and shift. In the following subsections, we will first present the improvement on diagnostic resolution for benchmark circuits, and then show the other evaluation results. Finally, we will study the real industry case with silicon results. 5.1 Diagnostic Resolution The diagnostic resolutions are presented in Table I. The first column shows the names and the number of of each circuit. The second and the third columns show the number of chains and the number of EDT channels. N/A means no EDT compactors are applied. The fourth column shows the label used to represent each circuit in the following context. The fifth column shows the version. The next twelve columns show the average and the worst diagnostic resolutions. The last column shows the runtime of the proposed method. Paper 15.1 INTERNATIONAL TEST CONFERENCE 6

7 TABLE I DIAGNOSTIC RESOLUTIONS OF BENCHMARK CIRCUITS #S: Number of chains; #C: Number of EDT channels; N/A: EDT compaction is not applied; Avg.: Average diagnostic resolution; Wst.: Worst diagnostic resolution; Labels will be used in the following context to represent each circuit. Circuit #S #C Label Version SA0 SA1 STR STF FTR FTF Runtime Avg. Wst. Avg. Wst. Avg. Wst. Avg. Wst. Avg. Wst. Avg. Wst. (seconds) LAO N/A E1 DAO s s s s b b N/A E2 6 3 E3 2 N/A E4 4 N/A E5 6 3 E6 2 N/A E7 6 N/A E E9 2 N/A E10 6 N/A E E12 2 N/A E13 4 N/A E E15 2 N/A E16 6 N/A E E18 DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA LAO DAO DLA Generally speaking, the diagnostic resolutions of DLA and DAO are similar, since both of them take the diagnosis quality into accounts. The DLA and the DAO achieve significant improvement on diagnostic resolution in comparison with the LAO. The improved diagnosability differs for different circuits. Some improvements seem small because the diagnostic resolutions of some LAO are already good. The largest improvement appears in the circuit E14 under SA0 fault, where DLA improves the average diagnostic resolution by 10.06X, and in the circuit E18 under SA1 fault, where DLA improves the worst diagnostic resolution by 28.00X. On average, DLA improves the diagnostic resolution by 2.94X for SA0 fault, 1.56X for SA1 fault, and 1.16X for timing faults; DLA improves the worst diagnostic resolution by 8.43X for SA0 fault, 5.62X for SA1 fault, and 2.50X for timing faults. Paper 15.1 INTERNATIONAL TEST CONFERENCE 7

8 From Table I, we can also see that, as the number of chains increases, the diagnostic resolutions of DLA and DAO generally become better. This is because, with more chains, a cell s fanin are more likely to be assigned to different chains than the chain containing the cell itself. Hence more sensitive can be obtained. On the other hand, the diagnostic resolutions of timing faults are generally better than that of stuck-at faults. This is because the sensitive bits of timing faults are transition bit-pairs instead of a single bit. Hence, during shift-in, fewer bits may be masked to X. However, due to same reason, a cell without capturing X may not obtain a valid transition, so it is still a non-sensitive cell. That is why, for only a few cases, the diagnostic resolutions of DAO and DLA for timing faults are a little worse than that of LAO. For stuck-at faults, only under the circuit E13, the average diagnostic resolutions of DAO and DLA for SA1 fault are a little worse than that of LAO, but this brings around 5X resolution improvements for SA0 fault. The average runtime of creating DLA and DAO is 28.00s and 14.76s, respectively. As heuristic algorithms, the simulated annealing algorithm and the ant colony optimization algorithm could achieve better results with more iterations and longer runtime. For PFA, the fewer number of suspect, the better. The cases with diagnostic resolution 1 are the perfect candidates for PFA. If the diagnostic resolution is no more than 3, the cases are still acceptable by PFA, otherwise the cases are seldom analyzed by PFA. In Fig.10, for stuck-at faults, we present the percentage of diagnosis cases with diagnostic resolution =1 and <=3. LAO DAO DLA Precentage of Diagnosis Cases with Diagnostic Resolution = 1 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average LAO DAO DLA Precentage of Diagnosis Cases with Diagnostic Resolution <= 3 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average Fig.10 Percentage of Cases with Diagnostic Resolution =1 and <=3 On average, the percentage of diagnosis cases with diagnostic resolution 1 increases from 71.82% of LAO to 87.1% of DAO and to 89.59% of DLA; the percentage of diagnosis cases with diagnostic resolution no more than 3 increases from 88.94% of LAO to 98.58% of DAO and 98.72% of DLA. Hence, using the proposed method, more effective diagnosis results can be provided for PFA. 5.2 Chip Performance Using the maximum chip clock frequency of LAO as the baseline, the normalized maximum chip clock frequencies of DLA and DAO are illustrated in Fig.11. Without considering the cell placement in DAO, it could cost long wires for stitching chains at layout, which may affect the routing of system logic and result in large degradation of chip performance. The average performance degradation of DAO is about 4.05%. By considering the layout placement when stitching in DLA, the performance degradation is much smaller. The average value is only around 0.22%. Hence, the proposed method has very small impact on chip performance. In addition, please note that, for several circuits, the maximum chip clock frequency of DLA is a little larger than that of LAO. This is because LAO optimizes the chain routing only. Though avoiding long chain routing is normally able to avoid degrading the chip performance, the shortest chain routing does not always lead to the highest chip performance. It is possible that some wires that pass through critical region of system logic may happen to be used in LAO, but are not used in DLA, which makes the chip performance of several DLA a little bit better than that of LAO. 5.3 Embedded Scan Compaction With embedded compaction in the circuit, we do not change the number of channels, the number of chains, and the length of chains, as we mentioned earlier. However, the fault coverage of system logic and the number of ATPG patterns could be different since the compacted are changed. In Fig.12, we present the stuck-at fault coverage and the number of ATPG patterns. We can see that, LAO, DAO, and DLA have similar results. In other words, the proposed method does not impact stuck-at fault coverage and ATPG patterns with EDT compaction. 105% LAO DAO DLA Normalized Maximum Chip Clock Frequency 105% E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average Fig.11 Chip Performance Paper 15.1 INTERNATIONAL TEST CONFERENCE 8

9 Stuck-At Fault Coverage LAO DAO DLA E3 E6 E9 E12 E15 E18 Number of Scan ATPG Patterns LAO DAO DLA E3 E6 E9 E12 E15 E18 0 Fig.12 EDT Scan Compaction 5.4 Transition Fault Coverage Transition fault coverage of system logic is also related to the ordering of. We present the transition fault coverage in Fig.13. On average, it is 95.43% for LAO, 95.81% for DAO, and 95.74% for DLA. 5.5 Test Power Dissipation The test power dissipation is measured by calculating the percentage of cell transitions during capture and during shift. The experimental results are presented in Fig.14. In general, the test power dissipations are very close for these three versions of circuits. Transition Fault Coverage LAO DAO DLA 99% 99% 98% 98% 97% 97% 96% 96% 94% 94% 93% 93% 92% 92% 91% 91% 89% 89% 88% 88% 87% 87% 86% 86% E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average 40% 30% 20% 10% Fig.13 Transition Fault Coverage 0% 0% E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average 40% 30% 20% 10% Percentage of Scan Cell Transitions During Capture LAO DAO DLA Percentage of Scan Cell Transitions During Shift LAO DAO DLA Fig.14 Test Power Dissipation 40% 30% 20% 10% 40% 30% 20% 10% 0% 0% E1 E2 E3 E4 E5 E6 E7 E8 E9 E10E11E12E13E14E15E16E17E18 Average 5.6 Real Industry Case Study The proposed method is applied to a real industry circuit R1, which is a test chip manufactured with 20nm technology. In R1, there is one block A duplicated many times. In block A, there are 18796, stitched into 160 chains, and every 20 chains are compacted into one EDT channel. To compare the effectiveness of DLA over LAO on silicon, about 40% of block A use DLA, while others use conventional LAO. Before manufacturing, like benchmark circuits, we also run simulations to analyze the diagnostic resolution of block A using DLA, DAO, and LAO, respectively. Since timing faults are much easier to be diagnosed than stuck-at faults, only the diagnostic resolutions of stuck-at faults are analyzed, as shown in Table II. In comparison with LAO, DLA improves the average and the worst diagnostic resolution by 1.36X and 6.21X for SA0 fault, and by 1.26X and 29.00X for SA1 fault, with only 0.2% performance degradation. DAO achieves a higher improvement of diagnostic resolution, but it causes 6.5% performance degradation. Fig.15 highlights a chain in block A of LAO, DAO, and DLA at layout. Since DAO does not consider the cell layout placement, unlike LAO and DLA, its chain is stitched globally at the layout. After manufacturing, 9 dies failed on Automatic Test Equipment (ATE) are found with chain faults in LAO blocks, and 6 dies failed on ATE are found with chain faults in DLA blocks. The diagnostic resolutions of all these cases are given in Table III. On average, using the DLA chain stitching method, the diagnostic resolution is improved by 7X based on the silicon results. TABLE II DIAGNOSTIC RESOLUTIONS OF A REAL INDUSTRY CIRCUIT Block A SA0 SA1 Performance #S #C Version of R1 Avg. Wst. Avg. Wst. Degradation LAO DAO % DLA % Fig.15 A Scan Chain at Layout TABLE III DIAGNOSTIC RESOLUTIONS OF SILICON RESULTS FC: Faulty Chain. LAO DLA Die1 FC1 2 FC1 2 Die1 FC1 2 Die2 FC1 2 FC2 2 Die2 FC1 2 Die8 Die3 FC1 2 FC3 14 Die3 FC1 2 Die4 FC1 3 FC4 53 FC1 2 Die4 FC1 1 FC1 1 FC2 2 Die5 FC2 1 FC2 2 FC1 1 Die5 FC1 1 FC3 2 FC2 5 Die6 FC2 1 FC4 3 FC1 1 Die9 FC1 1 FC5 3 FC2 1 Die7 FC2 2 FC6 6 Die6 FC3 2 FC7 25 FC4 2 FC8 179 FC5 2 Average 14 Average 2 Paper 15.1 INTERNATIONAL TEST CONFERENCE 9

10 6. Conclusions In this paper, we observe that the root causes of bad chain diagnostic resolution are the lack of sensitive and the bad distribution of sensitive along chains. Thus, we propose a novel Diagnosis and Layout Aware (DLA) chain stitching method. It is pattern independent, so it can be accommodated in the current design flow. It also supports embedded compaction, which is widely used in large industrial designs nowadays. To increase the number of sensitive, a simulated annealing algorithm is proposed to assign to appropriate chains. To determine the ordering on chains, an ant colony optimization algorithm is proposed to reduce the chain routing distance and to minimize consecutive non-sensitive. Experimental results on benchmark circuits prove the effectiveness of the proposed method in improving the chain diagnostic resolution with negligible impact on chip performance, embedded compaction, transition fault coverage, and test power dissipation. Applied in a real industry circuit, the proposed method improves the average diagnostic resolution for silicon chain defects by 7X. 7. References [1] S. Kundu, "On Diagnosis of Faults in a Scan Chain," Proc. of VLSI Test Symposium (VTS), pp , [2] R. Guo and S. Venkataranman, "A Technique for Fault Diagnosis of Defects in Scan Chains," Proc. of International Test Conference (ITC), pp , [3] J.-S. Yang and S.-Y. Huang, "Quick Scan Chain Diagnosis Using Signal Profiling," Proc. of International Conference on Computer Design (ICCD), pp , [4] Y. Huang, R. Guo, W.-T. Cheng, and J. C.-M. Li, "Survey of Scan Chain Diagnosis," IEEE, Design & Test of Computers, vol. 25, no. 3, pp , May-June [5] P. Song, F. Stellari, T. Xia, and A. J. Weger, "A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current," Proc. of ITC, pp , [6] F. Stellari, P. Song, T. Xia, and A. J. Weger, "Broken Scan Chain Diagnostics based on Time-Integrated and Time-Dependent Emission Measurements," Proc. of International Symposium for Testing and Failure Analysis (ISTFA), pp , [7] L. K. Chia and R. I. Mohammed, "Diagnosis of Multiple Scan Chain Faults," Proc. of ISTFA, pp , [8] Hwang, D. Kim, N. Seo, E. Lee, W. Choi, Y. Jeong, J. Orbon, and S. Cannon, "Deterministic Localization and Analysis of Scan Hold- Time Faults," Proc. of ISTFA, pp , [9] K. Khusyari, T. N. Wei, N. Jaarsma, R. Abraham, W. N. Peng, H. A. Boon, and H. O. Chin, "Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method," Proc. of Asian Test Symposium (ATS), pp. 271, [10] J. L. Schafer, F. A. Policastri, and R. J. McNulty, "Partner SRLs for Improved Shift Register Diagnostics," Proc. of ITC, pp , [11] S. Edirisooriya and G. Edirisooriya, "Diagnosis of Scan Path Failures," Proc. of VTS, pp , [12] G. Edirisooriya and S. Edirisooriya, "Scan Chain Fault Diagnosis with Fault Dictionaries," Proc. of International Symposium Circuits and Systems (ISCAS), pp , [13] S. Narayanan and A. Das, "An Efficient Scheme to Diagnose Scan Chains," Proc. of ITC, pp , [14] Y. Wu, "Diagnosis of Scan Chain Failures," Proc. of International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp , [15] F. Wang, Y. Hu, H. Li, and X. Li, "A Design-For-Diagnosis Technique for Diagnosing Combinational Circuit Faults with Faulty Scan Chains" Proc. of Asia-Pacific Design Automation Conference (ASP-DAC), pp , [16] Y. Huang, W.-T. Cheng, and J. Rajski, "Compressed Pattern Diagnosis for Scan Chain Failures," Proc. of ITC, pp , [17] Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski, R. Klingenberg, W. Hsu, and Y.-S. Chen, "Diagnosis with Limited Failure Information," Proc. of ITC, [18] Y.-L. Kao, W.-S. Chuang, and J. Li, "Jump Simulation: A Technique for Fast and Precise Scan-Chain Fault Diagnosis," Proc. of ITC, paper 22.1, [19] R. Guo and S. Venkataraman, "An Algorithmic Technique for Diagnosis of Faulty Scan Chains," IEEE Transcations on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 9, pp , Sept [20] Y. Huang, W.-T. Cheng, R. Guo, W. Hsu, Y.-S. Chen, A. Man, "Diagnose Compound Scan Chain and System Logic Defects," Proc. of ITC, [21] F. Wang, Y. Hu, Y. Huang, H. Li, and X. Li, "Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects," Proc. of ITC, paper 14.1, [22] F. Wang, Y. Hu, Y. Huang, J. Ye, and X. Li, "Observation point oriented deterministic diagnosis pattern generation (DDPG) for chain diagnosis," Proc. of Asian Test Symposium (ATS), pp , [23] R. Guo, L. Lai, Y. Huang, and W.-T. Cheng, "Detection and Diagnosis of Static Scan Cell Internal Defect," Proc. of ITC, paper 17.2, [24] W.-S. Chuang, S.-T. Lin, W.-C. Liu, and J. C.-M. Li, "Diagnosis of Multiple Scan Chain Timing Faults," IEEE Transcations on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 6, pp , June [25] C. Sunghoon and A. Orailoglu, "DiSC: A New Diagnosis Method for Multiple Scan Chain Failures," IEEE TCAD, vol. 29, no. 12, pp , Dec [26] M. Cheng and A. Orailoglu, "Diagnosing Scan Clock Delay Faults Through Statistical Timing Pruning," Proc. of Design Automation Conference (DAC), pp , [27] Y. Huang, W.-T. Cheng, R. Guo, T.-P. Tai, "Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns," Proc. of Asian Test Symposium (ATS), pp , [28] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, "Design of Routing-Constrained Low Power Scan Chains," Proc. of DATE, pp , [29] S.-J. Wang; K.-L. Peng, and K. S.-M. Li, "Run Based Reordering: A Novel Approach for Test Data Compression and Scan Power," Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp , [30] Y.-Z. Wu and M. C.-T. Chao, "Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes," Proc. of VLSI Test Symposium (VTS), pp , [31] S. Wang and S. T. Chakradhar, "A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs," Proc. of International Test Conference (ITC), pp , [32] W. Li, S. Wang, S. T. Chakradhar, and S. M. Reddy, "Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage," Proc. of International Conference on VLSI Design (ICVD), pp , [33] R. Sankaralingam and N. A. Touba, "Inserting Test Points to Control Peak Power During Scan Testing," Proc. of Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp , [34] S. Sharifi, J. Jaffari, M. Hosseinababy, A. Afzali-Kusha, and Z. Navabi, "Simultaneous Reduction of Dynamic and Static Power in Scan Structures," Proc. of Design, Automation, and Test in Europe (DATE), pp , [35] S. P. Khatri and S. K. Ganeshan, "A Modified Scan-D Flip-Flop to Reduce Test Power," International Test Synthesis Workshop (ITSW), [36] B. Dervisoglu and G. Stong, "Design for testability: using path techniques for path-delay test and measurement," Proc. of International Test Conference (ITC), pp , [37] S. Kirpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, Science 220(4598), pp , [38] A. Colorni, M. Dorigo, V. Maniezzo, Distributed Optimization by Ant Colonies, Proc. of European Conference on Artificial Life, pp , Paper 15.1 INTERNATIONAL TEST CONFERENCE 10