SmartScan - Hierarchical Test Compression for Pin-limited Low Power Designs

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1 - Hierarchical Test Compression for Pin-limited Low Power Designs K. Chakravadhanula *, V. Chickermane *, D. Pearl *, A. Garg #, R. Khurana #, S. Mukherjee #, P. Nagaraj + Encounter Test R&D, Front End Design Group, Cadence Design Systems * Endicott, NY, USA + San Jose, CA, USA # Noida, UP, India Abstract IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead. 1. Introduction The proliferation of portable electronic devices has placed a greater focus on the efficient testing of these devices both on the test floor and in the user environment. Increasingly, SoCs are built with DFT-ready IP cores that use embedded test compression hardware. When multiple cores are integrated in a SoC there is a test bandwidth challenge when the narrow test access mechanism (TAM) at the top-level has to feed to the wider TAM at the core-level. SoC test pins are limited either by cost considerations high-speed tester pins are expensive or by test throughput considerations such as multi-site testing. Core-level DFT designers on the other hand favor a large multiplicity of short scan chains for the increased flexibility, leading to wider TAMs. correlation also increases. High correlation can impact the ability of automatic test pattern generation (ATPG) engines to generate tests for many faults in compression mode. Figure 2 shows how correlation can be a barrier to the effectiveness of combinational compression architectures when the scan bandwidth is reduced. The chart plots the fault coverage in the compression (XOR) mode such as described in [3] and (bypass) modes for different number of scanin (and scanout) pins. As expected, the coverage in the bypass mode is independent of the number of scan pins and stays at a consistently high number. Reasonably high fault coverage was obtained in the compression mode with 5 or more scanin pins. As the number of scanin (and scanout) pins goes down, the coverage achievable in compression is significantly reduced. This requires more top-up patterns in bypass mode to achieve the target fault coverage, negatively impacting the effective compression achieved. Fault Coverage (%) COMPRESSION FULLSCAN Number of scan in pins Figure 1. Generalized compression architecture Figure 1 shows a generalized combinational compression scheme that also supports X-masking [1-4]. The decompressor is directly connected to scanins and the compacted response is visible at scanouts. The mask enable (CME) determines on a per scan cycle basis whether an X captured in the internal scan chains is to be blocked from transfer into the compressor. The ratio of number of internal scan chains to the number of scanin pins is called the target compression ratio and when all the scan chains are balanced it is a close approximation of the compression in tester cycles achieved. As the compression ratio increases, the number of internal chains that get identical data due to data Figure 2. Effect of reducing the TAM bandwidth This paper presents a generalized time-multiplexed TAM architecture called that enables the efficient interconnection of core-level TAMs to SoC TAMs, allowing efficient distribution of compressed test data streams to and from embedded cores. The key idea is to serialize the compressed streams of test data and control bits at the corelevel and allow the SoC designer a flexible way to interconnect the core-level TAMs to the top-level tester pins. The presented method is especially beneficial for low power designs where shifting all the scan chains concurrently will cause unacceptable level of switching activity and may lead to IR drop issues or damage the chip due to overheating. The paper is organized as follows. Section 2 describes previous work. An overview of the architecture Paper 4.2 INTERNATIONAL TEST CONFERENCE /13/$ IEEE

2 is presented in Section 3 and Section 4 describes structured hierarchical interconnection architectures and unique low power aspects. Section 5 describes physically-aware layout of using scan pipelines. Section 6 describes interfacing with and P1687 access mechanisms. The paper then provides experimental results and conclusions. 2. Previous Work Some of the earliest work in this area was described in [5], [6] and [7] in the context of efficiently partitioning test resources between ATE electronics and on-chip DFT structures. ATE can transfer test data at 5-20X faster than typical scan shift frequencies, but are pin-limited due to the high cost of high-speed test pins. Chips can internally support multiple scan chains, X more than the number of test pins, but can only shift at much lower speeds. The use of time domain multiplexing such as used for highspeed functional data transfer using Serializers and Deserializers was proposed to achieve the bandwidth matching. The key concept is to transfer data through a low bandwidth channel by expanding it over a wider time frame. More recent work has extended this to combine this approach with on-chip test compression based on space compactors such as XOR and LFSR based structures. These structures allow data to be transferred from a high bus-width to a lower bus-width and vice-versa with the encoding technique providing a trade-off between compressibility vs. loss of information. In [8], the authors describe a serialization scheme tailored to their proprietary method of test compression called Adaptive Scan. The target application was to connect multiple embedded cores with test compression logic to SoCs in a hierarchical design environment. Their solution works very well for their proprietary compression scheme but has some limitations when extended to a generalized compression scheme. Since the TAM is blended in with the compression logic, the tests generated at the core-level cannot be easily re-targeted to the SoC-level. A new blended ATPG model of the core has to be created for SoC-level test generation, and top-level ATPG has to be re-run for each embedded core. Some novel techniques to support as few as three test pins is described in [9]. Their target application is imaging applications which have very few digital test pins available. Based on the serialization concept they created two vendorspecific implementations to convert the parallel compressed test data stream to a serial stream. They wrote wrapper scripts to transform the ATPG generated patterns on the original core. This work requires a vendor-specific test controller and TAM and does not address generic On- Product Clock Generation (OPCG) with multiple clock domains and use in a hierarchical bottom-up flow. More recently [10] describes the practical aspects of implementing a time-division multiplexed TAM for GPUs. They also write a wrapper script to serialize the patterns and their key contribution is in their detailed descriptions of the DFT insertion, rule checking and verification. The key contributions of this work are as follows: 1) Support for generalized XOR based compressors and decompressors and not restricted to a proprietary test compression hardware 2) The time-domain multiplexing also supports serialization of X-mask data and OPCG control data for multiple clock domains 3) The ATPG patterns generated at the core-level using the parallel compressed data bus are re-used at the SoClevel and serialized concurrently enabling seamless multi-core support without any scripting. There is no reduction in test coverage or compression ratio between the parallel and serial vector sets. The serialization is built into the backend ATPG process where the internal test pattern database is written out into ATE compatible formats such as STIL or WGL. 4) The serialization is compatible with IEEE or IEEE P1687 interfaces allowing this scheme to be used at the board or system level and 3D stacks. Selective patterns from the parallel test pattern set can be easily re-applied serially using the 5-pin TAP interface. 5) A novel extension of the DFT hardware permits scan chains to be divided into interleaved scan sections so that all the scan chains do not have to shift concurrently and a pre-set shift latency allows the effective scan switching factor to be reduced by a large factor. 3. Overview Figure 3 shows a simplified view of the architecture with optional X-masking. Note that while the explanation focuses on XOR-based compression schemes, the concepts also apply to MISR-based schemes. Figure 3. architecture The two N-bit shift registers deserialize/serialize the compressed test data and interface with the tester via the SERIAL_SCAN_IN and SERIAL_SCAN_OUT pins. It takes N cycles to load the input shift register (i.e., deserializer) with the compressed data for a single bit-slice of the scan chains. Once the deserializer is loaded, the clock to the internal scan chains is fired and data is transferred into the internal scan chains. Similarly the output serial shift register (serializer) does a parallel capture of the functional response data from the internal scan chains and serially shifts it out. The deserializer and serializer shift operations Paper 4.2 INTERNATIONAL TEST CONFERENCE 2

3 are overlapped such that when new data is shifted in via the SERIAL_SCAN_IN, the response data (from the scan chains) contained in the serializer is shifted out via the SERIAL_SCAN_OUT. If X-masking is present, then every N cycles the deserializer delivers N-1 bits of scan data and one bit of mask_enable data. The mask_enable allows per scan cycle activation of the masking. Figure 4 illustrates waveforms for an example design having 8-bit deserializer (and serializer) registers and 2-bit long internal scan chains. The clock controller gates the top-level test clock to generate the clocks for the deserializer and serializer registers, the internal scan chains and for the mask registers. It uses the scan_enable and mask_load_enable signals to differentiate between the scan and mask load states. The generated scan and mask clocks are mutually exclusive and pulse once every N cycles during the scan and mask load states respectively. The only exception is upon entry into scan or mask state, where the first N cycles are needed to initialize the deserializer. Figure 4. waveform example To ensure timing-safe operation, the deserializer has an update stage that captures (in parallel) the data contained in the shift register. Once the test data is loaded into the update register on the N th deserializer clock pulse, its output is constant for the next N cycles. This allows its content to be shifted into the internal scan chains in a skew-safe manner and also prevents switching activity within the decompressor while the deserializer shifts in new data. Pattern Generation One of the key aspects of the architecture is that test generation is performed using an N-bit wide parallel scan interface that bypasses the de/serializer registers. Figure 5 shows how compressed patterns are generated using the parallel interface (N-scanin / N-scanout), and then simply retargeted to a serial interface (e.g. 1 scanin / 1 scanout or 2 scanin / 2 scanout). Each scan cycle of the parallel interface is translated into a load/unload of the deserializer/serializer registers. Figure 6 shows some details of the serial and parallel interfaces. There is a multiplexor at the output of each deserializer bit whose select is controlled by the _enable and _parallel_access signals. When _parallel_access is true, the parallel scan pin feeds the decompressor and when false the deserializer feeds the decompressor. This is allowed only when _enable is true; when false the logic is made testable as part of the chains. Note that these two signals can be internally generated test signals and do not need to be dedicated chip I/Os. (b) Figure 5. (a) test generation performed using parallel interface (b) Patterns converted to Serial Interface (a) The parallel interface patterns can be applied directly at the Automatic Test Equipment (ATE) and/or retargeted and applied using the serial interface during multi-site test, or possibly used for board/system test. If the design does not contain an N-bit wide parallel scan interface, such an interface can be modeled just for test generation purposes. Figure 6. Serial and Parallel Interfaces Key advantages of the parallel interface are: It decouples the mainstream DFT verification and pattern generation process from the hardware. The bulk of the DFT verification can be done independent of and the logic is verified only in the context of post-atpg pattern retargeting. Errors in the implementation would not require expensive iterations of the mainstream DFT and ATPG flows. It greatly reduces the correlation that would otherwise be caused by only very few scan pins driving the compression logic directly. The internal scan configuration is identical between the two interfaces (figure 6) and hence the pattern quality is identical as long as the patterns can be retargeted. Debug and diagnostics are minimally impacted, as tools can continue to diagnose using the parallel interface Paper 4.2 INTERNATIONAL TEST CONFERENCE 3

4 patterns by simply translating serial pattern fails to the corresponding cycles in the parallel patterns. Several verification checks of the logic are necessary to ensure validity of the retargeted patterns. This is done prior to the pattern conversion process and some of the key checks are as follows: Verify the switch to serial interfacee and that the deserializer is feeding the decompressor. The initial circuit state must be identical between the two interfaces, except for _parallel_access. In the serial mode, there must be a sensitized path between the Serial scanin (scanout) pin and the first bit of the deserializer (serializer). Verify clocks to the registers are generated correctly. Ensure the deserializers and serializerss are functioning as shift registers in the serial mode. Map each parallel scan in (out) pin to its corresponding deserializer (serializer) pin. Programming Mask and Clock Control Registers provides a flexible architecture that can deliver data to general purpose test data registers. Two classical examples are the X-Mask registers [2] and the side-scan registers for programming the On-Product Clock Generation (OPCG) circuitry [11]. Figure 7 shows the paths to load the X-mask and OPCG programming registers, which are both control-only registers, via the deserializer(s). The ATPG test patterns load these registers using the parallel interface and the pattern conversion process transforms the data to now be loaded via the deserializer. times faster than the scan frequency. Note that only the deserializer and serializer registers will be shifting at the faster frequency, while the internal chains will still see a clock pulse every N cycles, i.e., at the slow frequency. Additionally, experimental results demonstrate that the parallel interface helps to achieve a lower pattern count due to reduced data correlation. Hence significant overall test time reduction can be achieved, and using a faster clock makes the test time reduction even more appealing. 4. Hierarchical Test of Embedded Cores Figure 8 shows applications of in a hierarchical System-on-Chip (SoC) environment. The registers enable independent controllability and observability of each embedded core, including even the mask and OPCG data. Identical cores can share the same deserializer(s) but must have separate serializers. This ensures a defect in all instances of a core is not masked due to aliasing if the outputs of the identical instances were simply XORed together. Even heterogeneous cores can be tested simultaneously, although there can be inefficiency if cores with highly unbalanced scan length are grouped together in the same test session. Note that even though the heterogeneous cores shift simultaneously, they can have different launch-capture clocking sequences since their OPCG programming registers can be loaded independently. Since the logic can be placed close to its core, the wiring congestion is reduced since only the few wires to/from each block need to be routed. Yet another advantage is that having a single serialized output per core allows a means to easily tell which cores are bad. Figure 7. Using the serial interface to load the (a) X-Mask and (b) OPCG programming registers The mechanism to activate the different states scan load, mask load, OPCG load is transparent t to the pattern conversion process; it simply needs to be provided the sequences that set up these states and the sequences are then embedded in the serial patterns. These sequences are autoneed for custom generated within the tool, unless there is a sequences, e.g. to manipulate configuration registers. Test Application Time Impacts Since each shift of the internal scan chains requires a complete load (unload) of the N-bit deserializer (serializer), the overall scan shift time for a single test pattern is N times longer. But this overhead can be reduced if the deserializer and serializer registers are clocked faster than the regular scan shift frequency. Typical ATE can supply clocks 4-6 Figure 8. application in hierarchical test also greatly simplifies the core/ip design flow since the core s scan bandwidth can be independent of the SoC TAM bandwidth constraints. The core can be designed and patterns generated using a M-bit wide scan bus. If the SoC TAM to the core is only 2 bits wide, these 2 pins could each drive M/2-bit wide deserializers. The M-wide core patterns can thus be retargeted to the 2 SoC scanin pins via the Serial interface. If the TAM is 3-bits wide, then each deserializer would be M/ /3 bits wide. This enables an IP reuse methodology where the patterns can be generated once and simply retargeted to a SoC TAM configuration with the help of. Addressing Power Issues during Scan Shift in SoCs Instantaneous switching during scan can cause power issues in SoCs, as millions of flops may be shifting simultaneously. This can be partially addressed by limiting the number of Paper 4.2 INTERNATIONAL TEST CONFERENCE 4

5 cores tested simultaneously, though at a test time cost. But in a scenario where the SoC has unwrapped cores and the SoClevel glue logic is being tested (inter-core test), all the cores would be shifting simultaneously, likely causing severe power issues. This can be addressed by leveraging a novel aspect of the clocking logic. Once the update register latches the stimulus data, it holds that data for the next N cycles. Generally only one of the next N clock cycles is used to shift all the cores. Instead, the next N-1 clock cycles can be leveraged to interleave the scan shift of multiple cores. core is tested at a time. To support the test schedule where all the cores are participating (inter-core test), a total of 24 deserializer (serializer) bits are distributed over the 2 scanins (scanouts), resulting in two 12-bit deserializer and two 12-bit serializer registers as shown in Figure 10(a). (a) Testing inter-core logic between all three cores Figure 9. Low power interleaved scan clocks Figure 9 shows how such staggered clocking can be easily achieved by the clock controller without any impact to the overall test time. The net effect is that the chains in the first core will shift for one cycle, followed by the chains in the second core and so on. After all the cores have shifted one cycle, the first core shifts again and this process repeats till all the cores have completed shifting for the length of the longest scan chain. Such shifting is possible since each core is independently controllable and observable via its corresponding deserializer/serializer registers. Essentially, the total number of deserializer (serializer) bits must equal the total scanins (scanouts) across all the cores. Interleaved shifting thus avoids shifting all the cores simultaneously and hence significantly reduces instantaneous scan power issues. This novel approach addresses global scan power issues and ATPG techniques can still be leveraged to address localized power issues within the cores. Silicon results of an interleaved implementation on a SoC with 11 unbalanced partitions show almost 10X reduction in peak power draw during scan at the tester. Re-configurability of the hardware plays a key role in eliminating the test time or hardware overhead that could otherwise be incurred when multiple cores are present. Figure 10 shows a hierarchical test scenario with three cores and a tester limit (e.g., during wafer probe) of 2 scanin and 2 scanout pins. Each core has 8 scanin and 8 scanout pins, for a total of 24 scanins and 24 scanouts across the three cores. There are multiple test schedules for inter-core testing, e.g., all three cores or only two cores are participating at a time. Interleaved Smartscan can be used to avoid shifting all cores simultaneously and thus reduce scan power. Additional test schedules are needed for intra-core testing, where only one (b) Testing the logic between cores 1 and 3 Figure 10. Supporting multiple test configurations with re-configurable For a test schedule with two cores participating at a time, only 16 total deserializer bits are needed to load the scanins for these cores. The logic can now be configured as shown in Figure 10(b) to only utilize the first 8 bits of each register, and the remaining 4 bits (farthest away from serial scan pins) are physically present but are unused in this mode of operation. Without such flexibility in the hardware, a scan cycle in this schedule would require completely loading each 12-bit deserializer register, resulting in almost 50% test time overhead compared to using two 8-bit registers. For a test schedule where a single core is being tested, the logic can be configured to appear as two 4-bit wide deserializer and serializer registers. Note that Figure 10 does not show the multiplexing logic that is needed to route the appropriate deserializer and serializer bits to the cores being tested in each schedule. But this overhead would still be less than the alternatives in nonconfigurable de/serializer architecture, i.e., either inserting additional sets of registers of varied lengths for the different test schedules or incurring a significant test time penalty. Paper 4.2 INTERNATIONAL TEST CONFERENCE 5

6 5. Physical & Timing Considerations Scan path pipelining has become de facto in SoCs to deal with the long wiring or the several levels of XOR logic gates for compression. While it may seem that the deserializer and serializer flops can be considered as pipelines, these flops would most likely be clustered together and may be located far away from the scan pins on the SoC boundary. Hence pipelines are necessary for timing closure and are sometimes present even within the chip I/O pads. Figure 11. Pipeline locations in Compression mode Figure 11 shows the different locations where pipelines may be present and need to be supported by the architecture. The internal pipes and embedded pipes (present within XOR logic) are transparent to s post- ATPG pattern conversion process as these pipes behave identically during the parallel and serial modes of operation. The external pipes present multiple challenges to the pattern conversion process and can be categorized into two types, Type-1 and Type-2. Type-1 external pipes are those on the serial scan pins, e.g. SI1 and SO1. If the design does not have real parallel scan pins, Type-1 external pipes are bypassed in the parallel mode of operation; in the serial mode they are on the path to/from the registers. As shown with the example in Figure 12, the first N clock cycles of the serialized vector are used to prime the deserializer flops with the stimulus for one bit-slice of the scan chains. During these first N cycles, the clock to the internal scan chains is suppressed. Since p pipes (p N) are present, the padded vector shows that the clock controller suppresses the clock to the internal chains for the first 2*N cycles. After 2*N clock cycles the pipes contain 01 and the deserializer contains 111. From 2*N+1 cycles onwards, the internal clocking resumes as shown in the figure. Every N cycles, the deserializer is loaded with the values for current bit-slice of the scan chains, while the pipes contain partial values for the subsequent bit-slice. A novel feature of this scheme is that the conversion process can handle 0 p N external pipes without any change to the hardware or requiring pattern re-generation. This is advantageous if pipes need to be added or removed during timing closure. In general for p 0, the controller needs to suppress the internal clock for the first (ceil((n+p)/n)*n) cycles. The increase in test application time to support pipelines is negligible, e.g. it is only N additional cycles for 0 p N. Figure 12. Pattern conversion to handle Type-1 external pipes that are bypassed during ATPG Though not shown in the example, Type-1 external pipes on the output side can be handled similarly such that every N cycles the measure at the serial scan out consists of values left in the output pipes and partial values from the current serializer content. The additional consideration is that when unloading the response data for a test pattern, the first few cycles will measure the response data left in the output pipes from the previous test. This necessitates that the pipes must not change value during the launch-capture cycles. Type-2 external pipes, i.e. those on SI2 through SI5 and SO2 through SO5, are present only in the parallel interface (pattern generation mode) and are not accessible during the serial mode of operation. The content of the output pipes can be ignored since ATPG does not measure a known value in them. But when unbalanced scan chains are present and scan load/unload are overlapped, the data in the input pipes goes through the shorter chains and influences the compressed output stream for the current test. Hence the data in the input pipes needs to be serialized appropriately to ensure the pattern quality is unchanged. Once again assuming the pipes do not change value during launch-capture, the columns in the ATPG stimulus data that pertain to the input pipes are serialized and appended to the beginning of the next serialized test pattern. This ensures that the pipeline content factored into the scan output stream computation of the current test is available before the overlap with the next test s stimulus. 6. Integration with IEEE and P1687 The building blocks of a typical implementation are shown in Figure 13. The Controller block produces the deserializer/serializer clock, update clock, scan chain shift clock, mask load clock and serializer scan enable control. A deserializer block with an update stage feeds the decompressor and serializer block serializes the output of the compressor block. Paper 4.2 INTERNATIONAL TEST CONFERENCE 6

7 Figure 13. building blocks The block can be directly controlled from ATE or controlled from an Tap controller by decoding the states of the Tap FSM as shown in Figure 14(a). The serial vs parallel operation is determined by an instruction decode. The test protocol states of scan data shift, mask load shift and launch-capture are decoded from TAP states. The per- scan cycle mask enable is extracted from the serialized scanimplementation. in data. Figure 14(b) shows a possible logic (a) (b) Figure 14. (a) Mapping controls on to JTAG states (b) Glue logic to support TAP controlled The advantage of the above approach is that the die-level test patterns can be easily re-applied at the board-level using a 5 pin TAP interface. Furthermore, the serializer and deserializer can be treated as IEEE P1687 (ijtag) [12] compatible test data instruments and integrated with other P1687compatible hardware on the die. The low pin interface is also valuable as a narrow test access mechanism on 3D stacked dies. 7. Experimental Results Experiments were conducted on several industrial designs to show the effectiveness of the approach. TAM widths of 1 SI - 1 SO or 2 SI - 2 SO were used. For each design, the following methodology was used: 1. Generate patterns in (bypass) mode and in a conventional XOR Compression mode using the specified TAM width. 2. Generate patterns in mode using the ATPG parallel interface and convert them to the serial interface. The number of internal scan chains (between decompressor and compressor) stays the same as the Compression mode. A deserializer (serializer) of 4, 6 or 8 bits is connected to each TAM scanin (scanout) pin. 3. In both the Compression and modes, the coverage will likely be less than the mode due to data correlation effects. Generate top-off patterns for the Compression and modes to reach the coverage targets. 4. Test application time for the Compression mode will be the number of cycles needed to apply the Compression patterns plus the cycles needed for the top-off patterns. Test time for is computed similarly. Figure 15 shows the results for a single design with 1 SI and 1 SO pin and an 8-bit deserializerr in mode. As seen from the chart plotting the coverage in each mode, the coverage achieved with just the Compression patterns is, at 82%, far below the target coverage of 99.2% (coverage in mode). This is primarily due to the high data correlation caused by the single SI pin driving a large number of internal scan chains. A large number of top-off patterns are needed to bridge the coverage gap and reach the target coverage. The parallel interface achieves coverage of 98.7%; only 10 top-off patterns are sufficient to meet the coverage target. The test application times for each mode are compared in Figure 15. The test application time for Compression is relatively high since it is dominatedd by the time for the large number of top-off patterns. The test time for each pattern is 8 times longer than a single Compression pattern due to the deserializer and serializer shift. In spite of this, the total test time on a design is still 3.5X less than Compression since there are much fewer top-off patterns required. If the tester can supply a clock that is up to 8X faster than the scan frequency, then the overhead due to the deserializer shifting is nullified and the total test time is further reduced. Paper 4.2 INTERNATIONAL TEST CONFERENCE 7

8 Figure 15. Coverage and Test Time Impacts for a design containing an 8-bit deserializer Comprehensive results for four industrial designs of varied sizes are shown in Table 1. Designs A, B and C have one deserializer and one serializer in the mode, with 8-bit wide registers in design A, 4-bit registers in design B and 6-bit registers in design C. Design D has two deserializer and two serializer registers, each 6-bit wide. For each design, results were generated for 4 different modes, XOR Compression, and a variant of where the tester clock is faster (by 4, 6 or 8X) than the scan clock. The parallel interface used for ATPG in the modes is the total number of deserializer bits available, i.e., number of TAM scanin pins multiplied by the width of each deserializer register. Target compression ratio of 100X and X-masking were implemented for all designs. For simplicity in generating the Compression results, an additional Mask Enable (CME) pin was used just for the Compression mode. Without X-masking, the Compression results for these designs would have been worse. For, a deserializer bit and its corresponding scanin in the parallel interface serve as CME. Columns 7 and 8 show the initial coverage in each of the 4 modes and the number of patterns to achieve that coverage. Column 9 shows the number of top-off patterns needed to match the coverage in mode. The last two columns present the percentage reduction in test application time and the test data volume reduction when compared against. Design A B C D Table 1. Test Application Time (TAT) and Test Data Volume (TDV) reduction for different designs Testmode Num Flops TAM Width Total De/Serializer Width -- Effective ATPG (Parallel) Interface Initial Fault Coverage (%) Initial Num Patterns Num Top-off Patterns TAT Reduction TDV Compression K SI, 1 SO Compression 1 SI, K % 1.4X 7K 1 SO K % 4.8X 8 bits 7 SI, 8 SO K % 4.8X (@ 8x Freq) K SI, 1 SO Compression 1 SI, K 7.8K 56.4% 2.3X 97K 1 SO K % 25.7X 4 bits 3 SI, 4 SO K % 25.7X (@ 4x Freq) SI, 1 SO Compression K % 1.4X 1 SI, 5.5K 1 SO K % 4.3X 6 bits 6 SI, 6 SO K % 4.3X (@ 6x Freq) K SI, 2 SO Compression 2 SI, K 4.8K 75.4% 4.0X 586K 2 SO K % 19.6X 12 bits 12 SI, 12 SO K % 19.6X (@ 6x Freq) Paper 4.2 INTERNATIONAL TEST CONFERENCE 8

9 For all the designs, the coverage in Compression mode is significantly lower than the target coverage and hence requires a large number of top-off patterns, thus limiting the actual compression achieved. The parallel interface in mode enables ATPG to get very close to the target coverage and hence only requires a handful of top-off patterns. As can be seen, while conventional XOR compression can provide some benefit compared to, its effectiveness is greatly limited at low bandwidths. is able to overcome the bandwith limitations to provide better overall compression without any degradation in pattern quality. If the tester can supply a clock that is 4 to 8 times faster than the scan frequency, the overhead due to serial scan shifting in can be eliminated, providing further reduction in test application time. Some of the ongoing development involves improving debug and automatic diagnosis of XOR-based. Optimization of scan structure integrity tests for test modes is another area of work. We are also looking at a number of enhancements in the interleaved area to reduce the scan shift power with the optimal hardware and software support. Finally, combining techniques with embedded MISR structures with parallel or serial signature observation provides further opportunities for test data compression. 8. Conclusions This paper presents a generalized TAM architecture called that allows efficient distribution of compressed test data streams to and from embedded cores. Some of the key contributions presented are: Support for generalized XOR and MISR-based compression schemes. This includes serialization of X- mask data and OPCG control data for multiple domains. The ATPG patterns generated at the core-level using the parallel compressed data bus are re-used at the SoClevel and serialized concurrently enabling seamless multi-core support without any scripting. There is no reduction in test coverage or compression ratio between the parallel and serial vector sets. Experimental results show that the parallel interface achieves up to 98% reduction in test time and 25X reduction in data volume. The results are significantly better than conventional compression with very few pins. The mainstream DFT flow verification, ATPG, diagnostics is minimally impacted as the serialization is built into the backend ATPG process. is compatible with IEEE or IEEE P1687 interfaces, allowing this scheme to be used at the board or system level and for 3D stacked dies. A novel extension of the DFT hardware permits low power interleaved scan shifting that reduces instantaneous scan switching by a large factor. 9. Acknowledgements The authors would like to acknowledge and thank Jordy Asher, Brion Keller, Ripu Singh, Rick Schoonover, Leon Palmer and Balveer Koranga for their valuable contributions to this work. 10. References [1] C. Barnhart et al., OPMISR: The foundation for compressed ATPG vectors, Proc. IEEE International Test Conference, 2001, pp [2] V. Chickermane, B. Foutz, & B. Keller, Channel Masking Synthesis for Efficient On-Chip Test Compression, Proc. IEEE International Test Conference, 2004, pp [3] S. Mitra, K.S. Kim, X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction, Proc. IEEE International Test Conference, 2002, pp [4] P. Wohl, et al, Minimizing the impact of scan compression, Proc. VLSI Test Symposium, 2007, pp [5] B. Koenemann, et al, A SmartBIST variant with guaranteed encoding, Proc. IEEE Asian Test Symposium, 2001, pp [6] C. Barnhart, et al, Logic DFT and Test Resource Partitioning for 100M Gate ASICs, Test Resource Partitioning Workshop, [7] A. Khoche, et al, A new methodology for improved tester utilization, Proc. IEEE International Test Conference, [8] A. Chandra, R. Kapur, Y. Kanzawa, Scalable Adaptive Scan (SAS), Proc. Design, Automation & Test in Europe (DATE), 2009, pp [9] J. Moreau, et al, Running scan test on three pins: yes we can!, Proc. IEEE International Test Conference, [10] A. Sanghani, et al, Design and implementation of a timedivision multiplexing scan architecture using serializer and deserializer in GPU chips, Proc. IEEE VLSI Test Symposium, 2011, pp [11] B. Keller, et al, Low Cost At-Speed Testing using On- Product Clock Generation Compatible with Test Compression, Proc. International Test Conference, [12] IEEE P Paper 4.2 INTERNATIONAL TEST CONFERENCE 9