VID (Voltage ID) features require timing analysis on even more corners

Transcription

1 Mehmet Avci

2 Number of Corners for Typical Part Introduction The number of signoff PVT corners is increasing VID (Voltage ID) features require timing analysis on even more corners Designers try to reduce the number of signoff PVT corners by choosing a subset of the possible corners based on previous node or experience A subset of corners can typically lead to conservative results, but not always Stratix IV Stratix V Arria 10 Stratix 10 Future Family (*12 corners for future family is the current projection of number of PVT corners) 2

3 Observations Typical designs have many timing paths that are far away from being critical both from setup and hold timing point of view This fact can help us to avoid doing detailed timing simulations for such paths, if we could conservatively approximate the delays in such paths The difficulty is to obtain such approximations without running simulations Assume that we were able to approximate delays easily and conservatively, then: If timing is met with such approximated delays, then the timing will be definitely met using simulation because of conservative delays If a timing path does not meet timing with approximated delays, we can fall back to accurate timing simulation to reanalyze the path in consideration to see if the timing failure was actually real 3

4 Background/Literature There is a proposed method [1] in which a full timing run is performed for small number of corners, and partial timing run are performed for others These results are then combined to find the worst-case hold slacks over all corners. In [2], authors determine that only 3 critical corners, out of the 12 corners provided by foundry, can be used with ± 2-5 % variation One for hold check and two for setup check. With this approach, final STA is limited to only these critical corners [1] S. Onaissi, F. Taraporevala, J. Liu, and F. N. Najm, "A fast approach for static timing analysis covering all PVT corners," ACM/IEEE 47th Design Automation Conference (DAC-2011), San Diego, CA, pp , June 5-9, 2011 [2] V. K. Singh, Improvement in Static Timing Analysis for Early TA-Signoff Closure in SoC flow at Very Deep Submicron Nodes, Master thesis, Indraprastha Institute of Information Technology, New Delhi, India,

5 Background/Literature Issues with such approaches: The approach in [1] is not recommended to be used for final timing results, which reduces its application to Intel PSG devices, as many PVT corners are specifically used for final sign-off timing analysis Even though running a few predetermined corners as in [2] can lead to acceptable results in some cases, this is not the case for all different situations. Authors in [1] show that for setup analysis, industry practice of choosing a small set of corners can indeed capture many of the worst-case slacks over all corners. On the other hand, they also show that it is not possible to choose such a set for hold analysis. 5

6 Proposed Solution Proposed approach can be summarized in 5 main stages: Offline Scaling Calculation: Find experimentally the scaling between corners for cell and routing resources separately, and save them. Default Corner Analysis: Analyze default corner using full accurate delay annotation and save the all the data path delays for future use. Non-default Corner Clock Path Analysis: Analyze clock paths of the designs in full accuracy mode. Non-default Corner Data Path Analysis: Use the crude scalings obtained from offline scaling calculation to scale the data path delays found in default corner analysis. Non-default Corner Timing Analysis: Use above calculated delays and perform timing analysis. If timing is met, then the results are good, as the scalings are pessimistic. If the timing is not met, then we fall back to full accuracy timing simulation, and reanalyze. 6

7 Exceptions to scaling approach We use simulated delays for all of the clock network Helps us avoid double penalty due to pessimistic scalings, as clock delays are used both in arrival and required paths For constraint arcs (setup/hold checks) and delays < 100ps (in default corner), we use an absolute derate, rather than a relative derate 7

8 Example Delay Calculation using Relative Scalings Max Min Relative Scaling Original Corner Delays (ps) New Corner Scaled Delays (ps) New Corner Simulated Delays (ps) Introduced Pessimism (ps) Scaled Delay: 300/176 Sim. Delay: 260/220 8

9 Example Delay Calculation using Absolute Scalings Max Min Absolute Scaling Original Corner Delays (ps) New Corner Scaled Delays (ps) New Corner Simulated Delays (ps) Introduced Pessimism (ps) 5 15 Scaled Delay: 90/60 Sim. Delay: 85/75 9

10 Clock Node Statistics Design Clock Nodes Total Nodes Comparison Design % Design % Design % Design % Design % 10

11 Relative scalings between corners Corner Scaling Type Scaling wrt. Slow 100C Cell Max 1.10 Slow 0C Cell Min 0.95 Routing Max 1.04 Routing Min 0.79 Cell Max 0.72 Fast 100C Cell Min 0.51 Routing Max 0.94 Routing Min 0.68 Cell Max 0.70 Fast 0C Cell Min 0.50 Routing Max 0.75 Routing Min

12 Absolute Adjustments (delays < 100ps) Corner Delay Type Scaling wrt. Slow 100C in ps Slow 0C Fast 100C Fast 0C Cell Max 11 Cell Min -3 Routing Max -3 Routing Min -13 Cell Max 0 Cell Min -38 Routing Max -7 Routing Min -25 Cell Max 0 Cell Min -39 Routing Max -9 Routing Min

13 Absolute Adjustments (constraints) Corner Delay Type Scaling wrt. Slow 100C in ps Slow 0C Fast 100C Fast 0C Setup Max 10 Setup Min -22 Hold Max 8 Hold Min -60 Setup Max 189 Setup Min -45 Hold Max 310 Hold Min 9 Setup Max 199 Setup Min -47 Hold Max 320 Hold Min 8 13

14 Percentage of paths that require simulation Slow 0C Fast 100C Fast 0C Design Name Setup Hold Setup Hold Setup Hold Design 1 15% 2% 2% 20% 3% 25% Design 2 13% 4% 3% 17% 3% 22% Design 3 11% 4% 4% 21% 3% 23% Design 4 18% 1% 1% 19% 2% 23% Design 5 10% 3% 2% 17% 2% 20% 14

15 Runtime Comparison Total Runtime (in seconds) Design Our Method Simulation Comparison Design % Design % Design % Design % Design % Average 32.6% * Results don t include the runtime for default corner simulation 15

16 Slacks in ns Slack Distribution Comparison (design 1) Original Corner: Slow 100c, New Corner: Slow 0c Average Slack Difference between New Corner Scaled and New Corner Simulated = 641ps New Corner Simulated Slacks New Corner Scaled Slacks Original Corner Simulated Delays 16

17 Future Work Different scalings for rise/fall delays would improve accuracy/runtime Get more detailed scalings per FPGA resource (such as individual wires) This should improve the runtime and the accuracy of our approach Guarantee slack conservatism rather than relying on experimental results Evaluate the approach using Stratix 10 and non-fpga timing systems Scaling based delays could confuse the user (because these delays will have large min/max) It would be best to mark these delays as scaled to avoid such confusion Or one could invoke simulation incrementally for the paths that user is interested 17

18 Conclusion Presented approach doesn t result in circuit performance degradations as opposed to the approaches that combine multiple corners into one by conservatively bounding the delays Arria 10 experimental results show that only a subset of timing paths need to be simulated Since the scalings that are used are pessimistic, the experimental results show that the slacks obtained using our approach are conservative Our approach also makes analyzing additional corners fast, helping designers stop worrying about which corners they should hand pick to do signoff analysis 18

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