PARAMETER SYMBOL MIN MAX Address Access Time

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1 TECHNICAL NOTE TN TIMING SPECIFICATION DERATING FOR HIGH CAPACITANCE OUTPUT LOADING Introduction Memory systems are varied in the number of controllers, memory, and other devices that may share a common data bus. Cellular phones, for example, may have several Micron memory devices and a Micron image sensor connected on the same data bus as the controller as well as one or two display devices. When a system design requires several devices to be connected on a common data bus, the designer needs to know how the additional loads affect system timing to calculate system speeds and timing margins. This technical note describes how to create capacitance derating data for Micron products that can then be used in preliminary evaluations of system timing. Micron s CellularRAM version 1.0 product family is used here as an example, but the process can be applied to any device. AC Timing Specifications Timing specifications for Micron products are usually tested under a single load condition. For this example, the values for the READ timing specifications shown in Table 1 are derived by testing under the load conditions illustrated in Figure 1. The output load is specified as 30pF with a pull-up resistor to VCCQ and a pull-down resistor to GND. The page mode READ timing diagram, Figure 2 on page 2, is a graphical representation of the specifications in Table 1. For the timing specifications and diagrams for any Micron device, please refer to the specific data sheet on Micron s Web site ( Figure 1: Output Load Circuit for Testing AC Parameters Device Under Test C1 VDDQ = 1.8V R1 R2 Table 1: READ Cycle Timing Specifications PARAMETER SYMBOL MIN MAX Address Access Time t AA 70 Page Access Time t APA 20 LB#/UB# Access Time t BA 70 Chip Select Access Time t CO 70 Output Enable to Valid Output t OE 20 Page Cycle Time t PC 20 Read Cycle Time t RC 70 TN0017.fm - Rev. A 5/04 EN Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON S PRODUCTION SHEET SPECIFICATIONS. ALL INFORMATION DISCUSSED HEREIN IS PROVIDED ON AN AS IS BASIS, WITHOUT WARRANTIES OF ANY KIND.

2 Figure 2: Page Mode READ Cycle Timing Diagram ADDRESS A[20:4] t RC ADDRESS ADDRESS A[3:0] CE# t AA t PC LB#/UB# t CO t BA OE# t OE t APA -OUT High-Z High-Z DON T CARE UNDEFINED Determining Transition Times Transition times are measured from the beginning of the transition to VCCQ/2. These values increase because the time it takes for the output to transition is longer when an output drives into a higher capacitance load. Not all the timing values in Table 1 will increase with higher capacitive loads. For example, the page cycle time ( t PC) and read cycle time ( t RC) are independent of the output load. The measurements that will increase with higher capacitive loads are those that measure the I/O buffer driving the load: Address access time ( t AA) Page access time ( t APA) LB#/UB# access time ( t BA) Chip select access time ( t CO) Output enable to valid output ( t OE) Memory Diagram To find out how much longer the output transition will take, let s examine a simple model. Memory devices can be thought of as having a core component and an I/O buffer as shown in the simplified memory diagram of Figure 3. Figure 3: Simplified Memory Diagram Address Control Memory Access Blocks Internal Data Path I/O Buffer Load Using this model, a memory READ cycle can be described as two sequential events. First, when there are changes in address or control, the memory access blocks read the data stored in the memory and provide the data on the internal data path. Second, when the data changes on the internal data path, the I/O buffer drives that change onto the DQ bus and out to the load. If the memory system s load capacitance is larger than the test load capacitance, then the overall access time is longer than the specifications listed in the data sheet. However, the timing of the memory access block is not affected at all. The longer access time is only a function of the I/O buffer and the load. The data sheet does not provide the memory access blocks and I/O buffer timing measurements separately. The designer needs to calculate the timing from the I/O buffer to the load to create derating data. DQ TN0017.fm - Rev. A 5/04 EN Micron Technology, Inc. All rights reserved.

3 Output Modeling The first step in calculating the derating data is to simulate the I/O buffer with the load value specified in the data sheet, which in this example is 30pF with pullup and pull-down resistors. The value extracted from the simulation represents the I/O buffer to the load portion of the data sheet timing specifications. This number becomes the baseline for comparison of all other simulation results. Simulations can be run using either the SPICE or IBIS models available on Micron s Web site, To calculate the timing change for higher capacitive loads, the simulation conditions must be changed to a higher load capacitance and the simulation run again. As is the case for the first simulation performed, the timing extracted from the simulation represents only the I/O buffer to the load portion of the timing. The difference between the two measurements is the result of the higher load capacitance. A full derating table or curve can be created from multiple simulations showing the effects of higher capacitance loading. An Example The topology shown in Figure 4 was simulated with the Micron CellularRAM IBIS model to illustrate the method for creating the derating curve. The value of C1 varied from 30pF (standard load) to 100pF in 10pF increments. To get the worst case numbers, the corner conditions are set to slow/weak conditions. That means that VCCQ is 1.7V, junction temperature is at T J (MAX), and the process corner is set to slow. The resulting family of waveforms is shown in Figure 5 on page 4. Figure 4: Test Circuit for Simulation of Micron s CellularRAM Version 1.0 I/O Buffer C1 VDDQ R1 R2 TN0017.fm - Rev. A 5/04 EN Micron Technology, Inc. All rights reserved.

4 Figure 5: Family of Waveforms for C1 Ranging from 30pF to 100pF Because the rising edge may be delayed more or less than the falling edge, both edges must be measured to find the maximum delay time that either edge arrived at VCCQ/2. Using the 30pF load as the baseline for all other timing comparisons, the maximum additional delay of the rising or falling edge is shown in Table 2. The derating curve, Figure 6 on page 5, is plotted from that data. Table 2: Load Capacitance LOAD CAPACITANCE (pf) ADDITIONAL DELAY (ns) TN0017.fm - Rev. A 5/04 EN Micron Technology, Inc. All rights reserved.

5 Figure 6: Capacitance Derating Curve for Micron s CellularRAM Version 1.0 Additional Access Time (ns) Capacitive Load (pf) System Application The derating information collected can be used as a first estimate of timing performance when the device drives a higher capacitance load. For example, if a system load is 65pF, the capacitance derating curve indicates that the worst case additional access time is 2.55ns. This value would be added to those timing specifications that measure the I/O buffer driving the load as listed on page 2. As a result, t AA, which is normally 70ns MAX, would be 72.55ns. Caveat While derating curves for higher capacitive loads can be derived using the method described here, those curves have limits in their application and should only be used as a guideline, not as a design validation. To model a system, especially one that has a high capacitive load, without using transmission lines to represent the proper system topology and the printed circuit board traces is to invite error into the system design. The system should be simulated to verify that all parts operate properly under the system s design and use conditions. Conclusion Using IBIS or SPICE models of the I/O buffer, an accurate derating curve can be constructed to show the additional delay when the output drives a capacitive load greater than the capacitance specified in the data sheet. The derating curve can be used for a first estimate of system performance. To accurately verify system timing, the system topology and loads should be simulated S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com, Internet: Customer Comment Line: Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc. inside the U.S. and a trademark of Infineon Technologies outside the U.S. TN0017.fm - Rev. A 5/04 EN Micron Technology, Inc. All rights reserved.