Performing STA. Learning Objectives

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1 Performing STA Learning Objectives UNIT 45 minutes Unit 8 You are provided with a design netlist that does not meet timing. You are also provided with another set of sub blocks that were improved for timing possibly at the expense of area. As an STA Engineer, you are in charge of providing analysis results to the Synthesis Engineer and find if you can meet timing using some or all of the improved blocks. After completing this lab, you should be able to: Use the Constraints Report to determine the scope of (how many) violations Use the bottleneck report to identify blocks in your design that are candidates for improvement Find the larget violation using Timing report and analyze the fanout, capacitance, transition time and delay along the worst violating timing path Conduct What if analysis by using improved blocks in place of the bottleneck blocks with the help of swap_cell command and look for any timing improvement Repeat the above steps until there are no setup violations in the design Document the changes to your design due to swap_cell commands using write_changes Performing STA 8-1 Synopsys S36

2 Getting Started Directory structure and relevant files../libs/ Directory with Library files core_slow.db Cell library for setup check Lab8_STA/.synopsys_pt.setup Reports/ Scripts/ read_solution.pt reg2reg_solution.pt io_solution.pt Source/ Verilog/ RISC_CORE.v DB_Improved/ *_new.db Directory to perform this lab PrimeTime Setup Report files directory Script files directory Script provided to read a design Script to constrain Reg2reg paths Script to constrain IO paths Verilog design directory Verilog design netlist Improved sub blocks directory Improved sub Block DB files If you need help Use the lecture material, SOLD or the Quick Reference Guide. pt_shell> help *bottle* pt_shell> help verbose report_bottleneck pt_shell> report_bottleneck help pt_shell> man report_bottleneck pt_shell> printvar *_path pt_shell> echo $link_path pt_shell> man link_path 8-2 Performing STA

3 Performing STA Completely Constrain the design using the provided scripts Analyze Scope of violations using Constraints Report Analyze Bottleneck blocks using Bottleneck Report Analyze detailed timing using Timing Report swap_cell from *_new.db files to improve timing. Document the changes with write_changes Your goals are to: - Meet timing on the RISC_CORE design by utilizing some or all of the improved sub blocks from DB_Improved/*_new.db files - Use the Constraint, Bottleneck and Timing Reports to guide your decision as you are trying to find improvement(s) - Document the changes to the design in terms what improved blocks have been used Performing STA 8-3

4 Background You are provided with the gate level netlist of the RISC_CORE design together with the following specifications that you will apply. You are provided with an improved (for timing) version of all of the sub blocks. The directory for performing this lab is Lab8_STA Specifications Library File name: core_slow.db Library name: ssc_core_slow Timing Goals Clock = 200 MHz, 50% duty cycle (Clk) Input arrival Time on all data input ports w.r.t Clk= 2 ns Output setup time on all output ports w.r.t Clk = 2 ns Clock Attributes Skew = 460 ps, Network latency = 0.4 ns, Source latency = 2 ns, Transition = 1 ns Operating 125 C, 1.62 V as provided by the library operating environment condition: slow_125_1.62 Wire load model and Use the largest available in the library: mode 320KGATES and top mode Cell driving Inputs fdf1a1 (pin Q) Load (Capacitance) Pin capacitance: load_of ssc_core_slow/and2b3/b * 10 on output ports in pf Wire capacitance: 0.00 Table 8-1: Design constraints NOTE: A solution script is provided at the end of this write-up, but, it s a lot more fun to perform this lab interactively using the instructions below 8-4 Performing STA

5 Task 1. Constrain your Design in PT 1. Make sure that your current directory is./lab8_sta ; Invoke pt_shell. unix% pt_shell tee lab8.log 2. Verify the aliases cs and so have been defined. (in the.synopsys_pt.setup file) pt_shell> alias cs pt_shell> alias so 3. Read the design netlist and link the design using the provided script. Perform syntax check before using the script pt_shell> set SCRIPT_FILE./Scripts/read_solution.pt pt_shell> cs $SCRIPT_FILE; # Ensure there are no errors pt_shell> so $SCRIPT_FILE 4. Perform syntax check and apply the script to constrain all the register to register paths in the design pt_shell> set SCRIPT_FILE./Scripts/reg2reg_solution.pt pt_shell> cs $SCRIPT_FILE; # Ensure there are no errors pt_shell> so $SCRIPT_FILE NOTE: check_script does not understand that FREQ2PERIOD procedure is declared in the.synopsys_pt.setup file and in the PT memory. You can ignore this warning. 5. Perform syntax check and apply the script to constrain all the I/O paths in the design pt_shell> set SCRIPT_FILE./Scripts/io_solution.pt pt_shell> cs $SCRIPT_FILE; # Ensure there are no errors pt_shell> so $SCRIPT_FILE Performing STA 8-5

6 Task 2. Check and Analyze the Design for Timing 1. Check that you have fully constrained your design. pt_shell> check_timing -verbose NOTE: Ensure that check_timing is succeeded. If there are any errors during check_timing, fix them before going to the next step. 2. Generate a constraint report to look at the scope of violations. Restrict the report to only setup violations. pt_shell> report_constraint all_violators max_delay Question 1. How many violations are reported? (NOTE: Count does not need to be exact)... Question 2. What is the largest violation?... Question 3. What RISC_CORE blocks contain violating end points?... Question 4. Which RISC_CORE block contains most of the violating end points?... NOTE: Transfer the needed answers into Table 8-2 NOTE: You can compare your answers to those provided in the Answers for Lab8 section at the end of this lab writeup Cell Swapped Initial Design # of violations Constraint Report Largest violation Blocks with violating endpoints REG_FILE Table 8-2: Constraint report 8-6 Performing STA

7 3. Analyze timing bottlenecks in PrimeTime GUI. Invoke GUI on demand (start_gui) from pt_shell. pt_shell> start_gui GUI Console: Reports -> Histograms -> Timing Bottleneck Bottleneck: Change Number of Bins to 2 (from 8) then OK Histogram: Click on the Right Hand (Worse) bin Question 5. How many cells are there in this bin?... Question 6. Which RISC_CORE block has the largest bottleneck cost?... Question 7. What is the bottleneck cost of the above RISC_CORE block (and the library cell involved)?... Question 8. What are the other RISC_CORE bottleneck blocks? (HINT: Click on the other bin)... NOTE: Transfer the needed answers into Table 8-3 Cell Swapped Bottleneck Report Initial Design Bottleneck blocks (maximum of 3) Worst bottleneck block Bottleneck Cost in the Worst block (Ref Cell) REG_FILE Table 8-3: Bottleneck report Performing STA 8-7

8 4. Exit the histogram and close the GUI. (Do NOT exit the GUI). Histogram: Histogram -> Close PT GUI Console: File -> Close GUI (OR) PT GUI Command prompt pt_shell> stop_gui 5. Generate a timing report pt_shell. Restrict the timing report options to setup check. Show the cell and net delays separately. Display the net fanout, capacitance on the net, transition times along the path up to 3 significant digits. pt_shell> report_timing input_pins nets \? -capacitance transition \? -significant 3 Question 9. What type (input, output, reg2reg) of timing path has been reported?... Question 10. Is timing met? What is the slack?... Question 11. Which RISC_CORE block(s) does the path go through?... Question 12. What is the largest fanout?... Question 13. What is the largest capacitance?... Question 14. What is the largest transition time?... Question 15. What is the largest cell delay?... Question 16. What is the data arrival time? Performing STA

9 NOTE: Transfer the needed answers into Table 8-4 Cell Swapped Timing Report Initial Design REG_FILE Path Type (Input/ Output/ Reg-Reg) Data arrival time (ns) Slack (ns) Largest fanout, capacitance (pf), transition time(ns) and cell delay (ns) Fan Cap Trans Delay Table 8-4: What If Analysis and Timing Report Task 3. Improve Timing (What if Analysis) 1. Read in the improved blocks into PT memory and set RISC_CORE to be the current design. pt_shell> foreach DB {ALU CONTROL DATA_PATH \? INSTRN_LAT PRGRM_CNT_TOP \? REG_FILE STACK_TOP} {? read_db ${DB}_new.db? } pt_shell> current_design RISC_CORE 2. Based on the analysis from previous task, it seems that REG_FILE block needs improvement. Use the new REG_FILE and look at the scope of violations. pt_shell> swap_cell I_REG_FILE REG_FILE_new.db:REG_FILE pt_shell> report_constraint all_violators max_delay Question 17. How many violations are reported?... Question 18. What is the largest violation?... Question 19. What RISC_CORE blocks contain violating end points?... Performing STA 8-9

10 NOTE: Transfer the needed answers into Table Generate bottleneck report. Unlike in the previous task, instead of invoking the GUI, you will perform bottleneck analysis in the pt_shell pt_shell> help *bottle* pt_shell> report_bottleneck Question 20. What are the bottleneck blocks in RISC_CORE?... Question 21. Which RISC_CORE block has the largest bottleneck cost?... Question 22. What is the bottleneck cost of the above RISC_CORE block (and the library cell involved?)... NOTE: Transfer the needed answers into Table Generate the setup timing report. You will need this command again, create an alias. pt_shell> alias rt report_timing input_pins nets \? -capacitance transition \? -significant 3 pt_shell> alias rt pt_shell> rt Question 23. What type (input, output, reg2reg) of timing path has been reported?... Question 24. Is the timing met? What is the slack?... Question 25. Which RISC_CORE block(s) does the path go through?... Question 26. What is the largest fanout?... Question 27. What is the largest capacitance?... Question 28. What is the largest transition time?... Question 29. What is the largest cell delay?... Question 30. What is the data arrival time? Performing STA

11 NOTE: Transfer the needed answers into Table Repeat Steps by identifying the cell to swap. Continue until you have no timing violations on RISC_CORE. Complete the tables 8-2, 8-3 and 8-4 as you proceed. HELPFUL HINT: To avoid retyping the same commands repeatedly, consider using aliases, variables, command recalling. For example: pt_shell> ### EXAMPLE ####### pt_shell> set SWAP ALU pt_shell> swap_cell I_$SWAP ${SWAP}_new.db:$SWAP pt_shell> alias rc report_constraint all_violators \ max_delay pt_shell> alias rb report_bottleneck pt_shell> rc; rb; rt pt_shell> ### EXAMPLE ####### 6. Your design met timing, you cannot, however, save the new netlist with PT. Instead, capture the changes due to the swap_cell commands. pt_shell> write_changes format text out wchanges.txt pt_shell> write_changes format ptsh out wchanges.pt Performing STA 8-11

12 Lab8_solution.pt ############################################### # Lab8_STA of PT:Introduction to STA # Last Modified: Thu May 16 14:07:14 EDT 2002 # ############################################### alias so "source -echo -verbose" so read_solution.pt ; # Read the design and libraries so reg2reg_solution.pt ; # Apply Register to Reg path constraints so io_solution.pt ; # Apply I/O path constraints so report_solution.pt ; # generate reports, Swap cell as needed echo "DONE" 8-12 Performing STA

13 Answers for Lab 8 Task 2. Check and Analyze the Design for Timing Q 1. Q 2. Q 3. Q 4. How many violations are reported? (NOTE: Count does not need to be exact). Too many to count. What is the largest violation? 0.57 ns What RISC_CORE blocks contain violating end points? REG_FILE, ALU, STACK_TOP Which RISC_CORE block contains most of the violating end points? REG_FILE Cell Swapped Constraint Report Initial Design # of violations Too many Largest violation Blocks with violating endpoints REG_FILE, ALU, STACK_TOP REG_FILE ALU, STACK_TOP ALU ALU, STACK_TOP INSTRN_LAT STACK_TOP STACK_TOP Table 8-2: Constraint report Q 5. Q 6. How many cells are there in this bin? 2 Which RISC_CORE block has the largest bottleneck cost? REG_FILE Performing STA 8-13

14 Q 7. Q 8. What is the bottleneck cost of the above RISC_CORE block (and the library cell involved)? 54.0 What are the other RISC_CORE bottleneck blocks? (HINT: Click on the other bin) ALU, INSTRN_LAT, STACK_TOP, DATA_PATH Cell Swapped Bottleneck Report Initial Design REG_FILE ALU INSTRN_LAT Bottleneck blocks REG_FILE, ALU, INSTRN_LAT ALU, INSTRN_LAT, STACK_TOP ALU, INSTRN_LAT STACK_TOP, CONTROL Worst bottleneck Block REG_FILE ALU ALU STACK_TOP STACK_TOP Table 8-3: Bottleneck report Bottleneck Cost in the Worst block (Ref Cell) (or2b2) Q 9. What type (input, output, reg2reg) of timing path has been reported? input Q 10. Is timing met? What is the slack? Violated, ns Q 11. Which RISC_CORE block(s) does the path go through? REG_FILE Q 12. What is the largest fanout? (and6a6) (and6a3) (or2b2) 8-14 Performing STA

15 Q 13. What is the largest capacitance? pf Q 14. What is the largest transition time? ns Q 15. What is the largest cell delay? ns (and2b2) Q 16. What is the data arrival time? ns Cell Swapped Timing Report Path Type (Input/ Output/ Reg-Reg) Data arrival time (ns) Slack (ns) Largest fanout, capacitance (pf), transition time(ns) and cell delay (ns) Fan Cap Trans Delay Initial Design Input REG_FILE Reg-Reg ALU Reg-Reg INSTRN_LAT Input STACK_TOP Reg-Reg Table 8-4: What If Analysis and Timing Report Task 3. Check and Analyze the design for Timing Q 17. How many violations are reported? 6 Q 18. What is the largest violation? 0.30 ns Q 19. What RISC_CORE blocks contain violating end points? ALU, STACK_TOP Performing STA 8-15

16 Q 20. What are the bottleneck blocks in RISC_CORE? ALU, INSTRN_LAT, STACK_TOP Q 21. Which RISC_CORE block has the largest bottleneck cost? ALU Q 22. What is the bottleneck cost of the above RISC_CORE block (and the library cell involved)? (and6a6) Q 23. What type (input, output, reg2reg) of timing path has been reported? reg2reg Q 24. Is the timing met? What is the slack? Violated, ns Q 25. Which RISC_CORE block(s) does the path go through? ALU Q 26. What is the largest fanout? 10 Q 27. What is the largest capacitance? pf Q 28. What is the largest transition time? ns Q 29. What is the largest cell delay? ns (fdesf1a6) Q 30. What is the data arrival time? ns End of Lab 8-16 Performing STA

Introduction to STA using PT

Introduction to STA using PT Learning Objectives Given the design, library and script files, your task will be to successfully perform STA using the PrimeTime GUI and generate reports. After completing