ECC Protection in Software

Transcription

1 Center for RC eliable omputing ECC Protection in Software by Philip P Shirvani RATS June 8, 1999 Outline l Motivation l Requirements l Coding Schemes l Multiple Error Handling l Implementation in ARGOS l Summary 1 Motivation l COTS Board in ARGOS * Transient errors (SEUs) in memory * No hardware ECC * Application corruption l Long repair time l Lost eperiment time * FT in applications l Added compleity due to redundancy l Single-point-of-failure * Operating system corruption Software Implemented ECC l Code Segments * Fied content after link stage * Generate ECC bits on the board * Scrub periodically l Data Segments * Read-only data * Stored results * Random read and writes l Intercept store instructions l Inefficient in software 3 4 Previous Work l Encoding/Decoding for Comm Systems l Software Impl of Error Detection Codes * Performance comparison * Multiple checksum schemes [1] * Computation of CRC via table look-up [] * Quasi-cyclic vs convolution code [3] * Byte-wide SEC-DED (55, 5) RS code [4] l RAM disks of satellite memories Requirements l Data Bits Preserved in Codewords * Systematic code l Small Overhead for ECC Bits l Fast and Small Program * Encoding/decoding and correction l Handling Multiple Error l Background Task l Self-Repair 5 6 Philip P Shirvani - RATS Page 1 6/8/99

2 l Block Code * Communication * Storage l Horizontal Code Different Codes * eg, over a 64-bit word * Memory ECC in hardware l Vertical Code * Bit-sliced l Fleibility in Software l Horizontal Horizontal vs Vertical Code * Wider memory architecture l Vertical * Bit-wise logical instr l Multiple Bit Error * In a word * In a bit-slice 64 data bits 4 ECC bits 8 ECC bits 7 8 Coding Schemes l Detection and Correction Capability * Single errors * Multiple errors * Errors in words, bit-slices l Ease of Software Implementation * Code size and speed l Overhead of Check Bits Scheme 1 - Hamming l (7, 64) Hamming Code Cdd [ 0 1 d63c 1 c7] = Ddd [ 0 1 d63] GI [ P64 8] c = d d d d d d d d d d d d d d d d d d d d d d d d d d d 0 d 1 d l SEC-DED * Independently for each bit-slice d 63 c Scheme - Cyclic 8 7 l (7, 64) Cyclic Code: P( X ) = X + X + X l Polynomial Division * LFSR l Software Implementation * 3 parallel LFSRs l SEC-DED * Independently for each bit-slice + 1 Scheme 3 - Parity l Vertical + Diagonal Parity D0 D1 D D3 C0 C1 l Single Bit Error Correction * One in whole block of 33 bits l Double Bit Detection 11 1 Philip P Shirvani - RATS Page 6/8/99

3 l RS Code, G( 3 ): 31 l d = n-k+1 30 * d=3: SbEC * d=4: SbEC-DbED c0 = di c1 = diα c = diα Scheme 4 - RS 3 P( X ) = X + X + X + X c 1 0 Up to 3-1 words (d=3) or 3 (d=4) check words 13 Comparison Scheme Prog Size Check-bit Performance (bytes) Overhead (Dec MB/s) Hamming % Cyclic % 94 Parity % 3468 RS (d=3) %* 441 * Block = 64 data + check words 14 Multiple Error Handling l Single Particle Hit * Multiple errors [5-7] l ECC Software * Logical view of memory l Programmer s view of bytes and addresses l Mapping of Physical to Logical Bits * Important in code design * System design dependent * Memory structure dependent System Level Dependency l Memory Chip Data Width l Eample: * 3-bit data bus * MB memory l 51K 8bit chips 4 l 51K 1bit chips 3 l Errors in Diff Chips * Independent c Memory Structure Dependency l Physical Layout of Memory Cells * One or multiple arrays * Connection of address bits to the decoders * Mu layouts * Variable among designs Memory Structure 1 l 51K 8bit A0 - A10 Row Decoder 51K 8 Column Decoder A11 - A Philip P Shirvani - RATS Page 3 6/8/99

4 l 4 bit Memory Structure Memory Structure 3 l bit A0 - A16 A0 - A17 A17, A18 1 of 4 Decoder A18 1 of Decoder D0 - D7 D0 - D Interleaving Implementation in ARGOS l Multiple Errors in Adjacent Addresses * eg, 4-way interleaving Memory Block Logical Block ECC Profiler Collector 64 data OS Diagnostic Main Control Telemetry 8 ECC 4*64 data Watchdog 64 data Computations Ground Program 8 ECC 4*8 ECC 1 l Periodic Scrubbing Design Framework Cache Memory l Multitasking * Separate, high priority task for ECC l Memory Access Right to Code Segments * No protection in VWorks l Synchronization * Timer for periodic scrubbing * Message-passing for wake-up calls l Automatic Addition of New Protected Blocks * Initialization code of each module * Block info sent to ECC by message l Cache Coherency in a Split Cache * Instructions in D-cache * Flush D-cache, invalidate I-cache l Software ECC for Cache? * Supervisor mode; OS level * Direct access to data and tag 3 4 Philip P Shirvani - RATS Page 4 6/8/99

5 l Error Detection Error Recovery * SSM, SAI, WD timer l First Retry * Computation errors l Second Retry * Code corrupted * Force ECC scrub l Message-passing l Reload Module l Hardware ECC Summary * Recommended when possible l ECC in Software * Provide protection for code segments * Coding schemes compared l ARGOS Project * Continuous error collection (ECC and others) * Automatic recovery 5 6 Future Work l Self-Checking and Correction for ECC Module * Different schemes * Reliability analysis l More Efficient Schemes l Observe Error Recoveries * Percentage of successful ones * Improvements 7 References (1) l [1] Feldmeier, David C, Fast Software Implementation of Error detection Codes, IEEE/ACM Trans Networking, Vol 3, No 6, pp , De995 l [] Sarwate, Dilip V, Computation of Cyclic Redundancy Checks via Table Look-up, Communications of the ACM, Vol 31, No 8, pp , Aug 1988 l [3] Whelan, James W, Error Correction with a Microprocessor, Proc IEEE National Aerospace and Electronics Conf, pp , 1977 l [4] Hodgart, MS, Efficient Coding and Error Monitoring for Spacecraft Digital Memory, Int l J Electronics, Vol 73, No 1, pp 1-36, 199 l [5] Ziegler, JF, et al IBM eperiments in soft fails in computer electronics, IBM J Res Develop, Vol 40, No 1, pp 3-17, Jan 1996 l [6] Liu, J, et al, Heavy Ion Induced Single Event Effects in Semiconductor Device, Proc Int l Conf on Atomic Collisions in solids, pp, References () l [7] Reed, R, et al, Heavy Ion and Proton-Induced Single Event Multiple Upset, IEEE Trans on Nuclear Science, Vol 44, No 6, pp 4-9, July, 1997 l [8] Rao, TRN, E Fujiwara, Error-Control coding for Computer Systems, Prentice Hall, Philip P Shirvani - RATS Page 5 6/8/99