Design and Implementation of Hybrid Galois Field Secure Digital Communication

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1 Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: Design and Implementation of Hybrid Galois Field Secure Digital Communication Jaya Bharti 1, Prof. Jyotsna Sagar 2 1 Micro Electronics and VLSI, Deptartment Electronics and Communication Engineering, Sri Satya Sai University of Technology & Medical Science, INDIA 2 Assistant Professor, Deptartment Electronics and Communication Engineering, Sri Satya Sai University of Technology & Medical Science, INDIA ABSTRACT The current world of digital communication secure data communication prime task. This paper discusses a new modified method for provide the security of the information in the unsecure communication channel. In this proposed paper implement a GF theory on digital data. In this thesis explore a variety of applications of the theory and applications of arithmetic and computation in the finished fields of cryptography and cryptanalysis as well as in the field of digital communication. For the improvement of security of the codes using the Galious field (G.F.). Computation over finite fields (also called Galois fields) is an active area of research in number theory and algebra, and finds many applications in cryptography, error control coding and combinatorial design. The proposed shows better security as compare to other encoding and decoding method. The proposed method shows good result not only in the security purpose also in the frequency level on FPGA implementation. Keywords Look up tables (LUT), Galious field, cryptography, cryptanalysis and linear error-correcting. I. INTRODUCTION Communication is important in our daily life. We use phones, satellites, computers and other devices to send messages through a channel to a receiver. Unfortunately, most types of communication are subject to noise, which may cause errors in the messages that are being sent. Especially when sending messages is a difficult or expensive task, for example in satellite communication, it is important to find ways to diminish the occurrence of errors as much as possible. As we know it today, cryptology primarily deals with discrete structures and algebraic manipulations inside hardware and software. Finite fields are well-studied discrete structures with a vast array of useful properties and are indispensable in the theory and application of cryptology. Efficient computation in finite fields is crucial for the feasibility of cryptographic systems built on them, and also for the successful cryptanalyses of such systems. Research progress in the arithmetic and computation in finite fields with a view to improving cryptological processes is constantly being made. In this both of case golay and galious field both are important for today s digital communication world because require the security by the hackers for safe and secure communication and money transaction. Finite Field Arithmetic in Prime Fields The prime fields (Fp) having the simplest representation of all finite fields, simply behave as integers modulo (p). The arithmetic in prime fields forms a basis for all algorithms in other finite fields. For example, arithmetic in extension fields (Fpn) can be performed entirely using algorithms built on modulo arithmetic. Public key systems based on various discrete logarithm problems are frequently implemented over finite fields or curves defined over finite fields, to provide structure and efficient arithmetic. In this thesis, we will present new efficient arithmetic for use in extension fields. Algebraic Attacks in Binary Fields The binary prime field F2, which acts in the same way as a Boolean algebra, serves as a great tool for development and analysis of symmetric ciphers, since many of them can be described using Boolean functions. The binary extension fields F2n are used in both public key cryptography in implementing efficient arithmetic and in symmetric key cryptography in designing cipher components. Algebraic attacks on symmetric ciphers rely heavily on the properties of binary fields for the equation generation and solution. In this thesis, we will use algebraic attacks to analyses a collection of stream ciphers not previously analyzed and comment on their susceptibility to these forms of attacks. A. Galious Field In a mathematics, a finite field or Galois field (so-named in honor of Evariste Galois) is a field that contains a finite number of elements. As with any field, a finite field is a set on which the operations of multiplication, addition, subtraction and division are 256 Copyright Vandana Publications. All Rights Reserved.

2 defined and satisfy certain basic rules. The most common examples of finite fields are given by the integer s mod p when p is a prime number. The number of elements of a finite field is called its order. A finite field of order q exists if and only if the order q is a prime power p k (where p is a prime number and k is a positive integer). All fields of a given order are isomorphic. In a field of order p k, adding p copies of any element always results in zero; that is, the characteristic of the field is p. In a finite field of order q, the polynomial X q X has all q elements of the finite field as roots. The non-zero elements of a finite field form a multiplicative group. This group is cyclic, so all nonzero elements can be expressed as powers of a single element called a primitive element of the field (in general there will be several primitive elements for a given field.) A field has, by definition, a commutative multiplication operation. A more general algebraic structure that satisfies all the other axioms of a field, but whose multiplication is not required to be commutative, is called a division ring (or sometimes skewfield). According to Wedderburn's little theorem, any finite division ring must be commutative, and hence a finite field. This result shows that the finiteness restriction can have algebraic consequences. Finite fields are fundamental in a number of areas of mathematics and computer science, including number theory, algebraic geometry, Galois Theory, finite geometry cryptography and coding theory. II. LITERATURE SURVEY A. SEPTEMBER 2015, Efficient Hardware Implementation of Encoder and Decoder for Golay Code, Satyabrata Sarangi and Swapna Banerjee, [01] This brief lays out cyclic redundancy checkbased encoding scheme and presents an efficient implementation of the encoding algorithm in field programmable gate array (FPGA) prototype for both the binary Golay code (G23) and extended binary Golay code (G24). High speed with low-latency architecture has been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shift register. This brief also presents an optimized and lowcomplexity decoding architecture for extended binary Golay code (24, 12, 8) based on an incomplete maximum likelihood decoding scheme. The proposed architecture for decoder occupies less area and has lower latency than some of the recent work published in this area. The encoder module runs at MHz, while the proposed architecture for decoder has an operating clock frequency of MHz. The proposed hardware modules may be a good candidate for forward error correction in communication link, which demands a high-speed system. Efficient hardware architecture for both binary Golay encoder and extended binary Golay encoder have been designed and implemented after verifying the proposed algorithm. The results obtained from simulation state that the proposed hardware architecture for encoder supersedes the conventional LFSR-based CRC generation schemes. Similarly, the proposed hardware module for decoder shows better performance to some of the recent publications considering various performance metrics. These hardware modules for encoder and decoder can be a good candidate for various applications in high speed communication links, photo spectroscopy, and ultrasonography. [01] B. Jul FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems Amirhossein Alimohammad and Saeed Fouladi Fard, [02] This paper presents the bit error rate (BER) performance validation of digital baseband communication systems on a field-programmable gate array (FPGA). The proposed BER tester (BERT) integrates fundamental baseband signal processing modules of a typical wireless communication system along with a realistic fading channel simulator and an accurate Gaussian noise generator onto a single FPGA to provide an accelerated and repeatable test environment in a laboratory setting. Using a developed graphical user interface, the error rate performance of single- and multiple-antenna systems over a wide range of parameters can be rapidly evaluated. The FPGA-based BERT should reduce the need for time-consuming software based simulations, hence increasing the productivity. This FPGA-based solution is significantly more cost effective than conventional performance measurements made using expensive commercially available test equipment and channel simulators. Hardware-accelerated validation is essential to speed up the characterization of computationally intensive and rapidly evolving modern wireless communication systems. This paper presented a parameterizable BERT for a typical single- and multipleantenna digital baseband communication system on a single FPGA. The BERT uses a MIMO realistic fading channel simulator and a high-quality GNG for faithful performance validations in a laboratory setting. By mapping the computationally intensive signal processing algorithms in the simulation chain to dedicated hardware, the simulation time was reduced by over four orders of magnitude. This BERT system is flexible enough to be reconfigured for adapting the new specifications of emerging standards and is scalable to support various configurations. In addition, this measurement system demonstrates how rapid prototyping can be used to minimize reliance on expensive test equipment and time consuming field trials. [02] C. Dec 2012, A low-complexity soft-decision decoding architecture for the binary extended Golay code [03] The (24, 12, 8) extended binary Golay code is a well-known rate-1/2 short block-length linear error correcting code with remarkable properties. This paper investigates the design of an efficient low-complexity softdecision decoding architecture for this code. A dedicated algorithm is introduced that takes advantage of the code s properties to simplify the decoding process. Simulation results show that the proposed algorithm achieves close to maximum-likelihood performance with low computational cost. The decoder architecture is described, and VLSI 257 Copyright Vandana Publications. All Rights Reserved.

3 synthesis results are presented. Soft-decision decoding of Golay codes has been investigated and decoder architecture has been described. The proposed approach relies on a dedicated decoding algorithm which exploits the code properties to achieve near-ml performance using a small number of error patterns. The simulation results and the hardware complexity of the prototype demonstrate the practicality and the benefits of the proposed decoding algorithm. [03] D. May 31, 2012, Galois Field in Cryptography, Christoforus Juan Benvenuto, This paper introduces the basics of Galois Field as well as its implementation in storing data. This paper shows and helps visualizes that storing data in Galois Fields allows manageable and effective data manipulation, where it focuses mainly on application in computer cryptography. Details on the algorithm for Advanced Encryption Standard (AES), which is an examples of computer cryptography that utilizes Galois Field, will also be included. III. PROPOSED METHOD Encoder End - Galois Field (GF2) The Galois field (GF) theory deals with numbers that are binary in nature. Galois operations match those of regular mathematics like addition, multiplication and logarithms using the multiplication property of the Galois field an algorithm can be implemented to design an encoder. Example: if the Multiplicant = 1111 (Hexadecimal = 15 Original data Multiplier = 1111 (Hexadecimal = 15) Irreducible polynomial [private key] = STEP1: (0000) XOR (1) AND (1111) = 1111 [Result] [A (3)] [Multiplicand] STEP2: 11110XOR 1 AND 1111=11110XOR01111 = Result is 5 Bit subtract polynomial to get 4bit result [ =00010] STEP3: (00010) XOR (1) AND (1111) = XOR 01111=01011 STEP4: AND (1111) =10110 XOR 01111=11001(MSB 1 append 0 to result) Result is 5 Bit subtract polynomial [ ] =1010 Final outcome is 1010 in form of hexadecimal [15* 15 = 10]. IV. Fig 1 Shows the proposed method SIMULATION AND RESULT In the simulation output calculate the different output of the proposed method as the register transistor logic (RTL) proposal view, the technological view of the design, the number of slices, the number of Flip Flop slices, the number of 4 LUT inputs: IOB, IOB Flip Flops and GCLK number. All this is calculated in this proposed method and compares it with the base paper. In the simulator isim, the simulation output of the proposed method is shown. In the simulation window, enter the preset in the workbench. Input message, transmitter end key, receiver end key, and encoder data and decoded data. The input signal is shown in the figure below. The above figure shows the result of VHDL default simulator. With the help of this simulator calculate the total number of cycle required used to complete the output. Also shows the letancy of proposed method. Letancy is also known the total delay in completing the process. The simulator window also use to check the output of the proposed method in terms of clock cycle, speed and other parameters. Fig 2 Shows the RTL view of proposed method 258 Copyright Vandana Publications. All Rights Reserved.

4 the table 1 shows the compression of slices and frequency of the proposed method and previous method. Table 1 shows the Comparison of Slices and frequency V. CONCLUSION AND FUTURE WORK Fig 3. Shows the simulation out of proposed method The proposed scheme is a hybrid structure of galious filed. The binary golay code is a type of linear error-correcting code used in digital communications. Special emphasis is laid on its auto morphism group, the group that acts on all code-words and leaves the code unaltered. Here in the proposed work minimized the LUTs and other parameters. In future there are different points to enhance this work. First improve the coding technique using advanced coding technique they will perform good result as compare to coding technique and others coding techniques. REFERENCES Fig 4 Output on Isim Simulator In the last of the simulation and result discuss the compression of outcomes with other previous method. In [1] Satyabrata Sarangi and Swapna Banerjee, Efficient Hardware Implementation of Encoder and Decoder for Golay Code IEEE transactions on very large scale integration (VLSI) systems, vol. 23, no. 9, September [2] Amirhossein Alimohammad and Saeed Fouladi Fard, FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems, IEEE transactions on very large scale integration (VLSI) systems, vol. 22, issue 7, pp , Jul [3] P. Adde and R. Le Bidan, A low-complexity softdecision decoding architecture for the binary extended Golay code, in Proc. 19th IEEE International. Conference Electronics, Circuits, System. (ICECS), Dec. 2012, pp [4] Patrick Adde, Daniel Gomez Toro, and Christophe Jego, Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes, IEEE Transaction Signal Process., vol. 60, no. 7, pp , Jul [5] T.-C. Lin, H. C. Chang, H. P. Lee, and T.-K. Truong On the decoding of the (24, 12, 8) Golay Code, International Science., vol. 180, no. 23, pp Dec Copyright Vandana Publications. All Rights Reserved.

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