An Efficient VLSI Execution of Data Transmission Error Detection and Correction Based Bloom Filter

Transcription

1 GRD Journals Global Research and Development Journal for Engineering International Conference on Innovations in Engineering and Technology (ICIET) July 2016 e-issn: An Efficient VLSI Execution of Data Transmission Error Detection and Correction Based Bloom Filter 1 S. Karthik Raja 2 Dr. A. Kaleel Rahuman 1 PG Scholar 2 Assistant Professor 1,2 Department of Electrical Engineering 1,2 PSNACET, Dindigul, Tamil Nadu, India Abstract Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to inter-symbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. High speed and high throughput hardware for encoder and decoder could be useful in communication field. Due to the channel achieving property, the GOLAY code has become one of the most favorable error-correcting codes. In this paper, a new algorithm has been proposed for CRC based encoding scheme, which devoid of any linear feedback shift registers (LFSR). In this architecture, our work is to design a GOLAY code based encoder and decoder architecture using CRC processing technique. The other approach is to design a Bloom filter with hamming distance based fast error detection and correction methodology and this work is to improve the secure data transmission. The bloom filter system is to identify the error bit location using the redundant bits add process and to correct the error for XOR based distance calculation process. The Bloom filter architecture is used to set the hash value for allocated transmitted data sequence and to improve the fault identification methodology. This method is to optimize the decoder structure and effectively identify the error location, then to correct to error using bit reverser logic process. Keyword- Golay Code, Extended Goaly Code, Bloom Filter I. INTRODUCTION A. Golay Code and Extended Golay Code The Golay codes were first discovered by Golay in The 23-bit Golay code is a very useful code, particularly for those applications when a parity bit is added to each word to yield a half-rate code. Among them, the Golay code was utilized to provide error control on the voyager mission. An algebraic decoding algorithm for the Golay code is given to correct the three possible errors. In 1990, another decoding approach developed is developed, called the shift-search decoding procedure. Forward Error Correction has become an important practical mean for improving the bit error rate (BER) performance of digital communication and storage systems. The (23, 12, 7) binary Golay code is a perfect binary triple-error-correcting code introduced in 1949 [1] with remarkable mathematical properties. The addition of an overall parity-check bit yields the rate- 1/2, self-dual (24,12,8) extended binary Golay code which has found numerous practical applications either as a standalone code (for example on the 1977 Voyager spacecraft mission [2]) or as an inner code in concatenated coding systems [3]. B. Bloom Filter A Bloom filter is a space-efficient probabilistic data structure, conceived by Burton Howard Bloom in 1970, that is used to test whether an element is a member of a set. False positive matches are possible, but false negatives are not, thus a Bloom filter has a 100% recall rate. In other words, a query returns either "possibly in set" or "definitely not in set". Elements can be added to the set, but not removed (though this can be addressed with a "counting" filter). The more elements that are added to the set, the larger the probability of false positives. Bloom proposed the technique for applications where the amount of source data would require an impracticably large hash area in memory if "conventional" error-free hashing techniques were applied. 519

2 Fig. 1: General block diagram of bloom filter He gave the example of a hyphenation algorithm for a dictionary of 500,000 words, out of which 90% follow simple hyphenation rules, but the remaining 10% require expensive disk accesses to retrieve specific hyphenation patterns. With sufficient core memory, an error-free hash could be used to eliminate all unnecessary disk accesses; on the other hand, with limited core memory, Bloom's technique uses a smaller hash area but still eliminates most unnecessary accesses. For example, a hash area only 15% of the size needed by an ideal error-free hash still eliminates 85% of the disk accesses. II. EXISTING WORK FOR THIS ALGORITHM A conventional fully parallel architecture for LDPC decoder was designed. The complex routing network for fully parallel architecture designed to produce the high throughput. Large VNUs and CNUs are required for fully parallel architecture. Connections between the nodes are based on the address logic rather than routing network. The proposed method is to design the partially parallel based architecture for LDPC codes and to reduce the routing congestion in network. This architecture improve the high throughput. The Golay code was presented to address error correcting phenomena. The binary Golay code (G23) is represented as (23, 12, 7), while the extended binary Golay code (G24) is as (24, 12, 8). The extended Golay code has been used extensively in deep space network of JPL-NASA as well as in the Voyager imaging system. In addition, Golay code plays a vital role in different applications like coded excitation for a laser and ultrasound imaging due to the complete side lobe nullification property of complementary Golay pair. All these applications need generation of Golay sequence, which is fed as trigger to the laser modules [4]. However, for generating Golay code an automatic pattern generator is used, which is of very high cost. Extended Golay Code is also known as Golay code (24, 12, 8), where we have code words of length 24 bits describing the original 12-bit message [2]. The minimum Hamming distance between any two code words is 8. The 24 Golay code is an extension of the 23 Golay code. Golay code (24, 12, 8) guarantees retrieving the original data if the error occurred is three bits or less. If errors occurred in four bits there is no guarantee to recover the original data, however, it is possible, due to the fact that the decoding may result in having the original words relate to a group or another with, perhaps, the same probability. More sophisticated choice and exploitation of the structure of both a subspace and the coset representatives are demonstrated for the (24, 12) Golay code, yielding a computational gain factor of about 2 with respect to previous methods. A ternary single-check version of the Wagner rule is applied for efficient soft decoding of the (12, 6) ternary Golay code [10]. An algorithm for maximum-likelihood softdecision decoding of the binary (24, 12, 8) Golay code is presented. The algorithm involves projecting the code words of the binary Golay code onto the code words of the (6, 3, 4) code over GF (4)-the hex code. The complexity of the proposed algorithm is at most 651 real operations. Along similar lines, the tetra code may be employed for decoding the ternary (12, 6, 6) Golay code with only 530 real operations. Invertible sub-matrix for the redundancy part. III. PROPOSED METHOD WITH GOLAY CODE AND EXTENDED GOALY CODE Our work is to design a GOLAY code technique based encoder and decoder using CRC methodology. This work is to increase the secure level and to optimize the circuit complexity. Proposed system is to modify the encoder and decoder data bits structure level and to add the message bit, key bit and to apply the these bits into GOLAY binary code technique[5]. This technique is to apply the majority gate analysis process and to get the final majority output bit and to add the any location in encoder architecture output data bits. To combat this problem, a hardware module programmed to yield a Golay encoded code word may be used. Golay decoder is used extensively in communication links for forward error correction [6]. Therefore, a high speed and high throughput hardware for decoder could be useful in communication links for forward error correction. Literature surveys were conducted, which deal with encoding methods for Golay code, but these are not suitable for hardware implementation due 520

3 to complexity of the algorithms [7]. Weng and Lee invented an encoding method for Golay code comprising of a linear feedback shift register (LFSR), an overall parity bit generator, a clock doubler, a five bit counter, and some switching logic [8]. Conventionally, LFSR-based cyclic redundancy check (CRC) generation scheme is preferred for hardware implementation of encoding process. Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The CRC-32 polynomial, commonly used for most computer network protocol standards, was chosen to implement the algorithm [9]. The LFSR (Linear Feedback Shift Register) circuit is implemented in VLSI (Very-Large-Scale Integration) to perform CRC calculation, which can only process one bit per cycle. Recently, parallelism in the CRC calculation becomes popular, and typically one byte or multiple bytes can be processed in parallel. In summary, this paper proposes a tablebased hardware architecture for calculating CRC that offers a number of benefits. First of all, it calculates the CRC of a message in parallel to achieve better throughput. While the algorithm is based on lookup tables, it adopts multiple small tables instead of a single large table so that the overall required area remains small. A CRC value is calculated as a remainder of the modulo-2 division of the original transmitted data with a specific CRC generator polynomial [10]. IV. PROPOSED METHOD WITH BLOOM FILTER The proposed is to design a Bloom filter with hamming distance based fast error detection and correction methodology and this work is to improve the secure data sequence transmission [11]. The proposed system is to identify the error bit location using the redundant bits add process and to correct the error for xor based distance calculation process. The proposed Bloom filter architecture is used to set the hash value for allocated transmitted data data sequence and to improve the fault identification methodology. The goal for this implementation is to achieve the correction of single bit errors using the CBF. That is, the CBF would enable single bit error correction without incurring in the cost of adding an ECC to the memories. The first step to achieve error correction is to detect errors. This is done by checking the parity bit when accessing either the DRAM or the cache. To ensure earlier detection of errors, the use of scrubbing to periodically read the memories could be considered. Once an error is detected, a correction procedure is triggered. If the error occurs in the CBF, it can be corrected by clearing the CBF and reconstructing it using the element set. If the error occurs in the element set, the procedure is more complex and can be divided in two phases that are described in the following sections [12]. The idea is that the simpler and faster procedure is used first and only when it is unable to correct the error, the second more complex error correction procedure is used subsequently. The proposed scheme is based on the observation that a CBF, in addition to a structure that allows fast membership check to an element set, is also in a way a redundant representation of the element set [13]. Therefore, this redundancy could possibly be used for error detection and correction. To explore this idea, a common implementation of CBFs where the elements of the set are stored in a slow memory and the CBF is stored in a faster memory is considered. The basic idea behind the proposed technique can be applied when the elements of the set are stored in a memory protected with more advanced ECCs [14]. In addition, a simplified version of the proposed approach can also be used for traditional BFs but in that case, the percentage of errors that can be corrected is much lower. The exploration of the scheme extension to these cases is left for future. V. ARCHITECTURE DIAGRAM Fig. 2: Architecture diagram for proposed model 521

4 VI. FLOW DIAGRAM Fig. 3: Flow diagram for proposed model VII. MODULE DESCRIPTION A. Pre-processing work First we apply the input data message directly and to convert the all character values to bit vector format and to passing the bloom filter operation. Fig. 4: flow diagram for Pre Processing This encodes and decoding method is consists of bloom filter function and hamming distance calculation function. Bloom filter operation is to improve the security level and hamming is used to detect and correct the bit wise error presentation. Then to apply the hash value for every DATA sequence and to allocate the sequence format level. Then to set the selected transmitted bit for every 16 bit sequence. B. Bloom Filter Architecture The bloom filter architecture is used to secure data transmission and reception process. The bloom filter is to add hash value in our input sequence. It then sets k bits in a m bit long vector at the addresses corresponding to the hash values. The same 522

5 procedure is repeated for all the members of the set. This process is called programming of the filter. The Bloom filter generates hash values using the same hash functions it used to program the filter. C. Error Detection Fig. 5: flow diagram for bloom filter Fig. 6: Flow diagram for Error Detection The error detection process is to check the bloom hash sequence value and to detect the error in single bit values. This process is to add the redundant bits in different bit position in overall transmission bit sequence. Then to send transmission bit sequence and to get the receiver side and to check the parity value. D. Error Correction To check the parity values to the receiver sequence level and to identify the error accrued bit position. Then to invert the error bit and to correct the overall received bit sequence. This process is mainly used to secured error detection and error correction in received DATA sample sequence. Fig. 7: Flow diagram for error correction 523

6 E. Performance Analysis Fig. 8: flow diagram for performance analysis The DNA sample sequence is to check whether the sequence is correct or wrong format presentation. So we apply the bloom filter function and to matching the selected DNA sequence. Finally we simulate and synthesis result about our proposed error detection and correction architecture. VIII. SIMULATION RESULTS The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates. The area and timing results of the hardware implementation are presented and compared with a conventional loop iteration technique. The analysed frequency for the GOLAY code module is MHz s. This architecture utilizes 24 slices registers out of , 688 slice LUTs out of and 39 bonded IOBs out of 210. The proposed bloom filter method has low number of values when compared to the previous method. Fig. 9: Simulation diagram for proposed model 524

7 Fig. 10: RTL diagram Fig. 11: Device utilization diagram 525

8 GOLAY CODE METHOD BLOOM FILTER METHOD Process Error Correction Error Correction And Detection LUT Count Flip Flops Count LUT Gate Delay Time Table 1: Comparison Table IX. CONCLUSION The proposed scheme is based on the observation that a Bloom filter, in addition to a structure that allows fast membership check to an element set, is also in a way a redundant representation of the element set. Therefore, this redundancy could possibly be used for error detection and correction. The reasoning behind this is that the Bloom filter is accessed frequently and needs a fast access time to maximize performance, while the elements of the set are only accessed when elements are read, added or removed and therefore the access time is not an issue. It should also be noted that when the entire element set is stored in a slow memory, no incorrect deletions can occur as they would be detected when removing the element from the slow memory. If the error occurs in the element set, the procedure is more complex and can be divided in two phases that are described in the following sections. The idea is that the simpler and faster procedure is used first and only when it is unable to correct the error, the second more complex error correction procedure is used subsequently. Finally we design a bloom filter with fast error detection and correction architecture and to improve the error identification process for given selected DATA sequence compare to GOLAY code based encoder and decoder methodology. Comparisons of hardware integrations with other well-known hash functions in literature, shows that the proposed architecture is comparatively better performance and in some cases better synthesis results for both speed and reduced false positive ratio. Thus the proposed bloom filter can be used to improve any application security. REFERENCES [1] M. J. E. Golay, Notes on digital coding, Proc. IRE, vol. 37, p. 657, Jun [2] X.-H. Peng and P. G. Farrell, On construction of the (24, 12, 8)Golay codes, IEEE Trans. Inf. Theory, vol. 52, no. 8, pp ,Aug [3] B. Honary and G. Markarian, New simple encoder and trellis decoderfor Golay codes, Electron. Lett., vol. 29, no. 25, pp ,Dec [4] B. K. Classon, Method, system, apparatus, and phone for error controlof Golay encoded data signals, U.S. Patent , Mar. 6, [5] M.-I. Weng and L.-N. Lee, Weighted erasure codec for the (24, 12) extended Golay code, U.S.Patent , Aug. 2, 1983 [6] S.-Y. Su and P.-C. Li, Photoacoustic signal generation with Golaycoded excitation, in Proc. IEEE Ultrason. Symp. (IUS), Oct. 2010, pp [7] M. Spachmann, Automatic generation of parallel CRC circuits, IEEEDes. Test. Comput., vol. 18, no. 3, pp , May/Jun [8] G. Campobello, G. Patane, and M. Russo, Parallel CRC realization, Trans. Comput., vol. 52, no. 10, pp , Oct [9] R. Nair, G. Ryan, and F. Farzaneh, A symbol based algorithm forhardware implementation of cyclic redundancy check (CRC), inproc.vhdl Int. Users Forum, Oct. 1997, pp [10] P. adde and R. le Bidan, A low-complexity soft-decision decoding architecture for the binay extended Golay code, in proc. 19th IEEE Int. Conf. Electron, Circuits, Syst. (ICECS), Dec. 2012, pp [11] F Chang, J dean, S, Ghemawat, Bigtable: A distributed storage system for structured data, WC Hsieh, [12] Michael Mitzenmacher, Compressed Bloom Filters, [13] Taskin Kocak and Ilhan Kaya, Low-Power Bloom Filter Architecture for Deep Packet Inspection, [14] Michael Paynter and Taskin Kocak, Fully Pipelined Bloom Filter Architecture, 2008 [15] Haoyu Song, Sarang Dharmapurikar, Fast Hash Table Lookup Using Extended Bloom Filter: An Aid to Network Processing,