TIMING-INDEPENDENT TESTING OF CROSSTALK IN THE PRESENCE OF DELAY PRODUCING DEFECTS USING SURROGATE FAULT MODELS *

Transcription

1 TIMING-INDEPENDENT TESTING OF CROSSTALK IN THE PRESENCE OF DELAY PRODUCING DEFECTS USING SURROGATE FAULT MODELS * Shahdad Irajpour Sandeep K. Gupta Melvin A. Breuer Department of EE Systems, University of Southern California, Los Angeles, CA Abstract All previous approaches for generating tests for crosstalk slow-downs are timing-dependent, i.e., they use the nominal values of gate and wire delays while generating tests. None of these methodologies can be used when a crosstalk slow-down must be considered in the presence of process variations and delay producing defects, since such variations and defects change the delay values from the nominal. In this paper, we present the first timing-independent approach to generate tests for crosstalk slow-downs. The framework is based upon defining a set of surrogates for each crosstalk slow-down target and generating a test for each surrogate. The timing-independent conditions that a test for each surrogate must satisfy are presented. Under the pin-to-pin delay model, we prove that a set of twovector sequences that covers every surrogate for a crosstalk slow-down target is guaranteed to detect the target, even in the presence of arbitrary delay variations and delay producing defects. We present a method to identify the crosstalk targets and surrogates for which tests must be generated as well as a test generator that we have implemented. We present extensive experimental results using combinational parts of ISCAS 89 circuits. 1. Introduction Capacitive crosstalk between two lines in a combinational circuit block may slow-down the circuit to such an extent that its worst case delay becomes larger than the desired clock period [1, 2, 3]. For a capacitive coupling between a given pair of lines, namely an affecting and a victim line, a crosstalk slow-down is invoked at the victim line when transitions in opposite directions occur at the two lines [1, 2, 3, 4]. If the delayed transition at the victim line is propagated along one or more propagation paths to circuit outputs, then it may cause delayed transitions at the corresponding outputs [2, 3]. Whether or not a significant crosstalk slow-down is invoked at the victim line depends on the skew between the transitions at the affecting and victim lines [2, 3]. Whether or not the slowed-down transition at the victim line is propagated with large additional delays to the outputs depends on the arrival time of the transition at the victim line as well as the delays of propagation paths from the * This work was supported by the Semiconductor Research Corporation. victim line to the outputs. To take all such timing factors into account, most existing test generators for crosstalk use a timing-dependent approach, i.e., they use gate and interconnect delay values and keep track of arrival and transition times at circuit lines during test generation [2, 3, 5, 6, 7]. Furthermore, most of such test generators use a node-oriented approach as opposed to a path-oriented one [2, 3, 5, 6, 7]. In general, delay values of gates and interconnects change from their nominal values due to variations in the manufacturing process (process variations). Furthermore, multiple delay producing defects (or delay defects for short) may be present at arbitrary locations in the circuit. (Delay defects affect delays of gates or interconnects without affecting their steady-state logic behavior.) Each crosstalk target must be considered in the presence of all such phenomena. Variations in delay values due to process variations can be captured using ranges (instead of single numbers) in the delay models. However, as the process variations become large, it becomes increasingly likely that no single twovector sequence can guarantee the detection of the target slow-down in all manufactured copies of the circuit. This likelihood is even higher when delay defects are also considered, since the multiplicity, locations, and severities of delay defects are unknown. It is not clear how timingdependent node-oriented approaches can be extended to deal with such possibilities. Our objective is to develop a new approach for testing crosstalk slow-down targets in the presence of delay defects and process variations. We will take a timingindependent approach to circumvent the fact that the delay values normally used by a timing-dependent test generation approach are invalidated in the presence of delay defects. In the proposed approach, for any given crosstalk slowdown target, we define a set of surrogates and reduce the problem of finding tests for the given crosstalk target to that of finding tests for the corresponding surrogates. The timing-independent conditions that a test for each surrogate must satisfy are identified. Under the pin-to-pin delay model for gates 1, we show that the tests generated for the 1- Under the pin-to-pin delay model for a gate, for each input line of the gate, and totally independent of the logic values at the other input lines, two delay values are defined, corresponding to the propagation of a rising transition and a falling transition to the output of the gate ITC INTERNATIONAL TEST CONFERENCE /04 $20.00 Copyright 2004 IEEE

2 surrogates corresponding to a given crosstalk slow-down target are collectively guaranteed to test the target in the presence of arbitrary delay defects and process variations. The paper is organized as follows. In Section 2, robust path delay testing framework is reviewed. Inspired by this framework s ability to capture the cumulative effects of isolated as well as distributed delay defects, surrogates and conditions that a test for a surrogate for a crosstalk target must satisfy are defined in Section 3. By use of an example, we show that the framework as defined in Section 3 fails to guarantee the testing of a given crosstalk slow-down target in the presence of arbitrary delay defects. In Section 4, we define another type of test for a surrogate and present the proposed framework for testing crosstalk slow-down targets in the presence of arbitrary delay defects and process variations and prove its correctness. In Section 5, a target list reduction method that identifies crosstalk slow-down targets that are likely to cause timing violations and thus need to be covered by tests is presented. The notion of a covered candidate-target is defined in Section 6. In Section 7, an ATPG capable of generating different types of tests for the surrogates is presented. In Section 8, target list reduction and test generation results are presented. Finally, in Section 9, we present our conclusions and future work. 2. Robust path delay testing framework The path delay fault model is one of the most general delay fault models [8, 9]. It considers isolated as well as distributed delay defects of arbitrary multiplicity, at arbitrary locations and of arbitrary severities, including those caused by statistical process variations [9]. The robust path delay testing framework provides a timingindependent approach for generating tests for such a general delay fault model, under the pin-to-pin delay model for gates [10]. In this framework, a robust test for a target path delay fault is defined as a two-vector sequence that satisfies (a) the complete path transition (CPT) requirement, i.e., causes an appropriate transition at the output of every on-path gate, and (b) the on-path transition sequencing (OTS) requirement, i.e. guarantees that at each on-path gate, the values applied at the off-path inputs are such that the transition at the output of the gate cannot occur unless the transition at the on-path input of the gate has propagated to its output. A robust test for a target path is said to robustly propagate a transition along the path. OTS requirement ensures that delay defects at gates and interconnects that are not on the target path cannot speed-up (but may further slow-down) the transition being propagated along the path. The above two requirements collectively capture the cumulative effect of arbitrary numbers of delay defects along the target path and guarantee (under the pin-to-pin delay model for gates) that a robust test for a target path invokes the maximum delay for the path delay fault. Robust path delay testing framework is based on satisfying CPT and OTS requirements, or equivalently finding robust tests, for every possible path delay fault. Under the pin-to-pin delay model, the generated tests collectively guarantee that the maximum delay is invoked for the entire circuit, even in the presence of an arbitrary number of delay defects. 3. Crosstalk slow-down targets in the presence of delay defects: Surrogates Our objective is to develop a framework for testing crosstalk slow-down targets in the presence of delay defects and variations in the manufacturing process. In a manufactured copy of the circuit, multiple delay defects with arbitrary severities may be present at arbitrary locations. This may result in a large number of distinct manufactured copies of a given circuit. Developing precise delay models for each possible manufactured copy of the circuit is not practical. Hence, we propose a timingindependent framework based on defining a set of surrogates 1 for each crosstalk slow-down target and generating tests for each of the surrogates. In other words, the problem of generating tests for a given crosstalk slowdown target is transformed to that of generating tests for the corresponding surrogates. The conditions that a test for a surrogate must satisfy are defined in a timingindependent manner. Any test set containing a test for each of the surrogates (if such a test exists) corresponding to a given crosstalk slow-down target will guarantee testing of the given target, even in the presence of arbitrary delay defects and variations in the manufacturing process. Consider a crosstalk site as shown in Figure 1 with lines x and y involved in the crosstalk. Considering line y as the victim, we obtain two crosstalk slow-down targets, namely, (x, R, y, F) and (x, F, y, R), where R (F) represents a rising (falling) transition and where (x, R, y, F) denotes a crosstalk target with x as the affecting line and y as the victim line and the two lines have rising and falling transitions, respectively. Similarly, considering line x as victim, we can identify two other crosstalk slow-down targets, namely, (y, R, x, F) and (y, F, x, R). Without loss of generality, we will discuss the crosstalk slow-down target (x, R, y, F) all through this paper. Figure 1. A crosstalk site with x as the affecting line and y as the victim line. 1- The word surrogate has been used by others (e.g. [11, 12]) in a slightly different context. We use this word with the meaning provided by the Oxford Dictionary: A thing that acts for or takes the place of another. x y 1025

3 A two-vector sequence is said to excite a path if it causes transitions at every line along the path, such that the transition at the output of any on-path gate is consistent with the transition at its on-path input. (For a non-inverting gate, a transition at the output is consistent with a transition in the same direction at an input; for an inverting gate, a transition at the output is consistent with a transition in the opposite direction at an input.) A test for the crosstalk slow-down target (x, R, y, F) must excite (i) a sub-path that ends at the affecting line, implying a rising transition at x; (ii) a sub-path that ends at the victim line, implying a falling transition at y; and (iii) a sub-path that starts at y and ends at one of the primary outputs 1. Such a scenario is illustrated in Figure 1. The quality of a test for a given crosstalk slow-down target is determined by crosstalk slowed-down arrival time of the transition at the victim line and the propagation delays of all the sub-paths from the victim line to the primary outputs that are excited. Furthermore, the amount of slow-down invoked at the victim line depends on the skew between the arrival times of the rising and falling transitions at the affecting and victim lines, respectively. A test for the crosstalk slow-down target (x, R, y, F) might excite multiple sub-paths that end at x, multiple subpaths that end at y, and multiple sub-paths that start at y and end at primary outputs. In a manufactured copy of the circuit, the arrival time of the transition at the affecting line, x, depends on delay values of gates and interconnect lines along the sub-paths ending at x that are excited by the applied test. The same is true for the arrival time of the transition at the victim line, y. Delay defects and process variations affect delays of gates and interconnect lines along the sub-paths ending at x and y and thus the arrival times of the transitions at these two lines. Therefore, testing the crosstalk target in the presence of these effects may require multiple tests generated in association with one or more sub-paths that end at x; one or more sub-paths that end at y, and one or more sub-paths that start at y and end at one of the primary outputs. In other words, a surrogate may be defined in terms of one or more sub-paths that end at the affecting line, one or more sub-paths that end at the victim line, and one or more sub-paths that start at the victim line and end at one of the primary outputs. Furthermore, the conditions that a test for a surrogate must satisfy should ensure that delay defects not on the subpaths associated with the surrogate do not accelerate the arrival of the transitions at the appropriate primary outputs. Now focus on the crosstalk slow-down target (x, R, y, F) with n sub-paths, IX 1, IX 2, and IX n, that end at x; m subpaths, IY 1, IY 2, and IY m, that end at y; and p sub-paths, YO 1, YO 2, and YO p, that start at y and end at a primary output. Each unique combination of sub-path IY j (1 j m) and sub-path YO k (1 k p) constitutes one path from an input to an output that passes via the victim line, y, and can 1- Generalization of the definition of excitation for a portion of a path, i.e., a sub-path, is straight-forward. be written as IY j YO k. If one generalizes the robust path delay test conditions in a straight-forward manner, a twovector sequence that (i) satisfies the CPT requirement along sub-path IX i and implies a rising transition at x, and (ii) at the same time satisfies both the CPT and OTS requirements along IY j YO k and implies a falling transition at y, may be considered a test for the given crosstalk slowdown target. Such a vector not only satisfies the necessary conditions depicted in Figure 1, but also captures the cumulative effects of all delay defects along the path IY j YO k and guarantees that the delay defects at off-path lines cannot speed-up the transition along IY j YO k, by satisfying the OTS requirement along this path. The above observations suggest defining surrogate and test for a surrogate in the following manner: A surrogate is a triplet of three sub-paths, a sub-path that ends at the affecting line, a sub-path that ends at the victim line, and a sub-path that starts at the victim line and ends at one of the primary outputs. A total of n.m.p surrogates, written as triplets of sub-paths, (IX i, IY j, YO k ), where 1 i n, 1 j m and 1 k p, are defined in association with the crosstalk slow-down target (x, R, y, F). For a surrogate (IX i, IY j, YO k ), a two-vector sequence is defined to be a robust test (R-test) for a surrogate if it satisfies the CPT requirement on IX i and both the CPT and OTS requirements on IY j YO k. The question is: Is any test set comprised of one R-test for every surrogate guaranteed to invoke the crosstalk slow-down effect with the maximum possible arrival time at primary outputs of any given manufactured copy of the circuit? The above question may be answered using the following example. Figure 2 illustrates the gate level schematic of C17. Consider a crosstalk site with lines 19 and 10 as the affecting and victim lines and (19, R, 10, F) as the crosstalk slow-down target. There are three sub-paths that end at the affecting line (n = 3), two sub-paths that end at the victim line (m = 2) and one sub-path that starts from the victim line and ends at the primary outputs (p = 1), making the total number of surrogates to be 6. The on-sub-path circuit lines together with the corresponding directions of transitions are as follows: IX 1 = 3(R), 9(R), 11(F), 15(F), 19(R) IX 2 = 6(R), 11(F), 15(F), 19(R) IX 3 = 7(F), 19(R) IY 1 = 1(R), 10(F) IY 2 = 3(R), 8(R), 10(F) YO 1 = 10(F), 22(R) According to the above framework, for each surrogate (IX i, IY j, YO k ), where 1 i 3, 1 j 2, and k = 1, an R-test should be sought. Table 1 shows such tests. In this table, T1, T0, S1 and S0 represent rising-transition, falling-transition, static-one and static-zero, respectively. As can be seen V 1 = (T1, S0, T1, T1, S1) is an R-test for surrogates #1, #2, #3, and #4, while V 2 = (T1, S0, T1, S0, T0) is an R-test for surrogates #5 and #

4 Figure 2. Gate level schematic of C17 with the crosstalk slowdown target (19, R, 10, F). Table 1. R-tests for the surrogates. Value at input line R-test for surrogates #1(IX1, IY1, YO1), #2(IX1, IY2, YO1), #3(IX2, IY1, YO1), #4(IX2, IY2, YO1) R-test for surrogates #5(IX3, IY1, YO1), #6(IX3, IY2, YO1) Line 1 T1 T1 Line 2 S0 S0 Line 3 T1 T1 Line 6 T1 S0 Line 7 S1 T0 We would like to verify whether in every manufactured copy of the circuit, application of the vector sequences in the test set TS 1 = {V 1, V 2 }, which contains R-tests for all the surrogates defined for the crosstalk target (19, R, 10, F), invokes a crosstalk slowed-down transition with the maximum possible arrival time at the primary outputs. Now, suppose that in a manufactured copy of the circuit, all the gates and circuit lines have one unit of delay, except line 1, which has four units of delay. If coupling effect does not exist, the two vectors in TS 1, namely, V 1 and V 2, imply a falling transition at the victim line with the same arrival time of 5 units of delay and the corresponding values of skew between arrival times of rising transition at the affecting line and falling transition at the victim line are 1 and -3 for V 1 and V 2, respectively. When coupling exists, based on the value of skew, the falling transition at the victim line is slowed-down and both vectors, by implying an S1 at line 20, propagate the slowed-down transition at the victim line to line 22. Now consider another vector V 3 = (T1, S0, S1, T1, S1). This vector causes a falling transition at the victim line at 5 units of delay and a rising transition at the affecting line with a skew of zero, and propagates the slowed-down transition to an output in an identical manner as either vector in TS 1. Zero skew creates greater slow-down at the victim line and thus V 3 invokes a crosstalk slowed-down transition with a larger arrival time at line 22. This demonstrates that applying TS 1 to the manufactured copy of the circuit does not necessarily invoke the transition with the maximum arrival time at the primary outputs. The above example demonstrates that the definitions proposed above fail to guarantee testing of a given crosstalk slow-down target in the presence of arbitrary delay defects. To remedy this shortcoming, we may consider modifying the definitions in two possible ways: changing the way surrogates are defined, or defining another type of test for a surrogate. As discussed earlier, a surrogate must be defined in terms of one or more sub-paths that end at the affecting line, one or more sub-paths that end at the victim line, and one or more sub-paths that start at the victim line and end at one of the primary outputs. Defining a surrogate as a triplet of sub-paths, or in other words defining a surrogate in terms of only one sub-path that ends at the affecting line, only one sub-path that ends at the victim line, and only one sub-path that starts at the victim line and ends at a primary output, gives the minimum number of surrogates. Any other definition for a surrogate results in considerably larger number of surrogates, for each of which test generation must be carried out. With the hope of avoiding this high complexity, we first investigated the possibility of developing the desired framework by simply seeking another type of test for the surrogates as defined above. 4. Tests for crosstalk slow-down targets in the presence of delay defects In this section, we introduce another type of test for a surrogate and prove that, under the pin-to-pin delay model for gates, when a test set comprised of such tests for all surrogates corresponding to a given crosstalk slow-down target is applied to any manufactured copy of the circuit, (a) all possible arrival times of rising transition at the affecting line and falling transition at the victim line (and thus all the possible skew values between the transitions at the affecting and victim lines) are exercised, and (b) all propagation paths from the victim line to the primary outputs are tried. In other words, we prove that, under the pin-to-pin delay model, applying such a test set to any manufactured copy of the circuit is guaranteed to fully test the crosstalk target. In the example presented in the previous section, neither of the vectors in TS 1 invoked a skew of zero between the rising transition at the affecting line and the falling transition at the victim line. In other words, neither of the vectors implied a rising transition at the affecting line with arrival time equal to 5 units of delay, the cumulative pinto-pin delay values (nominal) along IX 2. There are two surrogates that involve IX 2, surrogate #3 and surrogate #4, for both of which V 1 is an R-test. Although V 1 excites IX 2, it also excites IX 1 and the arrival time of the transition implied at the affecting line turns out to be the cumulative pin-to-pin delay values along IX 1 and not IX 2. On the other hand, by implying static non-controlling values at all the off-sub-path inputs of IX 2, another R-test for surrogate #3, V 3, causes IX 2 to be the only sub-path ending at the affecting line that is excited and makes the transition arrival time at the affecting line be equal to 5, the cumulative pin-to-pin delay values along IX 2. This observation suggests defining another type of test for the surrogates. 1027

5 A restricted-robust test (RR-test) for a surrogate (IX i, IY j, YO k ) is a two-vector sequence that (a) r-robustly propagates a transition along sub-path IX i to cause a rising transition at x, (b) r-robustly propagates a transition along sub-path IY j to cause a falling transition at y, and (c) robustly propagates the falling transition implied at y along sub-path YO k. A two-vector sequence is said to r-robustly (restricted-robustly) propagate a transition along a subpath if it satisfies the CPT requirement along the subpath while implying static non-controlling values at offsub-path inputs of on-sub-path gates. The implied arrival time of the transition at the end of the sub-path will thus be equal to the cumulative pin-to-pin delay values along the sub-path considering the inversion of the gates. If an RR-test exists for a surrogate, the surrogate is called RR-testable; else, it is called RR-untestable. Note that the timing-independent requirements that an RR-test must satisfy are more restricted than those that an R-test must satisfy. In other words, an RR-test is an R-test and thus like an R-test captures the cumulative effects of all delay defects along IY j YO k and guarantees that the delay defects at off-path lines cannot speed-up the transition along this path. Theorem 1: Under the pin-to-pin delay model for gates, a test set that contains at least one RR-test for each surrogate corresponding to a given crosstalk slow-down target is guaranteed to test the given target, even if an arbitrary number of delay defects are present in the circuit under test and even if there exist arbitrary variations in the manufacturing process. The above theorem states that if all the surrogates defined in association with a crosstalk target are RR-testable, applying a set of RR-tests that covers all the surrogates guarantees the coverage of the given target. The proof is based upon the following lemmas, the proof of which can be found in [13]. Lemma 1: Consider a circuit line C not in the transitive fan-out of a crosstalk site. For any arbitrary input vector, under the pin-to-pin delay model for gates, the arrival time of each transition edge in the signal at C is equal to the cumulative pin-to-pin delay values along one of the subpaths that ends at C considering the inversion of the gates along the sub-path. Lemma 2: Under the pin-to-pin delay model for gates, applying any set of RR-tests for the surrogates corresponding to the crosstalk target (x, R, y, F) to a manufactured copy of a circuit implies all the possible values of arrival times of rising transition at the affecting line and falling transition at the victim line (and thus all the possible values of skew between the transitions at the affecting and victim lines), even in the presence of arbitrary (multiple) delay defects or process variations. Proof of Theorem 1: Lemma 2 ensures that applying any set of RR-tests for the surrogates implies all the possible values of arrival times of transitions at the affecting and victim lines (and thus exercises all the possible values of skew), even in the presence of multiple delay defects or process variations. This, when combined with the fact that these tests (collectively) robustly propagate the crosstalk slowed down transition at the victim line along every sub-path from the victim line to a primary output, establishes that when applying such a test set to any manufactured copy of the circuit, the invocation of the transition with the maximum possible arrival time at the outputs is guaranteed. It should also be noted that even though Theorem 1 only states that tests that satisfy these conditions are sufficient for timing-independent testing of a crosstalk target, simple counterexamples can be used to show that these are also the least restrictive conditions that are guaranteed to produce a complete set of timing-independent tests. It should be pointed out that the proposed framework does not apply to crosstalk targets where the affecting line is in the transitive fan-in of the victim line or vice versa. The methodology proposed in this paper is based on the pin-to-pin delay model for gates. This model has been extensively used in path delay testing, gate-level timing analysis, as well as in the few instances where timing is used during crosstalk test generation or fault simulation. The robust path delay tests can be proven to guarantee coverage of all delay faults, only if one assumes the pin-topin delay model [10]. We are aware that the pin-to-pin delay model does not capture all the transistor-level details of delays. To this end, we have developed and used other delay models [14, 15, 16] that capture the cases where near-simultaneous to-controlling (non controlling) transitions at multiple inputs of a gate invoke a gate delay that is often lower (higher) than the pin-to-pin delay from any of the gate's inputs. Despite our work with more accurate delay models, we have based the methodology proposed in this paper on the pin-to-pin delay model for two reasons. First, the complexity of any other model is deemed excessive for test generation for crosstalk. Second, tests generated by implicitly assuming this model (namely robust path delay testing) or explicitly using this model (namely timing-oriented test generation for crosstalk delay fault), are believed by the industry as providing sufficient (or more than sufficient) test quality. A discussion of timing-independent testing of crosstalk under more realistic delay models can be found in [13]. 5. Target list reduction Most VLSI chips contain huge number of circuit-line pairs for each of which four crosstalk slow-down targets can be defined. Since test generation for a crosstalk slowdown target is usually a computationally intensive process, it is desirable to filter out or prune and ignore the crosstalk slow-down targets that are not capable of creating timing violations or those that are very unlikely to cause extensive delays and thus reduce the crosstalk target list. In this 1028

6 process, information such as circuit s logic description, layout, gate level timing models, process variations, as well as electrical parameters provided by extractors are commonly used [17]. In [18] layout information from physical design such as physical adjacency and physical separation are used to obtain the crosstalk target list. In [17] four different filtering procedures are presented. The first procedure uses the coupling capacitance between the affecting and victim lines (provided by an extractor) and the other three use gate level timing models and timing windows to decide whether each crosstalk slow-down targets is likely to create timing violations or not. In this paper, combining a testability attribute of the surrogates (to be defined in the next sub-section) with a simple filtering procedure that uses gate level timing models, we present a sample crosstalk slow-down target list reduction method that excludes the crosstalk slow-down targets that are not capable of creating timing violations or the targets that are very unlikely to cause extensive delays from the crosstalk slow-down target list. Of course, by exploiting a more complicated filtering procedure which uses more information about the circuit and/or information provided by extractors, more crosstalk slow-down targets will be pruned from the target list. The crosstalk slowdown targets that remain in the list are likely to cause timing violations and thus need to be covered via tests. Such targets will be referred to as Excluding FS-untestable targets A functional sensitization test (FS-test) for a surrogate (IX i, IY j, YO k ) can be defined as a two vector sequence that functionally sensitizes the three sub-paths IX i, IY j and YO k. A two vector sequence is said to functionally sensitize a path if it implies non-controlling final values at the off-path inputs of those on-path gates whose on-path input has a non-controlling final value [19] and such a two vector sequence is called a functional sensitization test (FS-test) for the path. Generalization of the definition of functionally sensitizability for a sub-path is straightforward. Analogous to an FS-test, which is the least restricted test defined for a target path in the path delay testing framework, FS-test for a surrogate also satisfies the least restrictive set of requirements for a test for a surrogate. If an FS-test exists for a surrogate, the surrogate is called FS-testable; else it is called FS-untestable. Theorem 2: Under the pin-to-pin delay model for gates, a test set that contains at least one RR-test for each FS-testable surrogate corresponding to a given crosstalk slow-down target is guaranteed to test the given target, even in the presence of arbitrary delay defects and process variations. The proof has been reported in [13]. The above theorem states that we need not consider those surrogates that are not FS-testable and whether or not the proposed framework can be applied to a crosstalk slowdown target only depends on the RR-testability of the FStestable surrogates. This is analogous to path delay testing framework where FS-untestable paths are excluded from the list of target paths because these paths, sometimes called redundant paths, will never cause timing violations [19]. Corollary: A crosstalk slow-down target for which all the surrogates are FS-untestable can not create any timing violation at the primary outputs. If every one of the surrogates of a crosstalk target is FS-untestable, the target is called an FS-untestable target. The above corollary states that FS-untestable targets can be excluded from the crosstalk slow-down target list and need not be covered via tests. A crosstalk target that is not FS-untestable, meaning that at least one of its surrogates is FS-testable, is called an FS-testable target. As mentioned before, for such targets, only the corresponding FS-testable surrogates need to be considered for test development Excluding low-delay targets Under the pin-to-pin delay model, nominal delay of a path is defined as the cumulative pin-to-pin delay values of the gates along the path considering the direction of transitions. The nominal delay of a surrogate denoted by the triplet of sub-paths (IX i, IY j, YO k ) is defined as the nominal delay of IY j YO k, the path that is obtained by concatenating the two sub-paths that include the victim line. FS-testable surrogates can be categorized according to their nominal delay values. Suppose A_max and A_min represent the maximum and the minimum nominal delay values of the FS-testable surrogates in a circuit. The closed range [A_min, A_max] can be divided into N groups, [a 0, a 1 ], (a 1, a 2 ],, (a N-1, a N ]. An FS-testable surrogate is said to belong to group-g if the nominal delay of the surrogate is between a g-1 and a g. Crosstalk slow-down targets can also be categorized according to nominal delay values of their FS-testable surrogates. A crosstalk slow-down target is said to be a group-g target (or said to belong to group-g) if it has at least one FS-testable surrogate in group-g and no FS-testable surrogates in group-(g+1),, group-n. It is highly unlikely that delay defects of likely magnitudes slow-down the propagation of the transition along surrogates in lower groups to the extent that the transition at the primary outputs will occur later than the clock sampling time. Therefore, in a manner analogous to the practice in path delay testing where paths that have nominal delay values much smaller than the maximum delay of the circuit are excluded from the target path list [20], group-1 to group-m crosstalk slow-down targets, where M (1 M < N) can be chosen based on test quality requirements, can also be excluded from the list of crosstalk slow-down targets. Such a crosstalk slow-down target is called a low-delay target Candidate-targets: Crosstalk slow-down targets that need to be covered via tests Using a combination of the FS-testability attribute and the value of the nominal delay of surrogates, explained in 1029

7 the above two sub-sections, crosstalk slow-down targets that are likely to cause timing violations and thus need to be covered via tests are identified. A candidate-target is a crosstalk slow-down target that is (a) FS-testable, and (b) belongs to group-(m+1) or higher. Note that for each candidate-target, we only consider surrogates that are FS-testable and belong to group-(m+1) or higher. 6. Candidate-target coverage For every FS-testable surrogate corresponding to each crosstalk candidate-target, an RR-test must be sought. A candidate-target all of whose FS-testable surrogates are RR-testable is called an RR-testable candidate-target. Such a crosstalk candidate-target is covered by the proposed framework. The notion of a covered candidatetarget can further be extended in the following two ways Practically-RR-testable A candidate-target all of whose FS-testable surrogates in group-(m+1), group-(m+2),, group-n, i.e., all of whose surrogates that we consider, are RR-testable is called a practically-rr-testable candidate-target. A practically- RR-testable candidate-target can also be considered as covered because it is very unlikely that the propagation of a transition along an FS-testable but RR-untestable surrogate in group-1 to group-m is slowed down to the extent that timing requirements are violated at the primary outputs Candidate-targets tested with high confidence One of the approaches for deriving test sets to achieve high defect coverage is based on the generation of n-detection test sets. In [21], it is shown that test sets that detect each stuck-at-fault n > 1 times (called n-detection stuck-at-tests) are more effective in achieving high defect coverages. In [12], generation of n-detection test sets for transition faults is studied. n-detection transition fault test sets are shown to lead to higher delay defect coverages than standard transition fault test sets. In general, the idea of n- detection is to detect a target fault in n different ways in order to achieve higher coverage of the more complicated defects that are not accurately captured in the simplified fault models. The main concern is that different test vectors should excite the fault in different ways leading to different propagation of transitions along different paths. The philosophy behind n-detection idea implies that a candidate-target for which numerous RR-tests exist is highly unlikely to be missed during test, even in the presence of arbitrary delay defects, using the corresponding RR-test set. If the RR-tests mostly correspond to surrogates that have higher nominal delay values, the unlikelihood would be higher. Considering this, with numerous RR-testable surrogates in group-(m +1), group- (M +2),, group-n, where M (1 M < N) can be chosen based on the specifications of the circuit, are called highconfidence-testable and can also be considered as covered because these are highly likely to be tested even in the presence of arbitrary delay defects Test pattern generation An ATPG for generating tests for surrogates has been implemented. Using six basic logic values namely, staticzero (S0), static-one (S1), falling-transition (T0), risingtransition (T1), hazardous-zero (H0) and hazardous-one (H1), twenty composite logic values are identified which provide closure for forward and backward implication procedures. This value system ensures that no information is lost during the implication process. Figure 3 shows details of the procedure used for identifying the composite value set and Table 2 shows the composite logic values and the basic values that they contain. 1. Define six composite logic values each of which contains only one of the basic logic values. 2. Define unknown value as a composite logic value that contains all the basic logic values. 3. Considering the currently identified composite logic values, construct (or reconstruct) tables to be used by forward implication procedure. 4. By applying combinations of the currently identified composite logic values to the backward implication procedure, identify new composite logic values that need to be added. (These composite logic values contain some specific combinations of the basic logic values.) 5. By applying combinations of the currently identified composite logic values to the forward implication procedure, identify other new composite logic values that need to be added. (These composite logic values contain some other specific combinations of the basic logic values.) 6. Repeat steps 3 and 5 until no new values are added. Figure 3. Details of the procedure used for identifying the composite logic values. Table 2: Composite logic values and the basic logic values that they contain. Composite logic value Basic logic values contained in the composite logic value Logic value 0 {S0} Logic value 1 {S1} Logic value 2 {T0} Logic value 3 {T1} Logic value 4 {H0} Logic value 5 {H1} Logic value 6 {S0, S1, T0, T1, H0, H1} Logic value 7 {S0, T0, H0} Logic value 8 {S0, T1, H0} Logic value 9 {S0, H0} Logic value 10 { S0, T0, T1, H0, H1} Logic value 11 {S1, T0, H1} Logic value 12 {T1, H0} Logic value 13 {T0, H1} Logic value 14 {S1, T1, H1} Logic value 15 {T0, H0} Logic value 16 {T1, H1} Logic value 17 {S1, T0, T1, H0, H1} Logic value 18 {T0, T1, H0, H1} Logic value 19 {S1, H1} Logic value 20 {} During initialization, depending on whether an RR-test or an FS-test is being sought for a surrogate, appropriate

8 values are injected at on-sub-path and off-sub-path circuit lines corresponding to the surrogate. The ATPG core implements D-algorithm [22] within which forward and backward implication and justification procedures are executed repeatedly until no unjustified line remains in the circuit. In order to save memory space, at each justification step and when storing the state of the test generator in order to deal with a possible backtrack, only the values at unjustified lines and primary inputs are stored. When backtrack becomes necessary, these values are injected back into circuit lines and necessary implications are performed to completely restore the values at all circuit lines. 8. Experimental Results The above ATPG is used to generate tests for the surrogates corresponding to crosstalk slow-down targets in the combinational parts of ISCAS 89 circuits. For each pair of circuit lines, where one is not in the transitive fan-in of the other, four crosstalk slow-down targets are defined. Table 3 gives some details of the circuits under study. Table 3: Specifications of the circuits under study. Circuit #of inputs #of outputs #of levels #of paths Total #of targets of the form (x, R, y, F) (x and y are not in transitive fan-in of each other) Total #of surrogates associated with the targets S ,006 1,104,012 S ,718 7,757,620 S ,214 9,893,487 S ,876 11,533,803 S ,930 5,742,053 S ,714 8,184,104 S ,157,036 83,915, Target list reduction The, i.e. the crosstalk slow-down targets that need to be covered by tests are identified and the statistics are shown in Table 4. Nominal delay values of the surrogates are calculated using a modified version of the timing simulator used in [23] in which delay of gates is modeled using the pin-to-pin delay model. Values of N and M are chosen to be 8 and 6, respectively. In other words, FS-testable surrogates are categorized into 8 (=N) groups according to their nominal delay values and only FS-testable crosstalk slow-down targets which have FS-testable surrogates in group-7 (7=M+1) or group-8 are identified as Testability of For the FS-testable surrogates corresponding to the identified, RR-tests are sought and RR-testable, practically-rr-testable and high-confidencetestable are identified. The results are Circuit Table 4: Candidate-targets. Total #of targets of the form (x, R, y, F) (x and y are not in transitive fan-in of each other) Total #of FS-untestable targets Total #of low-delay targets #of identified S298 84,006 7,253 68,487 8,266 S ,718 7,404 81,987 20,327 S ,214 18, ,295 17,415 S ,876 13, ,036 36,311 S ,930 35, ,213 23,787 S , , ,997 53,293 S1488 2,157, ,902 1,580, ,613 shown in Table 5. M is chosen to be 6. Recall that with numerous RR-testable surrogates in group-(m +1) to group-n are called high-confidencetestable. We use the following criteria to determine whether a target is deemed to have numerous RR-testable surrogates. A group-8 candidate-target that has less than eight FS-testable surrogates in group-8 is said to be tested with high-confidence if it has at least five RR-testable surrogates in group-7 or group-8. A group-8 candidate-target that has eight or more FS-testable surrogates in group-8 is said to be tested with high-confidence if it has at least four RR-testable surrogates in group-8. A group-7 candidate-target is said to be tested with high-confidence if it has at least six RR-testable surrogates in group-7. Table 5: RR-testable, practically-rr-testable, high-confidencetestable and the overall coverage. Circuit #of identified #of RR-testable #of practically-rr-testable # of high-confidence-testable #of not-covered S298 8, , % S349 20, ,217 12, % S420 17,415 3, , % S444 36,311 2,901 1,066 4,880 27, % S510 23,787 2,663 2, , % S820 53,293 10,440 5,470 2,767 34, % S ,613 31,498 19,184 6, , % Table 5 also shows the number of that are not covered by the proposed framework and the corresponding coverage. The fact that 65%-75% of the can not be tested with high confidence is not as critical as it may seem. Applying any test for a Coverage 1031

9 surrogate, if it exists, to a manufactured copy of the circuit might detect a probable timing violation. In particular, there might be candidate targets that are not identified as RR-testable or practically-rr-testable and are also not identified as high-confidence-testable (because they do not meet the numerous RR-testable high-delay surrogates criteria of the high-confidence-testable category) but have some RR-testable surrogates and applying the corresponding RR-tests to a manufacturing copy of the circuit might detect timing violations, although these are identified as uncovered. Such are not really uncovered; they are simply not confidently covered. For such, less stringent criteria might be defined and used to categorize them as medium-high-confidence-testable, mediumlow-confidence-testable, low-confidence-testable, and so on. A sample of such a categorization is shown in Figure 4 for S820. The only category of that are surely uncovered are those none of whose FS-testable surrogates are RR-testable (we may refer to these as completely RR-untestable). 100% 80% 60% 40% 20% 0% Completely RR-untestable Very-low-confidence-testable Low-confidence-testable Medium-low-confidence-testable Medium-high-confidence-testable High-confidence-testable Practically-RR-testable RR-testable Figure 4. Percentage of different categories of candidatetargets in S Run time Table 6 shows run times in seeking RR-tests and FS-tests for all the surrogates (all the possible pairs of lines were targeted in these results including those that are in transitive fan-in of each other) in different circuits. The number of circuit lines, the number of surrogates, the number of logic levels in the circuit and the topology of the circuit are factors that all affect the total run time for test generation. Two different approaches were used for targeting surrogates for test generation. The second approach or the so called new approach results in much smaller run times. Figure 5 shows the general flows of the two approaches. 9. Conclusions and future work We have developed the first timing-independent pathoriented framework for testing crosstalk slow-down targets in the presence of arbitrary delay defects and process variations. This approach is based upon defining a set of Table 6: Run times of FS/RR-test generation for old and new approaches. Circuit # of inputs # of outputs # of levels # of paths # of surrogates Run time (old approach) FS-test Run time (new approach ) FS-test Run time (old approach) RR-test Run time (new approach ) RR-test S ,647,987 10:06 6:32 6:05 4:04 S ,719, :27 65:46 75:50 28:34 S ,404, :12 80:23 119:16 50:29 S ,317, :37 61:33 83:40 32:14 S ,439, :36 68:27 66:37 36:18 S ,214, :19 201:30 156:42 96:33 S ,374, : : : :23 All times shown as Minutes:Seconds surrogates for each target and generating tests for the corresponding surrogates. We proved that, under the pinto-pin delay model for gates, any test set comprised of at least one RR-test for each surrogate for a given crosstalk slow-down target is guaranteed to test the given target, even in the presence of arbitrary delay defects and process variations. We proved that FS-untestable crosstalk targets cannot cause timing violations. Furthermore, we discussed that filtering procedures can be used for target list reduction. As an example filtering criteria, we used nominal delay of FStestable surrogates to identify targets that are unlikely to create timing violations and thus need to be excluded from the target list. We also discussed that even for the remaining targets, which are called, we can only consider FS-testable surrogates that have relatively large nominal delay values. We also presented metrics to describe high confidence coverage of. The proposed framework might seem impractical to use for large circuits, specifically, for targets with large number of surrogates. We believe that even by applying simple filtering procedures at the target level as well as the surrogate level, many of the targets and even surrogates will be eliminated from consideration. For the that are identified as not confidently covered, we are in the process of identifying additional types of tests so as to generate more comprehensive tests and to report more accurate coverage. We are also investigating how to make the framework more practical by simplifying its requirements in cases where we can assume bounds on extra delays caused by defects and/or process variations and/or cases where we can restrict the types or the number of delay defects. In particular, we are considering cases where we can assume a single delay defect or where we can assume that only significant process variation exists. We are also investigating how timing-dependent node-oriented approaches can be extend to deal with such cases and look forward to comparing their performance with that of the approach presented in this paper. 1032

10 Old Approach: For each target, select the surrogates one by one and perform the following steps. 1. Inject values at on_sub_path and off_sub_path lines for the three sub-paths, ending_at_affecting, ending_at_victim, and starting_at_victim Stop if there is a CONFLICT 2. Perform the necessary implications after value injection Stop if there is a CONFLICT 3. Stop if there remains no unjustified line Repeat the following step until it stops. 4. Using a search tree, inject a value assignment that may justify an unjustified line and perform the necessary implications afterwards Backtrack if there is a CONFLICT Stop if no unjustified line is left Stop if the entire search tree has been traversed New Approach: For each target, select the paths which pass through the victim line one by one and perform the following steps. (Recall: the concatenation of the two sub-paths, ending_at_victim and starting_at_victim, creates a complete path that goes through the victim line.) 1. Inject values at on_sub_path and off_sub_path lines for the path that goes through the victim line Stop if there is a CONFLICT (no need to perform value injection, implication, etc. on any sub-path ending at the affecting line) 2. Perform the necessary implications after the value injections Stop if there is a CONFLICT (no need to perform value injection, implication, etc. on any sub-path ending at the affecting line) 3. Save the status of the circuit (line values and the list of unjustified lines) Select the sub-paths ending at the affecting line one by one and perform the following steps. 4. Restore the status of the circuit (line values and the list of unjustified lines) 5. inject values at on_sub_path and off_sub_path lines of the subpath that ends at the affecting line Stop if there is a CONFLICT 6. Perform the necessary implications after the value injections Stop if there is a CONFLICT 7. Stop if there remains no unjustified line Repeat the following step until it stops. 8. Using a search tree, inject a value assignment that may justify an unjustified line and perform the necessary implications afterwards Backtrack if there is a CONFLICT Stop if no unjustified line is left Stop if the entire search tree has been traversed Figure 5. The general flow of the two approaches used for generating tests for surrogates. References [1] K. T. Lee, C. Nordquist, J. A. Abraham, Test generation for crosstalk effects in VLSI circuits, in Proc. IEEE Int. Symp. Circuits and Systems, pp , [2] W. Y. Chen, S. K. Gupta, M. A. Breuer, Analytic models for crosstalk delay and pulse analysis for non-ideal inputs, in Proc. Int. Test Conf., pp , [3], Analytic models for crosstalk excitation and propagation in VLSI circuits, IEEE Trans. Computer-Aided Design, pp , [4] H. B. Bakoglu, Circuits, interconnections, and packaging for VLSI. Addison-Wesley, [5] W. Y. Chen, S. K. Gupta, M. A. Breuer, Test generation for crosstalk-induced delay in integrated circuits, in Proc. Int. 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