Lecture 7 Fault Simulation

Transcription

1 Lecture 7 Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random Fault Sampling Summary Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7

2 Problem and Motivation Fault simulation Problem: Given A circuit A sequence of test vectors A fault model Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 2

3 Fault simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Remove tested faults Test compactor Delete vectors Fault coverage? Low Adequate Stop Test generator Add vectors Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 3

4 Fault Simulation Scenario Circuit model: mixed-level Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Timing: Two (, ) or three (,, X) states for purely Boolean logic circuits Four states (,, X, Z) for sequential MOS circuits Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 4

5 Fault Simulation Scenario (continued) Faults: Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 5

6 Fault Simulation Algorithms Serial Parallel Deductive Concurrent Differential Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 6

7 Serial Algorithm Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors Advantages: Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 7

8 Serial Algorithm (Cont.) Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together Test vectors Fault-free circuit Comparator f detected? Circuit with fault f Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 8

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10 Parallel Fault Simulation Compiled-code method; best with twostates (,) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w- new faults, where w is the machine word length Speed up over serial method ~ w- Not suitable for circuits with timing-critical and non-boolean logic F9 F8 F7 F6 F5 F4 F3 F2 F F F Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7

11 Parallel Fault Sim. Example Bit : fault-free circuit Bit : circuit with c s-a- Bit 2: circuit with f s-a- a b c s-a- e c s-a- detected g d f s-a- Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7

12 Fault Injection for parallels fault simulati ٦ ٧week Fault-Tolerant Digital System Design ١٢

13 Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 3

14 Deductive Fault Simulation One-pass simulation Each line k contains a list L k of faults detectable on k Following true-value simulation of each vector, fault lists of all gate output lines are updated using settheoretic rules, signal values, and gate input fault lists PO fault lists provide detection data At each of the primary inputs generate the list of faults that can be detected by the test vector Use these lists to generate the lists at other nodes by appropriate operations on these lists Limitations: Set-theoretic rules difficult to derive for non- Boolean gates Gate delays are difficult to use Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 4

15 Fault Lists In deductive Fault lists propagation In deductive fault simulator c a,c b,c a,b,c L ٦ ٧week B Is the set of faults not in L Fault-Tolerant Digital System Design B ١٥

16 Deductive Fault Sim. Example Notation: L k is fault list for line k k n is s-a-n fault on line k a b {a } L e = L a U L c U {e } = {a, b, c, e } {b, c } e {b } c d {b, d } f {b, d, f } g L g = (L e L f ) U {g } = {a, c, e, g } U Faults detected by the input vector Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 6

17 Two valued Deductive Simulation or L ٦ ٧week B Is the set of faults not in L Fault-Tolerant Digital System Design B ١٧

18 ٦ ٧week Fault-Tolerant Digital System Design ١٨

19 ٤Week Fault-Tolerant System Design ١٩

20 Example 5. Example 5. Test Vector ٦ ٧week Fault-Tolerant Digital System Design ٢٠

21 ٦ ٧week Fault-Tolerant Digital System Design ٢١

22 Deductive Fault Simulation (example) La = {a} Lb = {b} Lc = {c} Ld = {d} Le = {e} a i b c d e f g h Lfp = Lb Lc = {c} Lf = {c, f} Lgp = (Ld Le ) = {d} Lg = {d, g} Lhp = (Lf Lg), Lhp = Lh = {h} Lip = La Lh, Lip = {h} Li = {h, i}

23 Deductive Fault Simulation (example contd.) La = {a} Lb = {b} Lc = {c} Ld = {d} Le = {e} a i b c d e f g h Lfp = Lb Lc = { b, c} Lf = {b, c, f} Lgp = (Ld Le ) = {d} Lg = {d, g} Lhp = (Lf Lg) ={ d, g } Lhp = {d,g}, Lh = {d,g,h} Lip = La Lh, Lip = {d, g,h} Li = {d, g, h, i}

24 Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 24

25 Concurrent Fault Simulation Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) Faster than other methods, but uses most memory. Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 25

26 Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 26 Conc. Fault Sim. Example Conc. Fault Sim. Example a b c d e f g a b c e a b b c e d d g f f

27 Fault-Lists (Bad-gates) In concurrent Fault Simulation L g ={a,c,e,g } ٦ ٧week Fault-Tolerant Digital System Design ٢٧

28 Event processing and convergence in concurrent fault simula The processing of the ( ) good-event at a is not complete ٦ ٧week Fault-Tolerant Digital System Design ٢٨

29 Complete fault-lists (bad gates) Bade-gate divergence in concurrent fault simulation ٦ ٧week Fault-Tolerant Digital System Design ٢٩

30 Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 3

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33 ٦ ٧week Fault-Tolerant Digital System Design ٣٣

34 Critical Path Tracing ٦ ٧week Fault-Tolerant Digital System Design ٣٤

35 Example of Critical path tracing in fanout-free ٦ ٧week Fault-Tolerant Digital System Design ٣٥

36 S-a- S-a- S-a- S-a- S-a- ٦ ٧week Fault-Tolerant Digital System Design ٣٦

37 Example of Self masking B S-a- x S-a- ٦ ٧week Fault-Tolerant Digital System Design ٣٧

38 Routh s TEST-DETECT Algorithm = D = D Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 38

39 Fault Sampling A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults. Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 39

40 Motivation for Sampling Complexity of fault simulation depends on: Number of gates Number of faults Number of vectors Complexity of fault simulation with fault sampling depends on: Number of gates Number of vectors Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 4

41 Random Sampling Model Detected fault Undetected fault All faults with a fixed but unknown coverage Random picking N p = total number of faults (population size) C = fault coverage (unknown) C N p = Actual Detectable Faults X = value of c determined from sample fault simulation N s = sample size N s << N p c = sample coverage (a random variable) x N s = # of sample faults detected by given vectors Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 4

42 Number of ways obtaining sample of size N s p p Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 42

43 Probability Density of Sample Coverage, c (x--c ) p (x ) = Prob(x < c < x +dx ) = e 2 /2 p (x ) C ( - C) Variance 2 = N s Mean = C Sampling Error x-c C -3 C x C +3. Sample coverage x Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 43

44 Sampling Error Bounds C ( - C ) x - C = /2 N s Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) coverage estimate: 4.5 C 3 = x [ +.44 N s x ( - x )] /2 N s Where N s is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,96 faults has an actual fault coverage of 87.%. The measured coverage in a random sample of, faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about % of that for all faults. Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 44

45 Summary Fault simulator is an essential tool for test development. Concurrent fault simulation algorithm offers the best choice. For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section ) For large circuits, the accuracy of random fault sampling only depends on the sample size (, to 2, faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. Copyright 2, Agrawal & Bushnell VLSI Test: Lecture 7 45

46 homeworks 5-, 5-7,5-8, 5-2, 5-23, 5-25