S 3 = r 4 r S 2 r S 1 r

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1 nal Engineering Research And Management (IJERM) ISSN : , Volume-, 5, August 24 Design High Speed Excess- M allireddy Sai Deepika, M. N aresh Babu A bstract Processing decimal numbers using binary system tends to be costly in terms area and speed. To realize decimal operations efficiently an i mproved approach to implement decimal additions is proposed which is based on 6- input LUTs and fast carry chains. A new architecture is proposed with emphasis on critical path delay reduction. The adder architecture is implemented on Xilinx Virtex-6 FPGA for operand sizes from 2 to 8 digits. design has outperformed or approaches in terms area and delay. On average, delay reduction is.% and LUT saving is 28.9% compared to a conventional adder. excess- is implemented using this system. I ndex T erms Adders, critical path delay reduction, fast carry chain, 6-input LUT, xilinx virtex- 6 F PGA. I. I NTRODUCTION Decimal computations are required in various applications, such as internet, industrial control, f inancial and commercial systems. Recently re is an increasing demand for efficient hardware realizations required in se applications. This has also led to specification revision IEEE standard for floating- point arithmetic to incorporate decimal format [- 2 ]. A s in any hardware realization real time systems, re is always a requirement to achieve high performance at a low cost. However, decimal arithmetic architectures and hardware realizations, particularly, in Field Programmable Gate Arrays ( FPGAs) have not been fully tackled in literature. Therefore, efficient methods for implementation decimal operations are receiving more attention from h ardware designers. decimal computation, most common operation is. Earlier decimal adders were designed at Manuscript received Aug 8, 24 M. Sai Deepika, P.G.Student scholar M.Tech (VLSI) ECE Department Sree vidyanikethan en gineering college ( Autonomous) M. Naresh Babu, Assistant Pressor in sree V idyanikethan Engineering College, Tirupathi, dia gate level targeting ASICs [- 6]. Binary-Coded- Decimal () number representation was used in se designs. Some schemes utilized in binary adders were also employed in se additions. [], a reduced delay adder was p roposed. This approach improved delay addition by increasing parallelism. Two 4- binary adders, a carry circuit, one AND gate, and one OR gate were used in critical- path adder. [5], a a dder was realized using reversible logic gates. Carry Look- Ahead scheme was employed to speed up performance. The author in [6] proposed a multi- operand parallel decimal adder, which involved binary to decimal conversion in order to obtain r esult. The conversion allows for an easy alignment t he sums adjacent columns. With advancement in FPGA technology, efficiency architecture, and availability various hardware resources, decimal arithmetic can be implemented with high degree efficiency. [7] d ecimal adders/subtractors were proposed based on use Look Up Tables (LUTs) in FPGAs. [8] a multi- operand decimal adder trees were presented and optimized based on 6- input LUTs with fast carry chains. Carry- ripple adders were used in adder t ree, which led to an increase in critical path delay. this paper, an improved carry- ripple adder is presented targeting critical path delay reduction. When implemented into Xilinx Virtex- 6 FPGA, we achieved b oth speed improvement and area reducti on. The organization this paper is as follows. Section 2 introduces some existing decimal adders that were used in this paper for comparison purpose. The improved adder approach is presented in Section. S ection 4, implementations and comparison results are described, and conclusions are given in t he last section. I I. R ELATED ADDITIONS A. Conventional Adder a conventional - digit adder, two operands are added as binary numbers using a binary a dder, and n binary result is converted to number. To perform binary to conversion, correction logic and anor binary adder are required. Fig. is block diagram conventional - digit B CD adder. 89

2 Design High Speed Excess- [ r4rr2r] are used to compare with 4. This will lead to an improved DD conversion architecture, which requires only one adding- correction block, as shown in Fig. 2 (c). The function adding- correction b lock, named as C, is captured in Table. Fig. Conventional -d igit adder. T he c orrection logic function in Fig. is expressed as: C o ut X = S = 4 + S S 2 + S S The sum first binary adder is added to ()2 when sum is greater than 9 to generate correct B CD result. B. Double- D ibble Adder The Double-D abble (DD) adder uses Double- Dabble Binary to Conversion algorithm[9] to convert binary sum to number. This algorithm shifts binary result one left at once, and n compares with 4. If value s hifted s is great than 4, is added to shifted s; orwise, continue to shift one left. Suppose shifted s are called Shifted Unit (SU), a lgorithm is presented as: i f (SU>4) n S U=SU+; e lse shift left; I t is clear that this algorithm is not efficient for conversion large size binary numbers because number corrections is based on number binary s. However, for a - digit adder operation, we have simplified design as shown in Fig. 2, where block C performs function adding- correction. Originally, by using a binary adder, sum two operands is a 5- binary number. To convert this 5- binary result to a number, two adding- correction blocks are required, as shown in Fig. 2 (b) [ 9]. However, since maximum number binary r esult to be corrected is R = [r4r r 2 r r ] = A + B + Cin = 9 = ()2 n maximum value se first three shifted s, [ r4rr2] is not greater than 4. Thus, top adding- correction block in Fig. 2 (b) is not necessary. Then, continue to shift left - into Shifted Unit, which means shifting r into SU. Hence four s, ( a)dd (b)original (c)simplifi ed a dder correction correction Fig 2. DD - d igit adder. N r 4 r r 2 r C ut o S S 2 S N ote add- add- add- add- add- x x x x x x x x T able I. Truth table correction block According to Truth Table, adding- correction are expr essed as: C o ut = r + S = r 4 r S 2 r S r 4 r r + r r 2 + r r 2 r = 4 r + r r 2 + r 2 r = 4 r + r 4 r r + r r 2 r outputs C. 6-LUT-based carry- r ipple adder newer products FPGAs, 6- input LUTs are available to be used and combined with fast carry chain. Fig. shows this structure used to implement - binary adder. By cascading this - binary adder, an n- carry- r ipple binary adder can be realized. Fig. Architecture FPGA for - b it binary adder. 9

3 nal Engineering Research And Management (IJERM) ISSN : , Volume-, 5, August 24 Based on this configuration, a carry- ripple adder has been proposed in [8]. The carry- ripple adder uses 6- input LUTs to add most significant s input operands, and correct result by adding- to sum - addition. this method, correction is performed when sum is equal to or g reater than 4. Then, fast carry chain and XOR gates are used to compute two least significant s and carries. The structure is shown in Fig. 4. Since in this case sum adder, ()2 or ()2, h as been added to ()2, method allowed 4- combinations, ()2 and ()2, to be valid representations decimal values 8 and 9, respectively. To correct final result, a post c orrection has to be performed. T hus, final output adder is expressed as: S = Z 8 + Z2 Z 4 + Z Z 2 + Z this approach, critical path delay is propagated from Cin to Cout, which is equivalent to 4 multiplexer d elays. Fig 4. - d igit adder. (A+B) and carry full adder, named as C. T hus, output adder is expressed as: [ CoutS S 2 S S ] =(A+B+6)ifA+ B 5and C = Φ = A+B+6 if A+ B = 4 and C= = A+B if A+ B = 4 and C= = A+B if A+ B < 4 and C= Φ where adding-6 to (A+B) is same as adding- to ( A+B). According to (5), two scenarios can be considered separately. One is to design - adder with adding- correction without taking into consideration carry full adder; and or one is to add carry full adder for f inal result adder. First, let s consider - adder, (A+B). If sum (A+B) is equal to or greater than 5 while carry full adder is or, final result adder is equal to or greater than ( )2 2=5 2=, and adding- correction is required to be performed to sum ( A+B).Orwise, we do not perform adding- correction to - adder in this case. This - adder and correction are merged toger as a 6-input function, and implemented using a 6- input L UT. Fig. 5 illustrates this architecture, and Table 2 is Truth Table - adder with adding- f unction. I II. P ROPOSED ADDER The proposed adder is also based on 6-i nput LUTs and fast carry chains in FPGAs. Assume input operands adder are A and B in format. To use 6- input LUTs, each two input operands is d ecomposed into two parts: A =[aa 2 a a ] =( aa 2 a ) 2+ a = A 2+ a B =[bb 2 b b ] =( bb 2 b ) 2+ b = B 2+ b The output adder, named as (Co ut S S 2 S S ), i s presented as: [ CoutSS 2 S S ] =A + B + Ci n = [A 2+ a] +[ B 2+ b + Ci = [(a a 2 a ) +( bb 2 b )] 2+[ a+ b c ] n + i n ] (4), expression in first part represents a - adder, and expression in second part is a full adder. Since input operands in (4) are n umbers, maximum value operands, (aa2a) or (bb2b) is ()2. To achieve a output, an adding- correction is performed based on sum Fig 5. - adder with adding- correction using 6- input L UTs. ( a a 2 a ) + ( b b 2 b )... F 4 F F 2 F Note... add- add- add- 9

4 Design High Speed Excess- add- I V. S IMULATION RESULTS Table II. Truth table - adder with adding- c orrections. Now, let s take C into account. If C=, re is no change to result - adder. However, if C=, carry has to be added to sum - adder. This addition is realized by an exclusive OR gate and one multiplexer at each outputs - a dder. Moreover, if C= and sum (A+B) is F4FF2F=()2=4, result adder s hould be equal to: F ig 7: Conventional Adder [ CoutS S 2 S S ] = ( F4F F 2 F + C 2+ F = (+) 2+F = ( F) 2 = ( F) B CD ) I n this case, carry adder, Cout is same as carry full adder C= and sum adder has to be forced to at positions o f S and S. Considering all scenarios mentioned above, f inal carry adder is equal to F4 when ( A+B) 5 (in this case F= after adding- c orrection), and equal to C when (A+B) 4 (in this case F=). Thus, one multiplexer can be used to generate final carry adder. Fig. 6 shows completed design for improved adder. The most left- side multiplexer is used to select eir carry - b it adder F4 for (A+B) 5 and (A+B)<4, or carry full adder C for (A+B)=4. To force sum adder under t he condition (A+B) = (FF2F) = ()2 with C=, one AND gate with - input inverted is c onnected in positions S or S. The improvement our architecture shown in Fig. 6 over one proposed in [8] shown in Fig.4 is that our proposed approach has bypassed two multiplexer d elays in critical path adder, hence reduced carry- propagation delay. This has significant impact on performance large size B CD adders and multipliers. Fig 8: Double-D ibble Adder Fig 9: -d igit Adder Fig : Improved -d igit Adder C omparision Table: Types a dders Conventiona l adder Double-Dibbl e adder - digit a dder Improved - digit a dder Number o f LUTs Fig 6. Improved -d igit adder. D elay(ns).5ns.227ns.8n s 9.79ns 92

5 nal Engineering Research And Management (IJERM) ISSN : , Volume-, 5, August 24 Ex- addition using adders: E xample: using excess- 4-4+= 7 - += 6 7 E xample 2 : using excess- 7-7+= 6 6+= 9 add 6-> 9 Fig : Simulation result using Excess- addition. C omparision Table: Adder T ypes No. L UT's Delay(ns ) Conventiona l adder using ex Double-Dibbl Improved e adder - digit using ex- adder using ex ns 2.95ns.768ns incoming carry to outgoing carry in - digit a dder. The implementation proposed approach has resulted in improvements in terms delay reduction and savings in number LUTs. An excess- addition is implemented using LUT's which resulted in savings in number LUT's and delay r eduction. R EFERENCES [ ] [ ] IEEE Computer Society, IEEE Standard for Floating- P oint Arithmetic, A ug.28. at: j sp?tp=&arnumber=4695. [ 2] M. F. Cowlishaw, Decimal Floating Point: Algorism for Computers, 6th IEEE Symposium on Computer Arithmetic, June 2, page(s): 4-. [ ] A.A. Bayrakci and A. Akkas, Reduced Delay Adder, IEEE ternational Conference on Application- specific Systems, Architectures and Processors (ASAP) 27, page(s): [ 4] O. Al-Khaleel, Z. Al-Qudah, M. Al- Khaleel, C.A. Papachristou and F.G. Wolff, Fast and compact binary-to- conversion circuits for decimal multiplication, 2 IEEE 29th ternational Conference on Computer Design (ICCD), Oct. 2, page(s): [ 5] X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha and R. Sumathi, Realization adder using Reversible Logic, ternational Journal computer ory and engineering, Vol.2, No., June 2, page(s): - 7. [ 6] L. Dadda, Multi Operand Parallel Decimal Adders: a m ixed Binary and Approach, IEEE Transactions on Computers, vol. 56, Oct. 27, p age(s): [ 7] M. Vazquez, G. Sutter, G. Bioul, J.P. Deschamps, Decimal Adders/Subtractors in FPGA: Efficient 6- input LUT Implementations, ternational Conference on Reconfigurable Computing and F PGAs (ReConFig '9), Dec. 29, page(s): [ 8] Alvaro Vazquez and Florent de Dinechin, Multi- operand Decimal Adder Trees for FPGAs, ria , vol., at: [ 9] Binary-to- Converter: Double- Dabble Binary-to- Conversion Algorithm, at: D.pdf. [ ] Xilinx c., Virtex- 6 User Guide, UG64 (v.2), Feb. 22, at: _ guides/ug64.pdf C ONCLUSIONS This paper presented an improved adder based on newer Xilinx FPGA architectures. The proposed a dder approach efficiently mapped decimal addition function onto 6- input LUTs and fast carry chains in FPGAs. The critical path adder has been minimized by bypassing two multiplexers from 9