Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses

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1 Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single clocked process! 2 A Short path Max /T (skew = 0) A Short path Max clock skew? Q Q B B R R C Long path C Long path Clk_ ata output by FF A, B, C f max = t co long su Clk_ ata output by FF A, B, C max( t scew ) = t co short t hold Clk_ Clock-tooutput Long path Setup time Clk_ Clock-to-output + short path ata sampled by FF Q, R holdtime ata sampled by FF Q, R ata must be stable until here 3 4

2 A Max /T at clock skew = 2.0ns? A Max /T at skew = - 2.0ns? Short path Short path Q Q B B R R C Long path C Clk_ ata output by FF A, B, C Clk_ Clock-to-output + long path +setup time Long path ata sampled by FF Q, R f = = t t co co long long su su t scew 2.0 ata outpuy by FF A, B, C Clk_ Clk_ Clock-to-output + long path + setup time ata sampled by FF Q, R f = = t t co co long long su su t scew T T 5 6 esign alternatives ASICs and Programmable Logic Microprocessors igital Signal Processors (SP), micro controllers, etc edicated standard chipsets PCI chipset, GPS chipset, etc Application specific integrated circuits (ASIC) Full custom, cell based, gate arrays Programmable logic Simple Programmable Logic evices (SPL), Complex Programmable Logic evices (CPL), Field Programmable Gate Arrays (FPGA) 7 8

3 Full Custom Standard cells Hierarchical cells Types of ASICs Cell based Types of ASICs Macro cells Generators: memory/pla datapath components etc Semi Custom Mask programmable Gate arrays Array based Field programmable Anti-fuse based Memory based ifferent types of ASICs Full custom ASICs Some or all of the logic cells, circuits or layout is specific for one ASIC. etailed design down to transistor level. For high volume specific applications Mixed analog/digital devices Standard cell based ASICs Libraries of standard cells. esigners connect predefines cells to create desired functionality. (Will be used in VLSI design course) Gate arrays Internal structure is an array of gates with initially unspecified interconnect. esigner specifies gate types and interconnection 9 0 Example standard cell implementation Example gate array implementation f x x f 2 x 2 x 2 x 3 f x 3 Two rows of standard cells 2

4 2 n A PLA is one type of SPL PLA gate level diagram x x 2 x 3 Input buffers and inverters Programmable Logic Array (PLA) AN-OR arrays are common blocks in SPL and CPL architectures P Programmable connections OR plane x x x n x n AN plane P P k OR plane Implements two level logic functions like: f = x + x2 + x2x4 x3x4 x5 P 2 P 3 P 4 f f m AN plane f f PLA simplified gate level diagram x x 2 x 3 P P 2 OR plane What function is implemented? Programmable Array Logic (PAL) Only difference from a PAL is that the OR array is fixed - cheaper to manufacture x x 2 x 3 P P 3 P 4 P 2 P 3 P 4 f f 2 AN plane AN plane f f 2 5 6

5 Simple Programmable Logic evices PAL6V8 Complex Programmable Logic evices CPLs have much higher capacity than SPLs, but the architecture is similar. PAL-like block PAL-like block Macrocell Interconnection wires PAL-like block PAL-like block 7 8 Field Programmable Gate Arrays Logic block Interconnection switches What function is implemented? A section of a programmed FPGA x 3 f x x 2 x x x 2 0 f f 2 0 x 3 0 f f 2 0 f 9 20

6 esign alternatives - when to choose what? Choose the smallest and cheapest device that can implement the required functionality If you can implement a design in a small cheap microcontroller then do not choose an FPGA PLs: PLA, PAL address decoding, high fan-in, small FSMs CPL control logic, FSMs FPGAs control logic and data path logic esign alternatives - when to choose what? CPU, ASIC or FPGA Highly application dependent. What kind of algorithm are you trying to implement? Processors execute in a sequential manner ASICs and FPGAs are not restricted to sequential execution Performance. High data rates? ASIC have highest performance FPGAs can in many applications outperform a processor Flexibility, can the function of the device easily be altered? Processors are most flexible in that sense it is easy to modify and recompile a program FPGAs can be reconfigured Function in an ASIC is fixed 2 22 esign alternatives - when to choose what? CPU, ASIC or FPGA Is power consumption an issue? ASICs have the lowest power consumption. Silicon is tailored for the specific application Time to market Processors, very short FPGAs, short ASICs, very long Volume, cost ASICs have high initial costs. Best choice for high volume designs FPGAs are most expensive, but low initial cost Processors are cheap. Ideal if fast enough CPL or FPGA? This is what Xilinx says (but I agree) CPL Non-volatile Wide fan-in Fast counters, state machines Combinational Logic Small student projects, lower level courses Control Logic FPGA SRAM reconfiguration Excellent for computer architecture, SP, registered designs ASIC like design flow Great for first year to graduate work More common in schools PROM required for non-volatile operation 23 24

Spartan II Architecture SRAM based, needs external configuration memory Two main configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs) CLBs interconnect through a

edicated block memories of 4096 bits each Clock LLs for clock-distribution delay compensation and clock domain control 3-State buffers (BUFTs) associated with each CLB that drive dedicated horizontal

7 Spartan II Architecture SRAM based, needs external configuration memory Two main configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs) CLBs interconnect through a general routing matrix (GRM). The Virtex architecture also includes the following circuits that connect to the GRM. edicated block memories of 4096 bits each Clock LLs for clock-distribution delay compensation and clock domain control 3-State buffers (BUFTs) associated with each CLB that drive dedicated horizontal routing resources Spartan II E family Low cost version of Virtex E device Q: What is a system gate? A: It s all about marketing Spartan II CLB Spartan II slice Xilinx definitions: The additional logic are the F5 and F6 multiplexers. One CLB contains two slices Logic cell (LC) - 4 input LUT, carry logic and a storage element A slice consist of two LCs A CLB consists of 4.5 LC. The /2 LC comes from the fact that some additional logic is available for implementing functions with more than 4 inputs as well as carry logic 27 28

8 Spartan II - LUTs Spartan slice - FPGA Editor view The Spartan LUTs can be configured to implement: 4-input LUTs implements any function of 4 variables 6x-bit synchronous RAM Two LUTs in one slice can be combined to implement 6x2-bit or 32x-bit synchronous RAM 6x-bit dual-port synchronous RAM 6-bit shift register library ieee; use ieee.std_logic_64.all; Example entity Example is port ( A, B, C, : in std_logic; -- Inputs Reset, Clk, En : in std_logic; -- Reset, Clock, Clock enable Y : out std_logic); -- Output end Example; architecture RTL of Example is begin -- RTL process(clk) begin if rising_edge(clk) then if Reset = '' then Y <= '0'; elsif En = '' then Y <= A xor B xor C xor ; end if; end if; end process; end RTL; How will this be implemented? How many slices? 3 32

9 A Clk Reset FC s[0] [0] [0] FC s[] [] [] FC s[2] [2] [2] FC s[3] [3] [3] FC s[4] [4] [4] FC s[5] [5] [5] FC s[6] [6] [6] FC s[7] [7] [7] FC s[8] [8] [8] FC s[9] [9] [9] FC s[0] [0] [0] FC s[] [] [] FC s[2] [2] [2] FC s[3] [3] [3] FC s[4] [4] [4] FC s[5] Y Example 2 8-bit adder with carry input and output How can this be implemented in a Virtex? How many slices? library ieee; use ieee.std_logic_64.all; use ieee.numeric_std.all; entity Example2 is port ( A, B : in unsigned(7 downto 0); Cin : in std_logic; R : out unsigned(7 downto 0); Cout : out std_logic); end Example2; architecture RTL of Example2 is begin -- RTL process(a, B, Cin) variable r_tmp : unsigned(8 downto 0); variable cin_tmp : integer range 0 to ; begin if Cin = '0' then cin_tmp := 0; else cin_tmp := ; end if; r_tmp := ('0' & A) + B + cin_tmp; R <= r_tmp(7 downto 0); Cout <= r_tmp(8); end process; end RTL; Example 2 Four slices - the carry chain is the high lighted (red) net Next slide shows this slice Example 2 Two full adders per slice library ieee; use ieee.std_logic_64.all; Example 3 - shift register 35 entity Example3 is port ( A : in std_logic; Clk, Reset : in std_logic; Y, Y2 : out std_logic); end Example3; architecture RTL of Example3 is signal S, S2 : std_logic_vector(5 downto 0); begin -- RTL Shift : process(clk, Reset) begin if Reset = '' then S <= (others => '0'); elsif rising_edge(clk) then S <= S(4 downto 0) & A; end if; end process; Shift2 : process(clk) begin if rising_edge(clk) then S2 <= S2(4 downto 0) & A; end if; end process; Y <= S(5); Y2 <= S2(5); end RTL A Clk 0 6 FFs 8 slices /2 slice SRL6 A0 A A2 Q A3 CLK s2[4] F C Q s2[5] Y2 36

10 Spartan IIE Block RAM Each Block RAM is a synchronous dual-ported 4096-bit RAM with independent control signals for each port ata widths may be configured independently Spartan tristate buffers Using tristate buffers can save LUTs! Spartan routing resources A view from FPGA editor. Blue boxes are slices (2 slices = CLB). Grey lines are local interconnect. Red lines are long lines. Green lines are pin wires. Three switch boxes per CLB. Spartan IIE clock distribution There are four primary global clock nets that are driven by four global buffers. If these clock nets are used clock skew will not be a problem

11 A elayed Locked Loop (LL) can eliminate on-chip clock distribution delay. This maximizes the achievable I/O speed. LLs Spartan IIE IOB The IOBs are configurable to support several different I/O standards Spartan have four LLs. The LLs can also be used to divide or double the incoming clock frequency internally. The output of the LL can drive the global clock routing recourses and clock skew can be eliminated Virtex II and Virtex II Pro New Xilinx FPGA family faster and larger due to Refined architecture Smaller transistor geometries Virtex II has dedicated 8x8 multipliers... and other stuff as well. Up to system gates and 68 multiplier blocks Virtex II has up to four embedded Power PC processors Computer organization and logic design igital electronics Just in case you are not fed up... igital hardware design with VHL Computer architecture VLSI design Linus Svensson Project in digital synthesis Per Lindgren SMxxx Smaller project course I m not involved in more courses this year 43 44

0 point project course Lp3 lp4 (Per Lindgren plans this course) Soft Processor Core 32-bit - Harvard Bus RISC Architecture Size: 900 Logic Cells Speed: 25 MHz, 82 -MIPS 32 General Purpose Registers;

12 0 point project course Lp3 lp4 (Per Lindgren plans this course) Soft Processor Core 32-bit - Harvard Bus RISC Architecture Size: 900 Logic Cells Speed: 25 MHz, 82 -MIPS 32 General Purpose Registers; 3 Operand Instruction Format IBM CoreConnnect Bus Standard Peripheral set Timer, Counter Arbiter UART, Interrupt controller, SPI GPIO, Watchdog timer External flash, SRAM interface GNU evelopment tools 45

Programmable Logic. Simple Programmable Logic Devices

Programmable Logic. Simple Programmable Logic Devices Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements