9/95. PowerPC 603e. RISC Microprocessor User's Manual with Supplement for PowerPC 603 Microprocessor

Transcription

1 MPR603EUM-01 MPC603EUM/AD 9/95 PowerPC 603e RISC Microprocessor User's Manual with Supplement for PowerPC 603 Microprocessor

2

3 CONTENTS Paragraph Number Title Page Number About This Book Audience... xxvi Organization... xxvii Additional Reading... xxviii Conventions... xxix Acronyms and Abbreviations... xxix Terminology Conventions... xxxiii Chapter 1 Overview 1.1 PowerPC 603e Microprocessor Overview PowerPC 603e Microprocessor Features PowerPC 603 and PowerPC 603e Microprocessors System Design and Programming Considerations Hardware Features Replacement of XATS Signal by CSE1 Signal Addition of Half-Clock Bus Multipliers Software Features Kbyte Instruction and Data Caches Clock Configuration Available in HID1 Register Performance Enhancements Block Diagram Instruction Unit Instruction Queue and Dispatch Unit Branch Processing Unit (BPU) Independent Execution Units Integer Unit (IU) Floating-Point Unit (FPU) Load/Store Unit (LSU) System Register Unit (SRU) Completion Unit Contents iii

4 Paragraph Number CONTENTS Title Page Number Memory Subsystem Support Memory Management Units (MMUs) Cache Units Processor Bus Interface System Support Functions Power Management Time Base/Decrementer IEEE (JTAG)/COP Test Interface Clock Multiplier Levels of the PowerPC Architecture PowerPC 603e Microprocessor: Implementation-Specific Information Features PowerPC Registers and Programming Model General-Purpose Registers (GPRs) Floating-Point Registers (FPRs) Condition Register (CR) Floating-Point Status and Control Register (FPSCR) Machine State Register (MSR) Segment Registers (SRs) Special-Purpose Registers (SPRs) User-Level SPRs Supervisor-Level SPRs Instruction Set and Addressing Modes PowerPC Instruction Set and Addressing Modes PowerPC Instruction Set Calculating Effective Addresses PowerPC 603e Microprocessor Instruction Set Cache Implementation PowerPC Cache Characteristics PowerPC 603e Microprocessor Cache Implementation Exception Model PowerPC Exception Model PowerPC 603e Microprocessor Exception Model Memory Management PowerPC Memory Management PowerPC 603e Microprocessor Memory Management Instruction Timing System Interface Memory Accesses PowerPC 603e Microprocessor Signals Signal Configuration iv PowerPC 603e RISC Microprocessor User's Manual

5 CONTENTS Chapter 2 PowerPC 603e Microprocessor Programming Model 2.1 The PowerPC 603e Processor Register Set PowerPC Register Set PowerPC 603e-Specific Registers Hardware Implementation Registers (HID0 and HID1) Data and Instruction TLB Miss Address Registers (DMISS and IMISS) Data and Instruction TLB Compare Registers (DCMP and ICMP) Primary and Secondary Hash Address Registers (HASH1 and HASH2) Required Physical Address Register (RPA) Instruction Address Breakpoint Register (IABR) Operand Conventions Floating-Point Execution Models UISA Data Organization in Memory and Data Transfers Alignment and Misaligned Accesses Floating-Point Operand Effect of Operand Placement on Performance Instruction Set Summary Classes of Instructions Definition of Boundedly Undefined Defined Instruction Class Illegal Instruction Class Reserved Instruction Class Addressing Modes Memory Addressing Memory Operands Effective Address Calculation Synchronization Context Synchronization Execution Synchronization Instruction-Related Exceptions Instruction Set Overview PowerPC UISA Instructions Integer Instructions Integer Arithmetic Instructions Integer Compare Instructions Integer Logical Instructions Integer Rotate and Shift Instructions Contents v

6 Paragraph Number CONTENTS Title Page Number Floating-Point Instructions Floating-Point Arithmetic Instructions Floating-Point Multiply-Add Instructions Floating-Point Rounding and Conversion Instructions Floating-Point Compare Instructions Floating-Point Status and Control Register Instructions Floating-Point Move Instructions Load and Store Instructions Self-Modifying Code Integer Load and Store Address Generation Register Indirect Integer Load Instructions Integer Store Instructions Integer Load and Store with Byte-Reverse Instructions Integer Load and Store Multiple Instructions Integer Load and Store String Instructions Floating-Point Load and Store Address Generation Floating-Point Load Instructions Floating-Point Store Instructions Branch and Flow Control Instructions Branch Instruction Address Calculation Branch Instructions Condition Register Logical Instructions Trap Instructions Processor Control Instructions Move to/from Condition Register Instructions Memory Synchronization Instructions UISA PowerPC VEA Instructions Processor Control Instructions Memory Synchronization Instructions VEA Memory Control Instructions VEA External Control Instructions PowerPC OEA Instructions System Linkage Instructions Processor Control Instructions OEA Move to/from Machine State Register Instructions Move to/from Special-Purpose Register Instructions Memory Control Instructions OEA Supervisor-Level Cache Management Instruction Segment Register Manipulation Instructions Translation Lookaside Buffer Management Instructions Recommended Simplified Mnemonics PowerPC 603e Implementation-Specific Instructions vi PowerPC 603e RISC Microprocessor User's Manual

7 CONTENTS Chapter 3 Instruction and Data Cache Operation 3.1 Instruction Cache Organization and Control Instruction Cache Organization Instruction Cache Fill Operations Instruction Cache Control Instruction Cache Invalidation Instruction Cache Disabling Instruction Cache Locking Data Cache Organization and Control Data Cache Organization Data Cache Fill Operations Data Cache Control Data Cache Invalidation Data Cache Disabling Data Cache Locking Data Cache Touch Load Support Basic Data Cache Operations Data Cache Fill Data Cache Cast-Out Operation Cache Block Push Operation Data Cache Transactions on Bus Single-Beat Transactions Burst Transactions Access to Direct-Store Segments Memory Management/Cache Access Mode Bits W, I, M, and G Write-Through Attribute (W) Caching-Inhibited Attribute (I) Memory Coherency Attribute (M) Guarded Attribute (G) W, I, and M Bit Combinations Out-of-Order Execution and Guarded Memory Effects of Out-of-Order Data Accesses Effects of Out-of-Order Instruction Fetches Cache Coherency MEI Protocol MEI State Definitions MEI State Diagram MEI Hardware Considerations Coherency Precautions Coherency in Single-Processor Systems Load and Store Coherency Summary Atomic Memory References Contents vii

8 Paragraph Number CONTENTS Title Page Number Cache Reaction to Specific Bus Operations Operations Causing ARTRY Assertion Enveloped High-Priority Cache Block Push Operation Cache Control Instructions Data Cache Block Touch (dcbt) Instruction Data Cache Block Touch for Store (dcbtst) Instruction Data Cache Block Clear to Zero (dcbz) Instruction Data Cache Block Store (dcbst) Instruction Data Cache Block Flush (dcbf) Instruction Enforce In-Order Execution of I/O Instruction (eieio) Instruction Cache Block Invalidate (icbi) Instruction Instruction Synchronize (isync) Instruction Bus Operations Caused by Cache Control Instructions Bus Interface MEI State Transactions Chapter 4 Exceptions 4.1 Exception Classes Exception Priorities Summary of Front-End Exception Handling Exception Processing Enabling and Disabling Exceptions Steps for Exception Processing Setting MSR[RI] Returning from an Exception Handler Process Switching Exception Latencies Exception Definitions Reset Exceptions (0x00100) Hard Reset and Power-On Reset Soft Reset Machine Check Exception (0x00200) Machine Check Exception Enabled (MSR[ME] = 1) Checkstop State (MSR[ME] = 0) DSI Exception (0x00300) ISI Exception (0x00400) External Interrupt (0x00500) viii PowerPC 603e RISC Microprocessor User's Manual

9 CONTENTS Alignment Exception (0x00600) Integer Alignment Exceptions Page Address Translation Access Floating-Point Alignment Exceptions Program Exception (0x00700) IEEE Floating-Point Exception Program Exceptions Illegal, Reserved, and Unimplemented Instructions Program Exceptions Floating-Point Unavailable Exception (0x00800) Decrementer Interrupt (0x00900) System Call Exception (0x00C00) Trace Exception (0x00D00) Single-Step Instruction Trace Mode Branch Trace Mode Instruction TLB Miss Exception (0x01000) Data TLB Miss on Load Exception (0x01100) Data TLB Miss on Store Exception (0x01200) Instruction Address Breakpoint Exception (0x01300) System Management Interrupt (0x01400) Chapter 5 Memory Management 5.1 MMU Features Memory Addressing MMU Organization Address Translation Mechanisms Memory Protection Facilities Page History Information General Flow of MMU Address Translation Real Addressing Mode and Block Address Translation Selection Page Address Translation Selection MMU Exceptions Summary MMU Instructions and Register Summary Real Addressing Mode Block Address Translation Memory Segment Model Page History Recording Referenced Bit Changed Bit Scenarios for Referenced and Changed Bit Recording Page Memory Protection Contents ix

10 Paragraph Number CONTENTS Title Page Number TLB Description TLB Organization TLB Entry Invalidation Page Address Translation Summary Page Table Search Operation Page Table Search Operation Conceptual Flow Table Search Operation with the PowerPC 603e Microprocessor Resources for Table Search Operations Data and Instruction TLB Miss Address Registers (DMISS and IMISS) Data and Instruction TLB Compare Registers (DCMP and ICMP) Primary and Secondary Hash Address Registers (HASH1 and HASH2) Required Physical Address Register (RPA) Software Table Search Operation Flow for Example Exception Handlers Code for Example Exception Handlers Page Table Updates Segment Register Updates Chapter 6 Instruction Timing 6.1 Terminology and Conventions Instruction Timing Overview Timing Considerations General Instruction Flow Instruction Fetch Timing Cache Arbitration Cache Hit Cache Miss Instruction Dispatch and Completion Considerations Rename Register Operation Instruction Serialization Execution Unit Considerations Execution Unit Timings Branch Processing Unit Execution Timing Branch Folding Static Branch Prediction Predicted Branch Timing Examples Integer Unit Execution Timing Floating-Point Unit Execution Timing x PowerPC 603e RISC Microprocessor User's Manual

11 CONTENTS Load/Store Unit Execution Timing System Register Unit Execution Timing Memory Performance Considerations Copy-Back Mode Write-Through Mode Cache-Inhibited Accesses Instruction Scheduling Guidelines Branch, Dispatch, and Completion Unit Resource Requirements Branch Resolution Resource requirements Dispatch Unit Resource Requirements Completion Unit Resource Requirements Instruction Latency Summary Chapter 7 Signal Descriptions 7.1 Signal Configuration Signal Descriptions Address Bus Arbitration Signals Bus Request (BR) Output Bus Grant (BG) Input Address Bus Busy (ABB) Address Bus Busy (ABB) Output Address Bus Busy (ABB) Input Address Transfer Start Signals Transfer Start (TS) Transfer Start (TS) Output Transfer Start (TS) Input Address Transfer Signals Address Bus (A0 A31) Address Bus (A0 A31) Output Address Bus (A0 A31) Input Address Bus Parity (AP0 AP3) Address Bus Parity (AP0 AP3) Output Address Bus Parity (AP0 AP3) Input Address Parity Error (APE) Output Address Transfer Attribute Signals Transfer Type (TT0 TT4) Transfer Type (TT0 TT4) Output Transfer Type (TT0 TT4) Input Transfer Size (TSIZ0 TSIZ2) Output Contents xi

12 Paragraph Number CONTENTS Title Page Number Transfer Burst (TBST) Transfer Burst (TBST) Output Transfer Burst (TBST) Input Transfer Code (TC0 TC1) Output Cache Inhibit (CI) Output Write-Through (WT) Output Global (GBL) Global (GBL) Output Global (GBL) Input Cache Set Entry (CSE0 CSE1) Output Address Transfer Termination Signals Address Acknowledge (AACK) Input Address Retry (ARTRY) Address Retry (ARTRY) Output Address Retry (ARTRY) Input Data Bus Arbitration Signals Data Bus Grant (DBG) Input Data Bus Write Only (DBWO) Input Data Bus Busy (DBB) Data Bus Busy (DBB) Output Data Bus Busy (DBB) Input Data Transfer Signals Data Bus (DH0 DH31, DL0 DL31) Data Bus (DH0 DH31, DL0 DL31) Output Data Bus (DH0 DH31, DL0 DL31) Input Data Bus Parity (DP0 DP7) Data Bus Parity (DP0 DP7) Output Data Bus Parity (DP0 DP7) Input Data Parity Error (DPE) Output Data Bus Disable (DBDIS) Input Data Transfer Termination Signals Transfer Acknowledge (TA) Input Data Retry (DRTRY) Input Transfer Error Acknowledge (TEA) Input System Status Signals Interrupt (INT) Input System Management Interrupt (SMI) Input Machine Check Interrupt (MCP) Input Checkstop Input (CKSTP_IN) Input Checkstop Output (CKSTP_OUT) Output Reset Signals Hard Reset (HRESET) Input Soft Reset (SRESET) Input xii PowerPC 603e RISC Microprocessor User's Manual

13 CONTENTS Processor Status Signals Quiescent Request (QREQ) Quiescent Acknowledge (QACK) Reservation (RSRV) Output Timebase Enable (TBEN) Input TLBI Sync (TLBISYNC) COP/Scan Interface Pipeline Tracking Support Clock Signals System Clock (SYSCLK) Input Test Clock (CLK_OUT) Output PLL Configuration (PLL_CFG0 PLL_CFG3) Input Power and Ground Signals Chapter 8 System Interface Operation 8.1 PowerPC 603e Microprocessor System Interface Overview Operation of the Instruction and Data Caches Operation of the System Interface Optional 32-Bit Data Bus Mode Direct-Store Accesses Memory Access Protocol Arbitration Signals Address Pipelining and Split-Bus Transactions Address Bus Tenure Address Bus Arbitration Address Transfer Address Bus Parity Address Transfer Attribute Signals Transfer Type (TT0 TT4) Signals Transfer Size (TSIZ0 TSIZ2) Signals Burst Ordering During Data Transfers Effect of Alignment in Data Transfers (64-Bit Bus) Effect of Alignment in Data Transfers (32-Bit Bus) Alignment of External Control Instructions Transfer Code (TC0 TC1) Signals Address Transfer Termination Contents xiii

14 Paragraph Number CONTENTS Title Page Number 8.4 Data Bus Tenure Data Bus Arbitration Using the DBB Signal Data Bus Write Only Data Transfer Data Transfer Termination Normal Single-Beat Termination Data Transfer Termination Due to a Bus Error Memory Coherency MEI Protocol Timing Examples Optional Bus Configurations Bit Data Bus Mode No-DRTRY Mode Reduced-Pinout Mode Interrupt, Checkstop, and Reset Signals External Interrupts Checkstops Reset Inputs System Quiesce Control Signals Processor State Signals Support for the lwarx/stwcx. Instruction Pair TLBISYNC Input IEEE Compliant Interface IEEE Interface Description Using Data Bus Write Only Chapter 9 Power Management 9.1 Dynamic Power Management Programmable Power Modes Power Management Modes Full-Power Mode with DPM Disabled Full-Power Mode with DPM Enabled Doze Mode Nap Mode Sleep Mode Power Management Software Considerations xiv PowerPC 603e RISC Microprocessor User's Manual

15 CONTENTS Appendix A PowerPC Instruction Set Listings A.1 Instructions Sorted by Mnemonic...A-1 A.2 Instructions Sorted by Opcode...A-9 A.3 Instructions Grouped by Functional Categories...A-17 A.4 Instructions Sorted by Form...A-27 A.5 Instruction Set Legend...A-38 Appendix B Instructions Not Implemented Appendix C PowerPC 603 Processor System Design and Programming Considerations C.1 PowerPC 603 Microprocessor Hardware Considerations... C-1 C.1.1 Hardware Support for Direct-Store Accesses... C-1 C Extended Address Transfer Start (XATS)... C-2 C Extended Address Transfer Start (XATS) Output... C-2 C Extended Address Transfer Start (XATS) Input... C-2 C.1.2 Direct-Store Protocol Operation... C-2 C Direct-Store Transactions... C-4 C Store Operations... C-5 C Load Operations... C-6 C Direct-Store Transaction Protocol Details... C-7 C Packet 0... C-7 C Packet 1... C-8 C I/O Reply Operations... C-8 C Direct-Store Operation Timing... C-10 C.1.3 CSE Signal... C-12 C.1.4 PowerPC 603 Processor Bus Clock Multiplier Configuration... C-12 C.1.5 PowerPC 603 Processor Cache Organization... C-13 C Instruction Cache Organization... C-14 C Data Cache Organization... C-14 C.2 PowerPC 603 Processor Software Considerations... C-15 C.2.1 Direct-Store Interface Address Translation... C-16 C Direct-Store Segment Translation Summary Flow... C-16 C Direct-Store Interface Accesses... C-17 C Direct-Store Segment Protection... C-18 C Instructions Not Supported in Direct-Store Segments... C-18 C Instructions with No Effect in Direct-Store Segments... C-18 Contents xv

16 Paragraph Number C.2.2 C.2.3 CONTENTS Title Page Number Store Instruction Latency...C-19 Instruction Execution by System Register Unit...C-20 Glossary of Terms and Abbreviations INDEX xvi PowerPC 603e RISC Microprocessor User's Manual

17 ILLUSTRATIONS Figure Number Title Page Number 1-1 PowerPC 603e Microprocessor Block Diagram PowerPC 603e Microprocessor Programming Model Registers Data Cache Organization System Interface PowerPC 603e Microprocessor Signal Groups PowerPC 603e Microprocessor Programming Model Registers Hardware Implementation Register 0 (HID0) Hardware Implementation Register 1 (HID1) DMISS and IMISS Registers DCMP and ICMP Registers HASH1 and HASH2 Registers Required Physical Address Register (RPA) Instruction Address Breakpoint Register (IABR) Instruction Cache Organization Data Cache Organization Double-Word Address Ordering Critical Double Word First MEI Cache Coherency Protocol State Diagram (WIM = 001) Bus Interface Address Buffers Machine Status Save/Restore Register Machine Status Save/Restore Register Machine State Register (MSR) MMU Conceptual Block Diagram 32-Bit Implementations PowerPC 603e Microprocessor IMMU Block Diagram PowerPC 603e Microprocessor DMMU Block Diagram Address Translation Types General Flow of Address Translation (Real Addressing Mode and Block) General Flow of Page and Direct-Store Interface Address Translation Segment Register and TLB Organization Page Address Translation Flow for 32-Bit Implementations TLB Hit Primary Page Table Search Conceptual Flow Secondary Page Table Search Flow Conceptual Flow Derivation of Key Bit for SRR DMISS and IMISS Registers DCMP and ICMP Registers HASH1 and HASH2 Registers Required Physical Address (RPA) Register Flow for Example Software Table Search Operation Illustrations xvii

18 ILLUSTRATIONS Figure Page Title Number Number 5-17 Check and Set R and C Bit Flow Page Fault Setup Flow Setup for Protection Violation Exceptions Pipelined Execution Unit Instruction Flow Diagram Instruction Timing Cache Hit Instruction Timing Cache Miss Branch Instruction Timing PowerPC 603e Microprocessor Signal Groups IEEE Compliant Boundary Scan Interface PowerPC 603e Microprocessor Block Diagram Timing Diagram Legend Overlapping Tenures on the PowerPC 603e Microprocessor Bus for a Single-Beat Transfer Address Bus Arbitration Address Bus Arbitration Showing Bus Parking Address Bus Transfer Snooped Address Cycle with ARTRY Data Bus Arbitration Normal Single-Beat Read Termination Normal Single-Beat Write Termination Normal Burst Transaction Termination with DRTRY Read Burst with TA Wait States and DRTRY MEI Cache Coherency Protocol State Diagram (WIM = 001) Fastest Single-Beat Reads Fastest Single-Beat Writes Single-Beat Reads Showing Data-Delay Controls Single-Beat Writes Showing Data Delay Controls Burst Transfers with Data Delay Controls Use of Transfer Error Acknowledge (TEA) Bit Data Bus Transfer (Eight-Beat Burst) Bit Data Bus Transfer (Two-Beat Burst with DRTRY) Data Bus Write Only Transaction C-1 Direct-Store Tenures...C-4 C-2 Direct-Store Operation Packet 0...C-7 C-3 Direct-Store Operation Packet 1...C-8 C-4 I/O Reply Operation...C-9 C-5 Direct-Store Interface Load Access Example...C-11 C-6 Direct-Store Interface Store Access Example...C-12 C-7 Instruction Cache Organization...C-14 C-8 Data Cache Organization...C-15 C-9 Direct-Store Segment Translation Flow...C-17 xviii PowerPC 603e RISC Microprocessor User s Manual

19 TABLES Table Number Title Page Number i Acronyms and Abbreviated Terms... xxix i Terminology Conventions... xxxiii ii Instruction Field Conventions... xxxiii 1-1 CSE0 CSE1 Signals PowerPC 603e Microprocessor PLL Configuration SRR1 [Key] Bit Generated by PowerPC 603e Microprocessor PowerPC 603e Microprocessor Exception Classifications Exceptions and Conditions MSR[POW] and MSR[TGPR] Bits HID0 Bit Settings HID1 Bit Settings DCMP and ICMP Bit Settings HASH1 and HASH2 Bit Settings RPA Bit Settings Instruction Address Breakpoint Register Bit Settings Memory Operands Integer Arithmetic Instructions Integer Compare Instructions Integer Logical Instructions Integer Rotate Instructions Integer Shift Instructions Floating-Point Arithmetic Instructions Floating-Point Multiply-Add Instructions Floating-Point Rounding and Conversion Instructions Floating-Point Compare Instructions Floating-Point Status and Control Register Instructions Floating-Point Move Instructions Integer Load Instructions Integer Store Instructions Integer Load and Store with Byte-Reverse Instructions Integer Load and Store Multiple Instructions Integer Load and Store String Instructions Floating-Point Load Instructions Floating-Point Store Instructions Branch Instructions Condition Register Logical Instructions Tables xix

20 Table Number TABLES Title Page Number 2-29 Trap Instructions Move to/from Condition Register Instructions Memory Synchronization Instructions UISA Move from Time Base Instruction Memory Synchronization Instructions VEA User-Level Cache Instructions External Control Instructions System Linkage Instructions Move to/from Machine State Register Instructions Move to/from Special-Purpose Register Instructions SPR Encodings for PowerPC 603e-Defined Registers (mfspr) Supervisor-Level Cache Management Instruction Segment Register Manipulation Instructions Translation Lookaside Buffer Management Instructions Combinations of W, I, and M Bits MEI State Definitions CSE0 CSE1 Signal Encoding Memory Coherency Actions on Load Operations Memory Coherency Actions on Store Operations Response to Bus Transactions Bus Operations Caused by Cache Control Instructions (WIM = 001) MEI State Transitions PowerPC 603e Microprocessor Exception Classifications Exceptions and Conditions Exception Priorities SRR1 Bit Settings for Machine Check Exceptions SRR1 Bit Settings for Software Table Search Operations MSR Bit Settings IEEE Floating-Point Exception Mode Bits MSR Setting Due to Exception Settings Caused by Hard Reset Soft Reset Exception Register Settings Machine Check Exception Register Settings DSI Exception Register Settings External Interrupt Register Settings Alignment Interrupt Register Settings Access Types Trace Exception Register Settings Instruction and Data TLB Miss Exceptions Register Settings Instruction Address Breakpoint Exception Register Settings Breakpoint Action for Multiple Modes Enabled for the Same Address System Management Interrupt Register Settings MMU Features Summary xx PowerPC 603e RISC Microprocessor User s Manual

21 TABLES 5-2 Access Protection Options for Pages Translation Exception Conditions Other MMU Exception Conditions for the PowerPC 603e Processor PowerPC 603e Microprocessor Instruction Summary Control MMUs PowerPC 603e Microprocessor MMU Registers Table Search Operations to Update History Bits TLB Hit Case Model for Guaranteed R and C Bit Settings Implementation-Specific Resources for Table Search Operations SRR1 Bits Specific to PowerPC 603e Processor DCMP and ICMP Bit Settings HASH1 and HASH2 Bit Settings RPA Bit Settings Branch Instructions System Register Instructions Condition Register Logical Instructions Integer Instructions Floating-Point Instructions Load and Store Instructions Transfer Encoding for PowerPC 603e Processor Bus Master PowerPC 603e Microprocessor Snoop Hit Response Data Transfer Size Encodings for TC0 TC1 Signals Data Bus Lane Assignments DP0 DP7 Signal Assignments Pipeline Tracking Outputs PLL Configuration Transfer Size Signal Encodings Burst Ordering 64-Bit Bus Burst Ordering 32-Bit Bus Aligned Data Transfers (64-Bit Bus) Misaligned Data Transfers (Four-Byte Examples) Aligned Data Transfers (32-Bit Bus Mode) Misaligned 32-Bit Data Bus Transfer (Four-Byte Examples) Transfer Code Encoding CSE0 CSE1 Signals IEEE Interface Pin Descriptions PowerPC 603e Microprocessor Programmable Power Modes A-1 Complete Instruction List Sorted by Mnemonic... A-1 A-2 Complete Instruction List Sorted by Opcode... A-9 A-3 Integer Arithmetic Instructions... A-17 A-4 Integer Compare Instructions... A-18 A-5 Integer Logical Instructions... A-18 A-6 Integer Rotate Instructions... A-18 Tables xxi

22 Table Number TABLES Title Page Number A-7 Integer Shift Instructions... A-19 A-8 Floating-Point Arithmetic Instructions... A-19 A-9 Floating-Point Multiply-Add Instructions... A-19 A-10 Floating-Point Rounding and Conversion Instructions... A-20 A-11 Floating-Point Compare Instructions... A-20 A-12 Floating-Point Status and Control Register Instructions... A-20 A-13 Integer Load Instructions... A-21 A-14 Integer Store Instructions... A-21 A-15 Integer Load and Store with Byte-Reverse Instructions... A-22 A-16 Integer Load and Store Multiple Instructions... A-22 A-17 Integer Load and Store String Instructions... A-22 A-18 Memory Synchronization Instructions... A-22 A-19 Floating-Point Load Instructions... A-23 A-20 Floating-Point Store Instructions... A-23 A-21 Floating-Point Move Instructions... A-24 A-22 Branch Instructions... A-24 A-23 Condition Register Logical Instructions... A-24 A-24 System Linkage Instructions... A-24 A-25 Trap Instructions... A-25 A-26 Processor Control Instructions... A-25 A-27 Cache Management Instructions... A-25 A-28 Segment Register Manipulation Instructions... A-25 A-29 Lookaside Buffer Management Instructions... A-26 A-30 External Control Instructions... A-26 A-31 I-Form... A-27 A-32 B-Form... A-27 A-33 SC-Form... A-27 A-34 D-Form... A-27 A-35 DS-Form... A-29 A-36 X-Form... A-29 A-37 XL-Form... A-33 A-38 XFX-Form... A-34 A-39 XFL-Form... A-34 A-40 XS-Form... A-34 A-41 XO-Form... A-34 A-42 A-Form... A-35 A-43 M-Form... A-36 A-44 MD-Form... A-36 A-45 MDS-Form... A-37 A-46 PowerPC Instruction Set Legend... A-38 B-1 32-Bit Instructions Not Implemented by the PowerPC 603e Microprocessor...B-1 xxii PowerPC 603e RISC Microprocessor User s Manual

23 TABLES B-2 64-Bit Instructions Not Implemented by the PowerPC 603e Microprocessor...B-1 B-3 64-Bit SPR Encoding Not Implemented by the PowerPC 603e Microprocessor...B-3 C-1 Direct-Store Bus Operations...C-4 C-2 Address Bits for I/O Reply Operations...C-9 C-3 CSE Signal Encoding...C-12 C-4 PowerPC 603 Microprocessor PLL Configuration...C-13 C-5 Store Instruction Timing...C-19 C-6 System Register Instructions...C-20 Tables xxiii

24 xxiv PowerPC 603e RISC Microprocessor User s Manual

25 About This Book The primary objective of this user s manual is to define the functionality of the PowerPC 603 and PowerPC 603e microprocessors for use by software and hardware developers. Although the emphasis of this manual is upon the 603e, all of the information within applies to both the 603 and 603e, except for those differences noted in Appendix C, PowerPC 603 Processor System Design and Programming Considerations. Those readers who are primarily interested in the 603 should begin with Appendix C. The 603e is built upon the low-power dissipation, low-cost and high-performance attributes of the 603 while providing the system designer additional capabilities through higher processor clock speeds (to 100 MHz), increases in cache size (16-Kbyte instruction and data caches) and set-associativity (4-way), and greater system clock flexibility. The 603e only implements the 32-bit portion of the PowerPC Architecture. It is important to note that this book is intended as a companion to the PowerPC Microprocessor Family: The Programming Environments, referred to as The Programming Environments Manual; contact your local sales representative to obtain a copy. Because the PowerPC architecture is designed to be flexible to support a broad range of processors, The Programming Environments Manual provides a general description of features that are common to PowerPC processors and indicates those features that are optional or that may be implemented differently in the design of each processor. The PowerPC 603e RISC Microprocessor User s Manual summarizes features of the 603e that are not defined by the architecture. This document and The Programming Environments Manual distinguish between the three levels, or programming environments, of the PowerPC architecture, which are as follows: PowerPC user instruction set architecture (UISA) The UISA defines the level of the architecture to which user-level software should conform. The UISA defines the base user-level instruction set, user-level registers, data types, memory conventions, and the memory and programming models seen by application programmers. PowerPC virtual environment architecture (VEA) The VEA, which is the smallest component of the PowerPC architecture, defines additional user-level functionality that falls outside typical user-level software requirements. The VEA describes the memory model for an environment in which multiple processors or other devices can access external memory, defines aspects of the cache model and cache control instructions from a user-level perspective. The resources defined by the VEA are About This Book xxv

26 particularly useful for optimizing memory accesses and for managing resources in an environment in which other processors and other devices can access external memory. PowerPC operating environment architecture (OEA) The OEA defines supervisorlevel resources typically required by an operating system. The OEA defines the PowerPC memory management model, supervisor-level registers, and the exception model. Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA. It is important to note that some resources are defined more generally at one level in the architecture and more specifically at another. For example, conditions that cause a floatingpoint exception are defined by the UISA, while the exception mechanism itself is defined by the OEA. Because it is important to distinguish between the levels of the architecture in order to ensure compatibility across multiple platforms, those distinctions are shown clearly throughout this book. For ease in reference, this book has arranged topics described by the architecture into topics that build upon one another, beginning with a description and complete summary of 603especific registers and progressing to more specialized topics such as 603e-specific details regarding the cache, exception, and memory management models. As such, chapters may include information from multiple levels of the architecture. (For example, the discussion of the cache model uses information from both the VEA and the OEA.) The PowerPC Architecture: A Specification for a New Family of RISC Processors defines the architecture from the perspective of the three programming environments and remains the defining document for the PowerPC architecture. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers responsibility to be sure they are using the most recent version of the documentation. For more information, contact your sales representative. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the 603e. It is assumed that the reader understands operating systems, microprocessor system design, the basic principles of RISC processing, and details of the PowerPC architecture. xxvi PowerPC 603e RISC Microprocessor User's Manual

27 Organization Following is a summary and a brief description of the major sections of this manual: Chapter 1, Overview, is useful for readers who want a general understanding of the features and functions of the PowerPC architecture and the 603e. This chapter describes the flexible nature of the PowerPC architecture definition, and provides an overview of how the PowerPC architecture defines the register set, operand conventions, addressing modes, instruction set, cache model, exception model, and memory management model. Chapter 2, PowerPC 603e Microprocessor Programming Model, provides a brief synopsis of the registers implemented in the 603e, operand conventions, an overview of the PowerPC addressing modes, and a list of the instructions implemented by the 603e. Instructions are organized by function. Chapter 3, Instruction and Data Cache Operation, provides a discussion of the cache and memory model as implemented on the 603e. Chapter 4, Exceptions, describes the exception model defined in the PowerPC OEA and the specific exception model implemented on the 603e. Chapter 5, Memory Management, describes the 603e s implementation of the memory management unit specifications provided by the PowerPC OEA for PowerPC processors. Chapter 6, Instruction Timing, provides information about latencies, interlocks, special situations, and various conditions to help make programming more efficient. This chapter is of special interest to software engineers and system designers. Chapter 7, Signal Descriptions, provides descriptions of individual signals of the 603e. Chapter 8, System Interface Operation, describes signal timings for various operations. It also provides information for interfacing to the 603e. Chapter 9, Power Management, provides information about power saving modes for the 603e. Appendix A, PowerPC Instruction Set Listings, lists all the PowerPC instructions while indicating those instructions that are not implemented by the 603e; it also includes the instructions that are specific to the 603e. Instructions are grouped according to mnemonic, opcode, function, and form. Also included is a quick reference table that contains general information, such as the architecture level, privilege level, and form, and indicates if the instruction is 64-bit and optional. Appendix B, Instructions Not Implemented, provides a list of PowerPC instructions not implemented on the 603e. Appendix C, PowerPC 603 Processor System Design and Programming Considerations, provides a discussion of the hardware and software differences between the 603 and 603e. This manual also includes a glossary and an index. About This Book xxvii

28 In this document, the term 603e is used as an abbreviation for the phrase, PowerPC 603e microprocessor, and the term 603 is used as an abbreviation for the phrase, PowerPC 603 microprocessor. The PowerPC 603e microprocessors are available from IBM as PPC603e and from Motorola as MPC603e. Additional Reading Following is a list of additional reading that provides background for the information in this manual: PowerPC Microprocessor Family: The Programming Environments, MPCFPE/AD (Motorola Order Number) and MPRPPCFPE-01 (IBM Order Number) The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, Morgan Kaufmann Publishers, Inc., San Francisco, CA John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., San Mateo, CA PowerPC 601 RISC Microprocessor User s Manual, Rev 1 MPC601UM/AD (Motorola Order Number) and 52G7484/(MPR601UMU-02) (IBM Order Number) PowerPC 601 RISC Microprocessor Technical Summary, Rev 1 MPC601/D (Motorola order number) and MPR601TSU-02 (IBM order number) PowerPC 603 RISC Microprocessor Technical Summary, Rev 3 MPC603/D (Motorola order number) and MPR603TSU-03 (IBM order number) PowerPC 603 RISC Microprocessor Hardware Specifications, Rev 2 MPC603EC/D (Motorola order #) and MPR603HSU-03 (IBM order #) PowerPC 603e RISC Microprocessor Technical Summary, Rev 0 MPC603E/D (Motorola order number) and MPR603TSU-04 (IBM order number) PowerPC 603e RISC Microprocessor Hardware Specifications, Rev 0 MPC603EEC/D (Motorola order #) and MPR603EHS-01 (IBM order #) PowerPC 604 RISC Microprocessor User s Manual, MPC604UM/AD (Motorola order number) and MPR604UMU-01 (IBM order number) PowerPC 604 RISC Microprocessor Technical Summary, Rev 1 MPC604/D (Motorola order number) and MPR604TSU-02 (IBM order number) PowerPC 620 RISC Microprocessor Technical Summary, MPC620/D (Motorola order number) and MPR620TSU-01 (IBM order number) xxviii PowerPC 603e RISC Microprocessor User's Manual

29 Conventions This document uses the following notational conventions: ACTIVE_HIGH Names for signals that are active high are shown in uppercase text without an overbar. ACTIVE_LOW A bar over a signal name indicates that the signal is active low for example, ARTRY (address retry) and TS (transfer start). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as AP0 AP3 (address bus parity signals) and TT0 TT4 (transfer type signals) are referred to as asserted when they are high and negated when they are low. mnemonics Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters, for example, bcctrx 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number ra, rb Instruction syntax used to identify a source GPR ra 0 The contents of a specified GPR or the value 0. rd Instruction syntax used to identify a destination GPR fra, frb, frc Instruction syntax used to identify a source FPR frd Instruction syntax used to identify a destination FPR REG[FIELD] Abbreviations or acronyms for registers are shown in uppercase text. Specific bits, fields, or ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. x In certain contexts, such as a signal encoding, this indicates a don t care. n Used to express an undefined numerical value. Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document. Table i. Acronyms and Abbreviated Terms Term Meaning ALU ATE ASR BAT Arithmetic logic unit Automatic test equipment Address space register Block address translation About This Book xxix

30 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning BIST BIU BPU BUC BUID CAR CIA CMOS COP CR CRTRY CTR DAR DBAT DCMP DEC DMISS DSISR DTLB EA EAR ECC FIFO FPECR FPR FPSCR FPU GPR HASH1 HASH2 IABR IBAT Built-in self test Bus interface unit Branch processing unit Bus unit controller Bus unit ID Cache address register Current instruction address Complementary metal-oxide semiconductor Common on-chip processor Condition register Cache retry queue Count register Data address register Data BAT Data TLB compare Decrementer register Data TLB miss address Register used for determining the source of a DSI exception Data translation lookaside buffer Effective address External access register Error checking and correction First-in-first-out Floating-point exception cause register Floating-point register Floating-point status and control register Floating-point unit General-purpose register Primary hash address Secondary hash address Instruction address breakpoint register Instruction BAT xxx PowerPC 603e RISC Microprocessor User's Manual

31 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning ICMP IEEE IMISS IQ ITLB IU L2 LIFO LR LRU LSB lsb LSU MEI MESI MMU MQ MSB msb MSR NaN No-op OEA PID PIR PLL POWER PR PTE PTEG PVR RAW Instruction TLB compare Institute for Electrical and Electronics Engineers Instruction TLB miss address Instruction queue Instruction translation lookaside buffer Integer unit Secondary cache Last-in-first-out Link register Least recently used Least-significant byte Least-significant bit Load/store unit Modified/exclusive/invalid Modified/exclusive/shared/invalid cache coherency protocol Memory management unit MQ register Most-significant byte Most-significant bit Machine state register Not a number No operation Operating environment architecture Processor identification tag Processor identification register Phase-locked loop Performance Optimized with Enhanced RISC architecture Privilege-level bit Page table entry Page table entry group Processor version register Read-after-write About This Book xxxi

32 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning RISC RPA RTC RTCL RTCU RTL RWITM SDR1 SLB SPR SR Reduced instruction set computing Required physical address Real-time clock Real-time clock lower register Real-time clock upper register Register transfer language Read with intent to modify Register that specifies the page table base address for virtual-to-physical address translation Segment lookaside buffer Special-purpose register Segment register SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 SRU TAP TB TBL TBU TLB TTL UIMM UISA UTLB UUT VEA WAR WAW WIMG XATC XER System register unit Test access port Time base facility Time base lower register Time base upper register Translation lookaside buffer Transistor-to-transistor logic Unsigned immediate value User instruction set architecture Unified translation lookaside buffer Unit under test Virtual environment architecture Write-after-read Write-after-write Write-through/caching-inhibited/memory-coherency enforced/guarded bits Extended address transfer code Register used for indicating conditions such as carries and overflows for integer operations xxxii PowerPC 603e RISC Microprocessor User's Manual

33 Terminology Conventions Table ii describes terminology conventions used in this manual. Table ii. Terminology Conventions The Architecture Specification This Manual Data storage interrupt (DSI) Extended mnemonics Fixed-point unit (FXU) Instruction storage interrupt (ISI) Interrupt Privileged mode (or privileged state) Problem mode (or problem state) Real address Relocation Storage (locations) Storage (the act of) Store in Store through DSI exception Simplified mnemonics Integer unit (IU) ISI exception Exception Supervisor-level privilege User-level privilege Physical address Translation Memory Access Write back Write through Table iii describes instruction field notation used in this manual. Table iii. Instruction Field Conventions The Architecture Specification BA, BB, BT BF, BFA D DS FLM FRA, FRB, FRC, FRT, FRS FXM RA, RB, RT, RS SI U UI Equivalent to: crba, crbb, crbd (respectively) crfd, crfs (respectively) d ds FM fra, frb, frc, frd, frs (respectively) CRM ra, rb, rd, rs (respectively) SIMM IMM UIMM /, //, /// (shaded) About This Book xxxiii