Exception Handling. Precise Exception Handling. Exception Types. Exception Handling Terminology

Transcription

1 Precise Handling CprE 581 Computer Systems Architecture Reading: Textbook, Appendix A Handling I/O Internal s Arithmetic overflow Illegal Instruction Memory Address s Protection violation Data alignment error Page fault Program initiated OS services Trap Debugging -- breakpoints 1 Types Synchronous/asynchronous Program initiated/forced Within or between instructions Restartable/fatal Handling Terminology event IBM 360 VAX Motorola 680x0 Intel 80x86 I/O device request Input/output interuption Device interupt (Level Vectored interupt autovector) Invoking the oper ating system ser vice interuption mode supervisor (unimplemented (INT instruction) Supervisor call (change Interupt from a user instruction)- program on Macintosh Tracing instruction execution (trace (trace) Interupt (singlestep Breakpoint (breakpoint (illegal instruction or break- Interupt (breakpoint Integer arithmetic overflow or underflow; FP trap Page fault (not in main memory) Misaligned memory accesses Memory protection violations Using undefined instructions Hardware malfunctions Power failure (overflow or underflow (only in 370) (specification (protection (operation Machine-check interuption Machine-check inte ruption (integer overflow trap or floating underflow (translation not valid (access control violation (opcode privileged/ reserved (machine-check abort) point) (floating-point coprocessor er rors) (memor y- management unit errors) (address eror) (bus eror) (illegal instruction or breakpoint/unimplemented instruction) (bus eror) Interupt (overflow trap or math unit Interupt (page Interupt (protection Interupt (invalid opcode) Urgent interupt Nonmaskable interrupt 1

2 Interrupts and Pipeline The hard ones are the restartable interrupts; especially the ones that occur in later stages (within type such as page faults, arithmetic exceptions). A page fault in MEM stage not only affects that instruction; but aborts the three instructions following it! Interrupts & Pipeline The objective is to maintain equivalence with the handling of the same interrupt for an unpipelined machine. One hopes to achieve precise interrupts: Interrupt has no effect on the preceding instructions and the interrupting instruction and instructions following it are restarted. Precise Interrupt Handling T-1 T T+1 T+2 T+3 T+4 T+5 T+6 I T-1 I T I T+1 I T+2 Let I T-1 finish. Force (at time T+4) from interrupt handler address. Save the PC for I T, the first instruction to be restarted. Restart there after trap; if a non-branch instruction; fetch later instructions sequentially; else compute branch condition and BTA and fetch later instructions. Interrupt handling contd. The writes of the following instructions are turned off by squashing or zeroing them. The exception handler should save the PC value before entering exception handling. How many PCs need to be saved? Normally just one --- for the interrupting (faulting) instruction. The restoring protocol would be to fetch from PC, increment PC and fetch and so on, unless a branch is encountered. For a branch, evaluate its condition and BTA and load PC with the appropriate address. 2

3 Interrupt handling contd. With Delayed branch, things are not that simple! I T Branch ID taken EX MEM I T+1 Delay slot I T+2 BT +4 Restart with Delay slot The restoring protocol: fetch from, followed by a fetch from, and then move on sequentially. What if the machine has k branch delay slots? How Many PCs need be saved? K-Delay Slots A machine with k delay slots needs to save k+1 PC values;one for the faulting instruction and for k following instructions. Why? Can the faulting instruction and the k following instructions be not-sequentially related? Assume 3 branch-delay slots. Let us save two PCs: for faulting instruction; for potentially branch-target instruction not sequentially related to. K Delay Slots Assume 3 branch-delay slots. Let us save two PCs: for faulting instruction;. I T I T+1 I T+2 I T+3 Delay slot 1 Delay slot 2 Delay slot 3 Branch target Offset of faulting inst +offset, +offset+4,, +(k-1)*offset, Control overhead is high! 3

4 Location of s in 5-stage Pipeline Illegal Arithmetic opcode Page Fault Misaligned data access Memory protection violation Misaligned instruction access Memory protection violation Multiple s handled as soon as it appears: when an exception encountered (in MEM); suspend all the instructions that are in, ID, EX and MEM stages, service the exception and then resume execution from the instruction in MEM stage. When multiple exceptions posted at the same time; one from an earlier instruction given priority. when same instruction generates multiple exceptions; more serious one (earlier one) handled first. Precise Handling Let all the preceding instructions complete; in the mean time stall the faulting and the following instructions. LW LW ADD ADD ID EX ID MEM EX MEM Arith It is not precise as interrupts can be handled out of order. Page Fault CC2 CC6 4

5 LW 10(R1), R10 Program execution order (in instructions) Status Vector Time (in clock cycles) SUB R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 # handling Other Complications In VAX, autoincrement updates state in the middle of an instruction. If this inst is aborted due to an interrupt, it leaves behind altered state! How to implement precise interrupts? Ability to reverse the state! Long running instructions: XOR R10, R1, R11 5