UM0434. e200z3 PowerPC core Reference manual. Introduction

Transcription

1 UM0434 e200z3 PowerPC core Reference manual Introduction The primary objective of this user s manual is to describe the functionality of the e200z3 embedded microprocessor core for software and hardware developers. This book is intended as a companion to the EREF: A Programmer's Reference Manual for Freescale Book E Processors (hereafter referred to as EREF). Book E is a PowerPC architecture definition for embedded processors that ensures binary compatibility with the user-instruction set architecture (UISA) portion of the PowerPC architecture as it was jointly developed by Apple, IBM, and Motorola (referred to as the AIM architecture). This document distinguishes among the three levels of the architectural and implementation definition, as follows: The Book E architecture Book E defines a set of user-level instructions and registers that are drawn from the user instruction set architecture (UISA) portion of the AIM definition PowerPC architecture. Book E also includes numerous supervisor-level registers and instructions as they were defined in the AIM version of the PowerPC architecture for the virtual environment architecture (VEA) and the operating environment architecture (OEA). Because the operating system resources (such as the MMU and interrupts) defined by Book E differ greatly from those defined by the AIM architecture, Book E introduces many new registers and instructions. Freescale Book E implementation standards (EIS) In many cases, the Book E architecture definition provides a general framework, leaving specific details up to the implementation. To ensure consistency among its Book E implementations, Freescale has defined implementation standards that provide an additional layer of architecture between Book E and the actual devices. e200z3 implementation details Each processor typically defines instructions, registers, register fields, and other aspects that are more detailed than either the Book E definition or the EIS. This book describes all of the instructions and registers implemented on the e200z3, including those defined by Book E and by the EIS, as well as those that are e200z3-specific. Information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers responsibility to be sure they are using the most recent version of the documentation. Nov 2013 Rev 2 1/391

2 Table of contents UM0434 Table of contents 1 Organization Bibliography Related documentation Audience Conventions Terminology conventions Acronyms and abbreviations e200z3 core complex overview Overview of the e200z Features Programming model Register set Instruction set VLE APU Interrupts and exception handling Interrupt handling Interrupt classes Interrupt types Interrupt registers Microarchitecture summary Instruction unit features Integer unit features Load/Store unit (LSU) features Memory management unit (MMU) features System bus (core complex interface) features Nexus3 module features Legacy support of PowerPC architecture Instruction set compatibility Memory subsystem Interrupt handling Memory management /391

3 UM0434 Table of contents Reset Little-endian mode Register model PowerPC Book E registers e200z3 - Specific registers e200z3-specific Device Control Registers Processor control registers Machine state register (MSR) Processor ID register (PIR) Processor version register (PVR) System version register (SVR) Registers for integer operations General purpose registers (GPRs) Integer exception register (XER) Registers for branch operations Condition register (CR) Count register (CTR) Link register (LR) SPE and SPFP APU registers Signal processing/embedded floating-point status and control register (SPEFSCR) Accumulator (ACC) Interrupt Registers Interrupt Registers Defined by Book E Exception syndrome register (ESR) VLE mode instruction syndrome Misaligned instruction fetch syndrome Precise external termination error syndrome e200z3 specific interrupt registers Software use SPRs (SPRG0 SPRG7 and USPRG0) Timer registers Timer control register (TCR) Timer status register (TSR) Time base (TBU and TBL) Decrementer register /391

4 Table of contents UM Decrementer auto-reload register (DECAR) Debug registers Debug address and value registers Debug counter register (DBCNT) Debug control and status registers (DBCR0 DBCR3) Debug status register (DBSR) Hardware implementation dependent registers Hardware implementation dependent register 0 (HID0) Hardware implementation dependent register 1 (HID1) Branch target buffer (BTB) registers Branch unit control and status register (BUCSR) L1 cache configuration registers L1 cache configuration register 0 (L1CFG0) MMU registers MMU control and status register 0 (MMUCSR0) MMU configuration register (MMUCFG) TLB configuration registers (TLBnCFG) MMU assist registers (MAS0 MAS4, MAS6) Process ID register (PID0) Support for fast context switching Context control register (CTXCR) SPR register access Invalid SPR references Synchronization requirements for SPRs Special purpose register summary Reset settings Parallel signature unit registers Parallel signature control register (PSCR) Parallel signature status register (PSSR) Parallel signature high register (PSHR) Parallel signature low register (PSLR) Parallel signature counter register (PSCTR) Parallel signature update high register (PSUHR) Parallel signature update low register (PSULR) Instruction model /391

5 UM0434 Table of contents 5.1 Operand conventions Data organization in memory and data transfers Alignment and misaligned accesses e200z3 Floating-Point implementation Unsupported instructions and instruction forms Optionally supported instructions and instruction forms Implementation-Specific instructions BookE instruction extensions Memory access alignment support Memory synchronization and reservation instructions Branch prediction Interruption of instructions by interrupt requests e200z3-specific instructions Integer select APU Debug APU SPE APU instructions Embedded vector and scalar single precision floating point APU instructions Unimplemented SPRs and read only SPRs Invalid instruction forms Instruction summary Instruction index sorted by mnemonic Instruction index sorted by opcode Interrupts and exceptions Overview e200z3 interrupts Exception syndrome register (ESR) Machine state register (MSR) Machine check syndrome register (MCSR) Interrupt vector offset registers (IVORn) Interrupt definitions Critical input interrupt (IVOR0) Machine check interrupt (IVOR1) Data storage interrupt (IVOR2) /391

6 Table of contents UM Instruction storage interrupt (IVOR3) External input interrupt (IVOR4) Alignment interrupt (IVOR5) Program interrupt (IVOR6) Floating-Point unavailable interrupt (IVOR7) System call interrupt (IVOR8) Auxiliary processor unavailable interrupt (IVOR9) Decrementer interrupt (IVOR10) Fixed-Interval timer interrupt (IVOR11) Watchdog timer interrupt (IVOR12) Data TLB error interrupt (IVOR13) Instruction TLB error interrupt (IVOR14) Debug interrupt (IVOR15) System reset SPE APU unavailable interrupt (IVOR32) SPE Floating-Point data interrupt (IVOR33) SPE Floating-Point round interrupt (IVOR34) Exception recognition and priorities Interrupt priorities Interrupt processing Enabling and disabling exceptions Returning from an interrupt handler Process switching Memory management unit Overview MMU features TLB entry maintenance features summary Effective to real address translation Effective addresses Address spaces Virtual addresses and process ID Translation flow Permissions Translation lookaside buffer IPROT invalidation protection in TLB /391

7 UM0434 Table of contents Replacement algorithm for TLB The G bit (of WIMGE) TLB entry field summary Software interface and TLB instructions TLB operations Translation reload Reading the TLB Writing the TLB Searching the TLB TLB coherency control TLB miss exception update TLB load on reset MMU configuration and control registers MMU configuration register (MMUCFG) TLB0 and TLB1 configuration registers Data exception address register (DEAR) MMU control and status register 0 (MMUCSR0) MMU assist registers (MAS) Effect of hardware debug on MMU operation Instruction pipeline and execution timing Overview of operation Control unit Instruction unit Branch unit Instruction decode unit Exception handling Execution units Integer execution unit Load/Store unit Instruction pipeline Description of pipeline stages Instruction buffers Single-Cycle instruction pipeline operation Basic load and store instruction pipeline operation Change-of-Flow instruction pipeline operation /391

8 Table of contents UM Basic Multi-Cycle instruction pipeline operation Additional examples of instruction pipeline operation for load & store Move to/from SPR instruction pipeline operation Stalls caused by accessing SPRs Instruction serialization Interrupt recognition and exception processing Instruction timings SPE and embedded Floating-Point instruction timing Operand placement on performance External core complex interfaces Overview Signal index Signal descriptions Processor state signals JTAG ID signals Internal signals Timing diagrams Processor Instruction/Data transfers Burst accesses Address retraction Address retraction Power management Interrupt interface Power management Overview Power management signals Power management control bits Software considerations for power management Debug considerations for power management Debug support Introduction Overview Software debug facilities /391

9 UM0434 Table of contents Additional debug facilities Hardware debug facilities Debug registers Software debug events and exceptions External debug support OnCE introduction JTAG/OnCE signals OnCE internal interface signals OnCE interface signals OnCE controller and serial interface Access to debug resources Methods for entering debug mode CPU status and control scan chain register (CPUSCR) Instruction address FIFO buffer (PC FIFO) Reserved registers Watchpoint support MMU and cache operation during debug Enabling, using, and exiting external debug Mode: example Nexus3 module Introduction General description Terms and definitions Feature list Enabling Nexus3 operation TCODEs supported Nexus3 Programmer s model Client select control register (CSC) Port configuration register (PCR) Development control register 1, 2 (DC1, DC2) Development status register (DS) Read/Write access Control/Status register (RWCS) Read/Write access data register (RWD) Read/Write access address register (RWA) Watchpoint trigger register (WT) Data trace control register (DTC) /391

10 Table of contents UM Data trace start address 1 and 2 registers (DTSA1 and DTSA2) Data trace end address registers 1 and 2 (DTEA1 and DTEA2) Nexus3 register access through JTAG/OnCE Ownership trace Overview Ownership trace messaging (OTM) OTM error messages OTM flow Program trace Branch trace messaging (BTM) BTM message formats BTM operation Program trace timing diagrams (2 MDO/1 MSEO Configuration) Data trace Data trace messaging (DTM) DTM message formats DTM operation Data trace timing diagrams (8 MDO/2 MSEO Configuration) Watchpoint support Overview Watchpoint messaging Watchpoint error message Watchpoint timing diagram (2 MDO/1 MSEO Configuration) Nexus3 Read/Write access to Memory-Mapped resources Single write access Block write access (Non-Burst Mode) Block write access (Burst Mode) Single read access Block read access (Non-Burst Mode) Block read access (Burst Mode) Error handling Nexus3 pin interface Pins implemented Pin protocol Rules for output messages Auxiliary port arbitration /391

11 UM0434 Table of contents Examples IEEE (JTAG) RD/WR sequences JTAG sequence for accessing internal nexus registers JTAG sequence for read access of Memory-Mapped resources JTAG sequence for write access of Memory-Mapped resources Glossary Revision history /391

12 List of tables UM0434 List of tables Table 1. Terminology conventions Table 2. Acronyms and abbreviated terms Table 3. Scalar and vector embedded floating-point APU instructions Table 4. Interrupt registers Table 5. Exceptions and conditions Table 6. Machine state register (MSR) Table 7. MSR field descriptions Table 8. Processor ID register (PIR) Table 9. PIR Field Descriptions Table 10. Processor version register (PVR) Table 11. PVR field descriptions Table 12. SVR field description Table 13. Integer Exception Register (XER) Table 14. XER field descriptions Table 15. Condition register (CR) Table 16. BI operand settings for CR fields Table 17. CR0 field descriptions Table 18. CR setting for compare instructions Table 19. Count register (CTR) Table 20. Link register (LR) Table 21. Signal processing and embedded floating point status and control register (SPEFSCR). 52 Table 22. SPEFSCR field descriptions Table 23. Save/restore register 0 (SRR0) Table 24. Save/restore register 1 (SRR1) Table 25. Critical save/restore register 0 (CSRR0) Table 26. Critical save/restore register 1 (CSRR1) Table 27. Data exception address register (DEAR) Table 28. Interrupt vector prefix register (IVPR) Table 29. IVPR field descriptions Table 30. Interrupt vector offset registers (IVOR) Table 31. IVOR field descriptions Table 32. IVOR assignments Table 33. Exception syndrome register (ESR) Table 34. ESR field descriptions Table 35. Debug save/restore register 0 (DSRR0) Table 36. Debug save/restore register 1 (DSRR1) Table 37. Machine check syndrome register (MCSR) Table 38. MCSR field descriptions Table 39. Software use SPRs (SPRG0 SPRG7 and USPRG0) Table 40. Timer control register (TCR) Table 41. TCR field descriptions Table 42. Timer status register (TSR) Table 43. Timer status register field descriptions Table 44. Time base upper/lower registers (TBU/TBL) Table 45. Decrementer register (DEC) Table 46. Decrementer auto-reload register (DECAR) Table 47. Instruction address compare registers (IAC1 IAC4) Table 48. Data address compare registers (DAC1 DAC2) /391

13 UM0434 List of tables Table 49. DBCNT register Table 50. DBCR0 Register Table 51. DBCR0 field descriptions Table 52. Debug control register 1 (DBCR1) Table 53. DBCR1 field descriptions Table 54. DBCR2 field descriptions Table 55. DBCR3 register Table 56. DBCR3 field descriptions Table 57. DBSR register Table 58. DBSR field descriptions Table 59. Hardware implementation dependent register 0 (HID0) Table 60. HID0 field descriptions Table 61. Hardware implementation dependent register 1 (HID1) Table 62. HID1 field descriptions Table 63. Branch unit control and status register (BUCSR) Table 64. Branch unit control and status register Table 65. MMU Control and Status Register 0 (MMUCSR0) Table 66. MMUCSR0 field descriptions Table 67. MMU configuration register 1 (MMUCFG) Table 68. MMUCFG field descriptions Table 69. TLB configuration register 0 (TLB0CFG) Table 70. TLB0CFG field descriptions Table 71. TLB configuration register 1 (TLB1CFG) Table 72. TLB1CFG field descriptions Table 73. MAS Register 0 (MAS0) Format Table 74. MAS0 - MMU read/write and replacement control Table 75. MMU assist register 1 (MAS1) Table 76. MAS1 - descriptor context and configuration control Table 77. MMU assist register 2 (MAS2) Table 78. MAS2 - EPN and page attributes Table 79. MMU assist register 3 (MAS3) Table 80. MAS3 - RPN and access control Table 81. MMU assist register 4 (MAS4) Table 82. MAS4 - hardware replacement assist configuration register Table 83. MMU assist register 6 (MAS6)) Table 84. MAS6 - TLB search context register Table 85. Process ID register (PID0) Table 86. Context control register (CTXCR) Table 87. System response to invalid SPR reference Table 88. Additional synchronization requirements for SPRs Table 89. Special purpose registers Table 90. Reset settings for e200z3 resources Table 91. Parallel signature control register (PSCR) Table 92. PSCR field descriptions Table 93. parallel signature status register (PSSR) Table 94. PSSR field descriptions Table 95. Parallel signature high register (PSHR) Table 96. Parallel signature low register (PSLR) Table 97. Parallel signature counter register (PSCTR) Table 98. Parallel signature update high register (PSUHR) Table 99. Parallel signature update low register (PSULR) Table 100. List of unsupported instructions /391

14 List of tables UM0434 Table 101. List of optionally supported instructions Table 102. Implementation-Specific instruction summary Table 103. Memory synchronization and reservation instructions e200z3 specific details Table 104. SPE APU vector multiply instruction mnemonic structure Table 105. Mnemonic extensions for multiply-accumulate instructions Table 106. SPE APU vector instructions Table 107. Vector and scalar SPFP APU floating-point instructions Table 108. Embedded floating-point APU options Table 109. Invalid instruction forms Table 110. Instructions sorted by mnemonic Table 111. Instructions sorted by opcode Table 112. Full instruction listing Table 113. Interrupt classifications Table 114. Exceptions and conditions Table 115. Exception syndrome register (ESR) Table 116. ESR field descriptions Table 117. Processor state definition of MSR Table 118. MSR field descriptions Table 119. Machine check syndrome register (MCSR) Table 120. MCSR field Descriptions Table 121. IVPR register Table 122. IVPR field descriptions Table 123. IVOR register fields Table 124. IVOR assignments Table 125. Critical input interrupt register settings Table 126. Machine check interrupt register settings Table 127. Data storage interrupt register settings Table 128. ISI exceptions and conditions Table 129. Instruction storage interrupt register settings Table 130. External input interrupt register settings Table 131. Alignment interrupt register settings Table 132. Program interrupt register settings Table 133. Floating-Point unavailable interrupt register Settings Table 134. System call interrupt register settings Table 135. Decrementer interrupt register settings Table 136. Fixed-Interval timer interrupt register settings Table 137. Watchdog timer interrupt register settings Table 138. Data TLB error interrupt register settings Table 139. Instruction TLB error interrupt register settings Table 140. Debug exceptions Table 141. Debug interrupt register settings Table 142. TSR watchdog timer reset status Table 143. DBSR most recent reset Table 144. System reset register Settings Table 145. SPE unavailable interrupt register settings Table 146. SPE Floating-Point data interrupt register settings Table 147. SPE Floating-Point round interrupt register settings Table 148. e200z3 exception priorities Table 149. MSR setting due to interrupt Table 150. TLB maintenance programming model Table 151. Page size (for e200z3 Core) and EPN field comparison Table 152. TLB entry bit fields for e200z /391

15 UM0434 List of tables Table 153. tlbivax EA bit definitions Table 154. TLB entry 0 values after Reset Table 155. MMU assist registers summary Table 156. MMU assist register field updates Table 157. Pipeline stages Table 158. Instruction timing by mnemonic Table 159. Timing for integer simple instructions Table 160. SPE load and store instruction timing Table 161. SPE complex integer instruction timing Table 162. SPE vector Floating-Point instruction timing Table 163. Scalar SPE Floating-Point instruction timing Table 164. Performance effects of storage operand placement Table 165. Interface signal definitions Table 166. Processor clock signal description Table 167. Descriptions of signals related to reset Table 168. Descriptions of signals for the address and data buses Table 169. Descriptions of transfer attribute signals Table 170. Descriptions of signals for byte lane specification Table 171. Byte strobe assertion for transfers Table 172. Big-and Little-Endian storage (64-Bit GPR contains A B C D E F G H ) Table 173. Descriptions of signals for transfer control signals Table 174. Descriptions of master ID configuration signals Table 175. Descriptions of interrupt signals Table 176. Descriptions of timer facility signals Table 177. Descriptions of processor reservation signals Table 178. Descriptions of miscellaneous processor signals Table 179. Descriptions of processor state signals Table 180. Descriptions of power management control signals Table 181. Descriptions of debug events signals Table 182. Core Debug/Emulation support signals Table 183. Descriptions of Debug/Emulation (Nexus 1/ OnCE) support signals Table 184. core development support (Nexus3) signals Table 185. JTAG primary interface signals Table 186. Descriptions of JTAG interface signals Table 187. JTAG register ID fields Table 188. JTAG ID register inputs Table 189. Descriptions of JTAG ID signals Table 190. Internal signal descriptions Table 191. Power states Table 192. Descriptions of timer facility and power management signals Table 193. Power management control bits Table 194. Debug registers Table 195. Debug event descriptions Table 196. JTAG/OnCE primary interface signals Table 197. OnCE internal interface signals Table 198. OnCE interface signals Table 199. OnCE status register (OSR) Table 200. OSR field descriptions Table 201. OCMD fields Table 202. OCMD field descriptions Table 203. OnCE control register fields Table 204. OnCE control register bit definitions /391

16 List of tables UM0434 Table 205. OnCE register access requirements Table 206. Methods for entering debug mode Table 207. Control state register (CTL) Table 208. CTL field definitions Table 209. Watchpoint output signal assignments Table 210. Terms and definitions Table 211. Public TCODEs supported Table 212. Error code encodings (TCODE = 8) Table 213. Resource code encodings (TCODE = 27) Table 214. Event code encodings (TCODE = 33) Table 215. Data trace size encodings (TCODE = 5, 6, 13, or 14) Table 216. Nexus3 register map Table 217. Client Select Control Register Table 218. CSC field descriptions Table 219. Port configuration register Table 220. PCR field descriptions Table 221. Development control register 1 (DC1) Table 222. DC1 field descriptions Table 223. Development control register 2 (DC2) Table 224. DC2 field descriptions Table 225. Development status register (DS) Table 226. DS field descriptions Table 227. Read write access control/status register (RWCS) Table 228. RWCS field descriptions Table 229. Read/Write access status bit encodings Table 230. read/write access data register Table 231. RWD data placement for transfers Table 232. RWD byte lane data placement Table 233. Read/write access address register Table 234. Watchpoint trigger register Table 235. WT field descriptions Table 236. Data trace control register Table 237. DTC field descriptions Table 238. Data trace start address registers Table 239. Data trace end address registers Table 240. Data Trace Address range options Table 241. Nexus3 Register Access through JTAG/OnCE (Example) Table 242. Nexus register example Table 243. Ownership trace message format Table 244. Error message format Table 245. Indirect branch message sources Table 246. Direct branch message sources Table 247. Indirect Branch Message (History) Format Table 248. Indirect Branch Message Format Table 249. Direct Branch Message Format Table 250. RCODE encoding Table 251. Debug status message format Table 252. Program correlation message format Table 253. Error message format Table 254. Direct/Indirect branch with synchronization message format Table 255. Indirect branch history with synchronization message format Table 256. Program trace exception summary /391

17 UM0434 List of tables Table 257. Relative address generation and re-creation example Table 258. Data write message format Table 259. Data read message format Table 260. Error message format Table 261. Data write/read with synchronization message format Table 262. Data trace exception summary Table 263. e200z3 bus cycle cases Table 264. Watchpoint message format Table 265. Watchpoint source encoding Table 266. Error message format Table 267. Single write access field settings Table 268. Single read access parameter settings Table 269. Error message format Table 270. JTAG pins for Nexus Table 271. Nexus3 auxiliary pins Table 272. Nexus port arbitration signals Table 273. MSEO Pin(s) protocol Table 274. MDO request encodings Table 275. Indirect branch message example (2 MDO/1 MSEO) Table 276. Indirect branch message example (8 MDO/2 MSEO) Table 277. Direct branch message example (2 MDO/1 MSEO) Table 278. Direct branch message example (8 MDO / 2 MSEO) Table 279. Data write message example (8 MDO/1 MSEO) Table 280. Data write message example (8 MDO/2 MSEO) Table 281. Accessing internal Nexus3 registers through JTAG/OnCE Table 282. Accessing memory-mapped resources (reads) Table 283. Accessing memory-mapped resources (writes) Table 284. Document revision history /391