CIS 371 Spring 2017 Computer Organization and Design 25 April 2017 Final Exam Answer Key

Transcription

1 CIS 371 Spring 2017 Final 1 CIS 371 Spring 2017 Computer Organization and Design 25 April 2017 Final Exam Answer Key 0.) The Easy One (1 point total) Check cover sheet for name, PennKey, and signature. 1.) Performance Pressure (9 points total) For each of the scenarios on the left, list the feature(s) on the right that definitely make sense to incorporate into your processor design. Do not include features whose impact is impossible to determine. For instance, list small caches or big caches only if there is a clear advantage to one or the other, but not if the cache size is totally irrelevant. The first scenario is completed for you. (a) Space Heater: Your heat isn t working so you re running an infinite loop of random instructions that keeps the processor busy while you huddle close to it for warmth and to toast marshmallows: b, c, d, j, k, l (b) Hearing Aid: You need to stream audio data from three microphones, separate speech from background noise, and play the enhanced audio stream through a speaker. Performance must be completely consistent to avoid skips and clicks in the output. The processor and battery must fit comfortably behind the user s ear, placing severe constraints on available power and cooling. a, c, (optional: e), i (Predicated instructions eliminate branches and make performance more predictable; little or no cache and nothing fancy to minimize power consumption.) (c) Ticketmaster: You re running a web server that sells tickets to concerts and shows. Most of shows have low volume, but a few blockbusters generate a mad rush of customers trying to buy tickets all at once. For simplicity, assume the web server handles all requests from a single thread of execution rather than spawning a new process for each request. b, d, e, i, j, k, l (Large write-back caches because lots of data will get rewritten frequently. Single-threaded server also means we want the fastest possible micro-architecture.) (a) Small caches (b) Big caches (c) 0 or 1 levels of cache (d) 2 or more levels of cache (e) Write-back cache (f) Write-through cache (g) Inclusive cache (h) Exclusive cache (i) Predicated instructions (j) Fancy branch predictor (k) Superscalar pipeline (l) Out-of-order pipeline (d) Web Crawler: You re computing the frequency count of every word on every web page in existence as part of generating the latest, greatest search engine. (There is now so much drivel on the web that indexing must be spread across hundreds of systems. You re system is only responsible for frequency counts.) All you re really doing is loading HTML files one by one, computing a hash of each word on the page, and incrementing a counter stored in the hash bucket. But you have to do this extra fast in order to keep up with the rest of the indexing process. b, d, e, k, l (This algorithm is pretty much straight-line code, so we care about performance, but not branch prediction. Frequency counters get rewritten often, so write-back is useful.)

2 CIS 371 Spring 2017 Final 2 2.) Persistence of Virtual Memory (10 points total) Assume you have a 32-bit, byte-addressed machine with virtual addressing. However, any memory address whose two high-order bits are 11 is treated as unmapped. These addresses are only accessible in privileged mode i.e. by the operating system and bypass virtual address translation. (This is the addressing scheme using by Linux and some versions of Windows on 32-bit x86 machines.) Answer all the questions below. Your answer can be expressed as a multiple of a power of 2, or in terms of KB, MB, GB, or TB as appropriate. 2.1) (1 point) What is the maximum amount of physical memory this system can address? 4GB 2.2) (2 points) What is the maxiumum amount of virtual memory any single process on this system can address? = = 3GB 2.3) (2 points) How many virtual pages are available to each process, assuming 4KB pages? pages 2.4) (2 points) Assuming each page table entry is 4 bytes, how much memory would a single-level page table require? = 3MB 2.5) (2 points) Assuming a two-level page table where half the bits of the virtual page number are used to index the first level, and the other half are used to index the second level, how many second-level page tables can a process use if its total page table size is limited to 400KB? (n + 1) n 99 pages

3 CIS 371 Spring 2017 Final 3 3.) Order of Out (20 points total) Complete the cycle chart for the program listing below, including arrows indicating all bypassed values (including from W to D). Assume a dual-issue out-of-order pipeline with full bypassing. The front end of the pipeline contains the Fetch (F) and Decode (D) stages, with register read occurring in decode. The back end contains the Issue (I), Execute (X), Memory (M), and Writeback (W). And of course there is a Commit (C) stage at the very end. Branches are predicted not taken and are resolved in execute, just like in your assignments. The pipeline can also retire at most two instructions per cycle. Do not include squashed instructions in the chart. You should not need all the rows or columns provided. The first instruction has been filled in for you..code.addr 0x0000 I0 CONST R7, 0 I1 LDR R5, R7, #6 I2 LDR R2, R5, #4 I3 ADDI R7, R7, #0 I4 BRz I7 I5 ADDI R5, R5, #0 I6 BRz.END I7 STR R5, R7, #1 I8 RET.END (program ends here) Label I0 F D I X M W C I1 F D I X M W C I2 F D I X M W C I3 F D I X M W C I4 F D I X M W C I7 F D I X M W C I8 F D I X M W C I0 F D I X M W C. I1 F D I X M W C Because branch instructions are PC-relative, I1 was overwritten with a branch to PC+3, i.e. I4, not with a branch to END. The program therefore enters an infinite loop at this point I1 I4 I7 I8 I0 I1...

4 CIS 371 Spring 2017 Final 4 4.) Don t Make a Hash of the Cache Part 1 (16 points total) For each of the following two sequences of operations, complete the tables of the L1 cache contents after all operations have been complete. Assume a 16-bit, word-addressed architecture (à la LC4) with an 8-entry write-back, write-allocate cache, one-word block sizes, and LRU replacement policy. For each sequence of operations, you will fill out a table for a 4-way set associative cache and a fully associative cache. We are asking you to write the full memory address in each cache entry rather than just the tag bits so you can easily write it in hexadecimal. The LRU column should contain a number between 1 and 8 where 1 is the most recently used item, and 8 is the least recently used. Complete the tables for a 4-way set associative and a fully associative cache after executing the following sequence of instructions. Assume that all cache lines are invalid when the sequence of operations starts. Read 0x4949 from address 0xF222 Read 0xAAAA from address 0x6767 Read 0x2345 from address 0xCABB Read 0x1188 from address 0xFACE Read 0x4444 from address 0x1234 Read 0x5555 from address 0xDAC1 Read 0xACED from address 0xACED Read 0x9999 from address 0x Way Set Associative Set Address Data Valid Dirty LRU 0 F FACE AAAA CABB DAC ACED ACED Fully Associative Address Data Valid Dirty LRU F AAAA CABB FACE DAC ACED ACED

5 CIS 371 Spring 2017 Final 5 5.) Don t Make a Hash of the Cache Part 2 (16 points total) Following the same directions as in the previous questions, complete the tables for a 4-way set associative and a fully associative cache after executing the following sequence of instructions. Assume each cache variant starts out from its state in the previous question, as if these instructions immediately follow the previous sequence. Write 0x8201 to address 0x8640 Read 0x4444 from 0x1234 Read 0x1776 from 0xBEDD Write 0x2017 to address 0x Way Set Associative Set Address Data Valid Dirty LRU BEDD CABB DAC ACED ACED Fully Associative Address Data Valid Dirty LRU BEDD FACE DAC ACED ACED