ECE331 Homework 4. Due Monday, August 13, 2018 (via Moodle)

Transcription

1 ECE331 Homework 4 Due Monday, August 13, 2018 (via Moodle) 1. Below is a list of 32-bit memory address references, given as hexadecimal byte addresses. The memory accesses are all reads and they occur in the order given 0xA00, 0x864, 0x50234, 0xA00, 0xF0C, 0x50234, 0x63C, 0x128, 0x3C4, 0x34B4, 0x50234 a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or miss, assuming the cache is initially empty b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 8 two-word blocks. Also list if each reference is a hit or miss, assuming the cache is initially empty c. For each of these references, identify the binary address, the tag, and the index given a two-way set-associative cache with 16 one-word blocks (Hint: there are 8 sets). Also list if each reference is a hit or miss, assuming the cache is initially empty. Use a LRU replacement strategy. d. Calculate the total number of bits required for the cache listed in (c). Include tag storage, dirty bit storage, valid bit storage, and the data storage

2 2. Given the following assumptions, fill out the table of data cache content on the next two pages based on memory access sequence shown in the following table. Cache is initially empty The data cache is a direct mapped cache The width of memory address is 8-bit and it is a byte address The cache block size is 4 bytes Write through strategy is used in this cache Memory Accesses # Access Size Access Type Byte Address in Binary 1 Byte Read Byte Read Byte Read Word Write Byte Read Word Write Word Read Byte Read Byte Read Byte Read

3 Data Cache Content Note: a.) For locations never accessed, leave the corresponding tag and data boxes blank. b.) Indicate the valid bit for each cache block. Use V for valid and I for invalid. c.) The block data should be given in the format of M [block address]. d.) Mark each access in order for up to 4 accesses. The first access should be the first one listed. Index V Tag Data

4 (b) What is the miss rate of the cache for the memory accesses in question (a)?

5 3. The following C program is run on a machine with a data cache that has two-word (8 bytes) blocks and the data capacity of the data cache is 128 bytes. Assume that only references to the array incur memory accesses and the cache is empty at the very beginning. Hint: a variable with int type contains four bytes and the MIPs uses byte addresses int i, c, array[128]; c = 0; for (i=0; i<128; i++) { c = c+array[i]; } (a) How many cache lines are there if the cache is direct mapped? Show your work. (b) How many sets are there if the cache is two-way associative? Which address bits are used for indexing the set in a 32-bit address? Please present the result in Addr[x:y] format (for example, Addr[8:5] means that bit 8 to bit 5 in the address are used for indexing). Show your work. (c) If a direct mapped cache is used, what is the expected miss rate after program execution. Show your work.

6 (d) If a two-way associative cache is used, what is the expected miss rate after program execution. Show your work. (e) If a four-way associative cache is used, what is the expected miss rate after execution the program. Show your work. 4. The diagram below illustrates a blocked, direct-mapped cache for 32-bit data words with 32-bit byte addresses

7 (a) What is the maximum number of words of data from the main memory that can be stored in the cache at any one time? (b) How many bits of the address are used to select which line of the cache is accessed? (c) How many bits wide is the tag field?

8 (d) Briefly explain the purpose of the one-bit V field associated with each cache line (e) Assume that location 0xCF120 was present in the cache. Using the row and column labels from the figure, in what location(s) could we find the data from that location? What would the value of the tag field have to be for the cache row in which the data appears? (f) Can data from location 0xF6768 and 0xF67F8 be present in the cache at the same time? What about the data from locations 0xB20738 and 0x2034? Explain? (g) When an access causes a cache miss, how many words need to be fetched from memory to fill the appropriate cache location?