CENG 5133 Computer Architecture Design Spring Sample Exam 2

Transcription

1 CENG 533 Computer Architecture Design Spring 24 Sample Exam 2. (6 pt) Determine the propagation delay and contamination delay of the following circuit using the gate delays given below. Gate t pd (ps) t cd (ps) 2-input AND input NAND input NOR input NAND 3 25 t pd : t cd : 2. (6 pt) Draw a state graph for a Moore sequential circuit. The circuit has one input (X) and one output (Z). Z becomes whenever input sequence occurs. The circuit resets after a output is generated. 3. (6 pt) Show how the data, $ABCDEF2, is mapped into memory starting the address, $8, using big-endian approach and little-endian approach. Big Endian Little Endian Address Data Address Data $7FD $7FD $7FE $7FE $7FF $7FF $8 $8 $8 $8 $82 $82 $83 $83

2 CENG 533 Computer Architecture Design Spring (6 pt) Assume that the following 32-bit binary value represents a machine-level MIPS assembly instruction. a. If the binary value represents the machine code of an R-format instruction, what is the 5-digit binary number representing the destination register? b. If the binary value represents the machine code of an I-format instruction, what is the 5-digit binary number representing the (first) source register? c. If the binary value represents the machine code of a J-format instruction, what is the opcode field? 5. (4 pt) The contents of the registers (in hexadecimal) are given below. For each instruction, calculate the address of the data that is transferred. Note that register contents are given in hexadecimal and offsets are given in decimal. R = x2222 R2 = xaaaabbbb R3 = x R4 = xccccdddd a. lw R, (R2) Address: (in hexa) b. sw R3, 32(R4) Address: (in hexa) 6. (5 pt) Write down the operation (add, subtract, or, etc.) performed by ALU for each instruction given below. lw R, (R2) subi R7, R, add R4, R3, R2 or R, R2, R3 bne R4, R,loop ALU Operation 2

3 CENG 533 Computer Architecture Design Spring (6 pt) The datapath for 5-stage MIPS Pipeline Architecture is given below. For each instruction given below, list the resources that do useful work during the execution of the instruction. When listing, use the numbers associated with the resources. Ignore MUXes. PC' PCF 4 A RD Memory InstrD 25:2 2:6 2:6 5: 5: A A2 A3 WD3 WE3 Register File Sign Extend RD RD2 RtE RdE SignImmE SrcAE SrcBE WriteDataE WriteRegE4: <<2 ZeroM WE ALUOutM A RD Data Memory WriteDataM WD WriteRegM4: PCBranchM ALUOutW ReadDataW WriteRegW4: PCPlus4F PCPlus4D PCPlus4E Fetch Decode Execute Memory Writeback ResultW Program Counter 2 Adder in IF stage 3 Memory 4 Register File 5 Sing-extension Unit 6 Shift-left-2 Unit 7 Adder in EX stage 8 ALU 9 Data Memory sw R, (R2) bne R4, R, loop Resources used 8. (5 pt) Assume that a processor uses -bit dynamic branch predictor and it is initially set to T. For the sequence of branch outcomes given below, indicate if branches are predicted correctly or not. What is the branch prediction accuracy? (T: Taken, NT: Not-Taken and C: Correct, I: Incorrect) Branch Outcome NT NT NT T T T NT NT T NT Correct/Incorrect Branch Prediction Accuracy : 3

4 CENG 533 Computer Architecture Design Spring ( pt) The 5-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: The architecture fully supports forwarding, Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, Register R4 is initially. L: lw R, (R4) // R <- Mem[R4+] add R3, R, R2 // R3 <- R + R2 sw R3, (R4) // Mem[R4+] <- R3 subi R4, R4, 4 // R4 <- R4 4 bne R4, R, L // branch if R4!= a. (4 pt) Show the pipeline timing diagram for one iteration of the loop. Clock Cycle lw R, (R4) F D X M W add sw R3, R, R2 R3, (R4) subi R4, R4, 4 bne lw R4, R, L R, (R4) b. (2 pt) How many clock cycles are needed to execute the entire loop? c. (2 pt) How many instructions are executed to complete the entire loop? d. (2 pt) What is the size of the memory (in bytes) needed to store this code fragment into memory?. (5 pt) A two-way set-associative cache has a total of 4 blocks and each block holds word of data. For the following memory references, determine the final cache content assuming LRU (Least Recently Used) replacement policy is in use. Assume that the cache is initially empty; memory is word-addressable; and memory references are given in decimal. Memory References:,, 5,,, 34,, 2 Block # 2 3 Final Content 4

5 CENG 533 Computer Architecture Design Spring 24. (5 pt) A four-way set-associative cache contains 32KB of useful data (not including tag or control bits). Assuming that the block size is 8-byte and the address is 3-bit, find the number of bits needed for tag, index, and byte select fields of the address. Number of bits for offset Number of bits for index Number of bits for tag : : : 5