CSC 252: Processor Architecture

Transcription

1 S 252: Processor rchitecture Hardware omponents of a omputer System Processor atapath ontrol Input and Output devices 2/21/ /21/ The Principle of bstraction Grouping principle Levels/layers of abstraction by which each layer only needs to understand that immediately above and below it 2/21/ Set rchitecture ssembly Language View Processor state Registers,, s addl, movl, leal, How instructions are encoded as bytes Layer of bstraction bove: how to program machine Processor executes instructions in a sequence elow: what needs to be built Use variety of tricks to make it run fast.g., execute multiple instructions pplication Program ompiler simultaneously 2/21/ IS PU esign ircuit esign hip Layout OS S 256/456 - Spring

2 asic Issues in Set esign Goal: find a language that makes it easy to build both the hardware and the compiler while maximizing performance and minimizing cost What operations (and how many) should be provided How (and how many) operands are specified What data types and sizes How to encode these into consistent instruction formats Typical Operations ata movement rithmetic Logical Shift ontrol (jump/branch) Subroutine linkage Interrupt Synchronization ultimedia 2/21/ /21/ Register Immediate Register indirect isplacement Indexed irect (or absolute) indirect uto- Scaled indexed ddressing odes Scaled Indexed ddressing ode ost General Form (Rb,Ri,S) em[reg[rb]+s*reg[ri]+ ] : onstant displacement 1, 2, or 4 bytes Rb: ase register: ny of 8 integer registers Ri: Index register: ny, except for %esp S: Scale: 1, 2, 4, or 8 Special ases (Rb,Ri) (Rb,Ri) (Rb,Ri,S) em[reg[rb]+reg[ri]] em[reg[rb]+reg[ri]+] em[reg[rb]+s*reg[ri]] 2/21/ /21/ S 256/456 - Spring

3 Format an be fixed length simpler decoding variable length higher code density/smaller program Large instruction word (encoding multiple instructions and dependences among those instructions) If we have many operands per instruction and many addressing modes, we need an address specifier per operand/result If we have a load-store architecture with 1 address per instruction and one or two addressing modes, we can encode the addressing mode in the opcode 2/21/ IS Sets omplex Set omputer ominant style through mid-80 s Philosophy dd instructions to perform typical programming tasks Variable length encodings Variable execution times ultiple formats for specifying operands Implementation artifacts hidden from machine-level programs Stack-oriented instruction set Use stack to pass arguments, save program counter xplicit push and pop instructions ny instruction can access addl %eax, 12(%ebx,%ecx,4) requires read and write omplex address calculation ondition codes 2/21/ Set as side effect of arithmetic and logical instructions RIS Sets Reduced Set omputer Internal project at I, later popularized by Hennessy (Stanford) and Patterson (erkeley) Fewer, simpler instructions ight take more to get given task done an execute them with small and fast hardware Fixed length encoding Simple addressing formats (typically just base+displacement) Register-oriented instruction set any more (typically 32) registers Use for arguments, return pointer, temporaries Only load and store instructions can access No ondition codes - test instructions return 0/1 in register Implementation artifacts exposed to machine-level programs 2/21/ $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15 $0 $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 IPS Registers onstant 0 Reserved Temp. Return Values Procedure arguments aller Save Temporaries: ay be overwritten by called procedures $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $30 $31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $t8 $t9 $k0 $k1 $gp $sp $s8 $ra allee Save Temporaries: ay not be overwritten by called procedures aller Save Temp Reserved for Operating Sys Global Pointer Stack Pointer allee Save Temp Return ddress 2/21/ S 256/456 - Spring

4 R-R IPS xamples Op Ra Rb Rd Fn addu $3,$2,$1 # Register add: $3 = $2+$1 R-I Op Ra Rb Immediate addu $3,$2, 3145 # Immediate add: $3 = $ sll $3,$2,2 # Shift left: $3 = $2 << 2 ranch Op Ra Rb Offset beq $3,$2,dest # ranch when $3 = $2 Load/Store Op Ra Rb Offset lw $3,16($2) # Load Word: $3 = [$2+16] 2/21/2008sw $3,16($2) # Store Word: [$2+16] = $3 13 IS vs. RIS Original ebate Strong opinions! IS proponents---easy for compiler, fewer code bytes RIS proponents---better for optimizing compilers, can make run fast with simple chip design urrent Status For desktop processors, choice of IS not a technical issue With enough hardware, can make anything run fast ode compatibility more important For embedded processors, RIS makes sense Smaller, cheaper, less power 2/21/ Overview of Logic esign Fundamental Hardware Requirements ommunication How to get values from one place to another omputation Storage its are Our Friends verything expressed in terms of values 0 and 1 ommunication Low or high voltage on wire omputation ompute oolean functions Storage Store bits of information 2/21/ a b omputing with Logic Gates out a b out a out out = a && b out = a b out =!a Outputs are oolean functions of inputs Respond continuously to changes in inputs With some, small delay Voltage nd Or Not Rising elay Falling elay a && b b 2/21/ Time a S 256/456 - Spring

5 ombinational ircuits cyclic Network 0 rithmetic Logic Unit Primary Inputs Primary Outputs Y X L U OF ZF F X + Y Y X L U OF ZF F X - Y Y X L U OF ZF F X & Y Y X L U OF ZF F X ^ Y cyclic Network of Logic Gates ontinously responds to changes on primary inputs Primary outputs become (after some delay) oolean functions of primary inputs 2/21/ ombinational logic ontinuously responding to inputs ontrol signal selects function computed orresponding to 4 arithmetic/logical operations in Y86 lso computes values for condition codes 2/21/ Sequential Logic: and ontrol Sequential: Output depends on the current input values and the previous sequence of input values. re yclic: Output of a gate feeds its input at some future time. : Remember results of previous operations Use them as inputs. xample of use: uild registers and units. 2/21/ s Signal used to synchronize activity in a processor very operation must be completely in the time between two clock pulses (or rising edges) --- the cycle time aximum clock rate (frequency) determined by the slowest logic path in the circuit (the critical path) 2/21/ S 256/456 - Spring

6 ata dge-triggered Latch T Trigger Only in latching mode for brief period T Rising clock edge Value latched depends on data as clock rises Output remains stable at Time all other times 2/21/ R S Q i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 Registers Structure Stores word of data ifferent from program registers seen in assembly code ollection of edge-triggered latches Loads input on rising edge of clock 2/21/ o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 I O Input = y State = x x Register Operation Output = x Stores data bits Rising clock For most of time acts as barrier between input and output s clock rises, loads input State = y Output = y 2/21/ y In Load State achine xample Load In Out omb. Logic 0 L U 0 1 UX ccumulator circuit Load or accumulate on each cycle 2/21/ Out x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 0 +x 1 x 0 +x 1 +x 2 x 3 x 3 +x 4 x 3 +x 4 +x 5 S 256/456 - Spring

7 Random-ccess Read ports Register Stores multiple words of ddress input specifies which word to read or write Register Holds values of program registers %eax, %esp, etc. Register identifier serves as address I 8 implies no read or write performed ultiple Ports val src val src an read and/or write multiple words in one cycle 2/21/2008 ach has separate address and data input/output 25 W valw dstw Write port x 2 val src val src 2 2 Register x Register Register File Timing x W valw dstw y 2 Reading Like combinational logic Output data generated based on input address fter some delay Writing Like register Update only as clock rises Rising clock Register 2/21/ y W valw dstw uilding locks ombinational Logic ompute oolean functions of inputs ontinuously respond to input changes Operate on data and implement control Storage lements Store bits ddressable memories Non-addressable registers Loaded only as clock rises Register 2/21/ val src val src fun L U W valw dstw 0 UX 1 = Y86 Processor State Program registers %eax %ecx %edx %ebx %esi %edi %esp %ebp ondition codes OF ZF SF Program Registers Same 8 as with I32. ach 32 bits ondition odes Single-bit flags set by arithmetic or logical instructions OF: Overflow ZF: Zero SF:Negative Program ounter Indicates address of instruction yte-addressable storage array Words stored in little-endian byte order 2/21/ S 256/456 - Spring

8 Format Y86 s 1--6 bytes of information read from an determine instruction length from first byte Not as many instruction types, and simpler encoding than with I32 ach accesses and modifies some part(s) of the program state ncoding Registers ach register has 4-bit I %eax %ecx %edx %ebx %esi %edi %esp %ebp Same encoding as in I32 Register I 8 indicates no register Will use this in our hardware design in multiple places /21/ /21/ xample ddition Generic Form addl r, r 6 0 r r dd value in register r to that in register r Store result in register r Note that Y86 only allows addition to be applied to register data Set condition codes based on result e.g., addl %eax,%esi ncoding: Two-byte encoding First indicates instruction type Second gives source and destination registers ncoded Representation rithmetic and Logical Operations ode dd addl r, r 6 0 r r Subtract (r from r) nd subl r, r 6 1 r r andl r, r 6 2 r r xclusive-or Function ode xorl r, r 6 3 r r Refer to generically as OPl ncodings differ only by function code Low-order 4 bits in first instruction byte Set condition codes as side effect 2/21/ /21/ S 256/456 - Spring

9 rrmovl r, r 2 0 r r ove Operations irmovl V, r r V Register --> Register Immediate --> Register ove xamples I32 Y86 ncoding movl $0xabcd, %edx irmovl $0xabcd, %edx cd ab movl %esp, %ebx rrmovl %esp, %ebx movl -12(%ebp),%ecx movl %esi,0x41c(%esp) mrmovl -12(%ebp),%ecx rmmovl %esi,0x41c(%esp) f4 ff ff ff c rmmovl r, (r) 4 0 r r Register --> movl $0xabcd, (%eax) movl %eax, 12(%eax,%edx) mrmovl (r), r 5 0 r r --> Register movl (%ebp,%eax,4),%ecx Like the I32 movl instruction Simpler format for addresses Give different names to keep them distinct 2/21/ /21/ Y86 Set yte nop 0 0 halt 1 0 rrmovl r, r 2 0 r r irmovl V, r r V addl 6 0 subl 6 1 andl 6 2 xorl 6 3 rmmovl r, (r) 4 0 r r jmp 7 0 mrmovl (r), r 5 0 r r jle 7 1 OPl r, r 6 fn r r jl 7 2 jxx est 7 fn est je 7 3 call est 8 0 est jne 7 4 ret 9 0 jge 7 5 pushl r 0 r 8 jg 7 6 2/21/2008 popl r 0 r 8 35 SQ Hardware Structure State Program counter register () ondition code register () Register File emories ccess same space ata: for reading/writing program data : for reading instructions Flow Read instruction at address specified by Process through stages Update program counter ecode icode, ifun r, r 2/21/ new val, val ddr, ata ch alu, alu src, src dst, dst val ata val val, val Register S 256/456 - Spring

10 SQ Stages Read instruction from instruction ecode Read program registers ompute value or address Read or write data Write ack Write program registers Update program counter ecode icode, ifun r, r 2/21/ new val, val ddr, ata ch alu, alu src, src dst, dst val ata val val, val Register icode ifun r r Format ecoding Optional Optional 5 0 r r byte icode:ifun Optional register byte r:r Optional constant word 2/21/ xecuting rith./logical Operation Read 2 bytes ecode Read operand registers Perform operation Set condition codes OPl r, r 6 fn r r o nothing Update register Update Increment by 2 2/21/ Stage omputation: rith/log. Ops ecode Write OPl r, r icode:ifun 1 [] r:r 1 [+1] +2 val R[r] val R[r] val val OP val Set R[r] val back update Read instruction byte Read register byte ompute next Read operand Read operand Perform operation Set condition code register result Update Formulate instruction execution as sequence of simple steps Use same general form for all instructions 2/21/ S 256/456 - Spring

11 Read 6 bytes ecode Read operand registers ompute effective address xecuting rmmovl rmmovl r, (r) 4 0 r r Write to o nothing Update Increment by 6 Stage omputation: rmmovl rmmovl r, (r) icode:ifun 1 [] Read instruction byte r:r 1 [+1] Read register byte 4 [+2] Read displacement +6 ompute next ecode val R[r] Read operand val R[r] Read operand val val + ompute effective address 4 [val] val Write value to Write back update Update Use for address computation 2/21/ /21/ Read 2 bytes ecode Read stack pointer Increment stack pointer by 4 xecuting popl popl r b 0 r 8 Read from old stack pointer Update stack pointer Write result to register Update Increment by 2 2/21/ ecode Write Stage omputation: popl popl r icode:ifun 1 [] r:r 1 [+1] +2 val R[%esp] val R [%esp] val val + 4 val 4 [val] R[%esp] val back R[r] val update Use to stack pointer ust update two registers Popped value New stack pointer Read instruction byte Read register byte ompute next Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer result Update 2/21/ S 256/456 - Spring

12 xecuting Jumps jxx est 7 fn est fall thru: target: XX XX XX XX Not taken Taken ecode Stage omputation: Jumps jxx est icode:ifun 1 [] 4 [+1] +5 Read instruction byte Read destination address Fall through address Read 5 bytes Increment by 5 ecode o nothing etermine whether to take branch based on jump condition and condition codes o nothing o nothing Update Set to est if branch taken or to ed if not branch 2/21/ Write ch ond(,ifun) back update ch? : ompute both addresses Take branch? Update hoose based on setting of condition codes and branch condition 2/21/ Read 5 bytes Increment by 5 ecode Read stack pointer ecrement stack pointer by 4 xecuting call call est 8 0 est return: target: XX XX XX XX Write ed to new value of stack pointer Update stack pointer Update Set to est 2/21/ Stage omputation: call call est icode:ifun 1 [] Read instruction byte 4 [+1] +5 Read destination address ompute return point ecode val R[%esp] Read stack pointer val val + 4 ecrement stack pointer 4 [val] Write return value on stack Write R[%esp] val Update stack pointer back update Set to destination Use to decrement stack pointer Store ed 2/21/ S 256/456 - Spring

13 xecuting ret ret 9 0 Stage omputation: ret ret icode:ifun 1 [] Read instruction byte return: Read 1 byte ecode Read stack pointer Increment stack pointer by 4 XX XX Read return address from old stack pointer Update stack pointer Update Set to return address 2/21/ ecode val R[%esp] Read operand stack pointer val R[%esp] Read operand stack pointer val val + 4 Increment stack pointer val 4 [val] Read return address Write R[%esp] val Update stack pointer back update val Set to return address Use to stack pointer Read return address from 2/21/ ecode Write omputation Steps icode,ifun r,r val, src val, src val ond code val dst back dst update OPl r, r icode:ifun 1 [] r:r 1 [+1] +2 val R[r] val R[r] val val OP val Set R[r] val Read instruction byte Read register byte [Read constant word] ompute next Read operand Read operand Perform operation Set condition code register [ read/write] result [ result] Update ll instructions follow same general pattern iffer in what gets computed on each step 2/21/ ecode Write back update omputation Steps icode,ifun r,r val, src val, src val ond code val dst dst call est icode:ifun 1 [] 4 [+1] +5 val R[%esp] val val [val] R[%esp] val Read instruction byte [Read register byte] Read constant word ompute next [Read operand ] Read operand Perform operation [Set condition code reg.] [ read/write] [ result] result Update ll instructions follow same general pattern iffer in what gets computed on each step 2/21/ S 256/456 - Spring

14 omputed Values SQ Hardware new New icode code ifun function rinstr. Register rinstr. Register constant Incremented ecode src Register I src Register I dst estination Register dst estination Register val Register value val Register value val result ch ranch flag val Value from Key lue boxes: predesigned hardware blocks.g., memories, Gray boxes: control logic escribe in HL White ovals: labels for signals Thick lines: 32- bit word values Thin lines: 4-8 bit values otted lines: 1- bit values ecode ch icode ifun r em. control r read write val ata ddr val data out ata val fun. val Register dst dst src src dst dst src src 2/21/ /21/ Possible Implementation Strategies Single-cycle control ulti-cycle control Pipelined (in-order execution) Superscalar and out-of-order execution Single-ycle ontrol annot use any hardware unit twice in one cycle ultiple datapath elements (e.g., and er) if needed for multiple purposes ultiple reads or writes to or register require multiporting cycle must accommodate instruction with the longest latency 2/21/ /21/ S 256/456 - Spring

15 ulti-cycle ontrol Split single instruction into multiple pieces individual pieces using hardwired finite state machine (FS) or microprogramming an finish simple instructions in fewer cycles an run clock faster Still execute a single instruction at a time Pipelined atapath ultiple instructions overlapped in execution Improve throughput, not individual instruction execution time xploit parallelism among instructions in a sequential stream alance length of each stage. Ideally - Time between instrs pipelined = Time between instrs non-pipelined /Number of pipe stages 2/21/ /21/ Hazards SQ Hardware new New val Structural (e.g., instruction/data fetch) ontrol (e.g., jeq) ata (e.g., add followed by sub reading dst register of add) Stages occur in sequence One operation in process at a time ch em. control read write val ata ddr data out ata fun. val val dst dst src src dst dst src src ecode Register icode ifun r r 2/21/ /21/ S 256/456 - Spring

16 S Hardware em. control read write val ata data out dding Pipeline Registers val, val W_icode, W_val W_val, W_val, W_dst, W_dst ddr ata val val Still sequential implementation Reorder stage to put at beginning Stage Task is to select for current instruction ased on results computed by previous instruction Processor State is no longer stored in register ut, can determine based on other stored information ecode ch icode ifun r picode r val val fun. Register pch pval pval pvalp val dst dst src src dst dst src src ecode ch icode, icode, ifun r, r pstate ddr, ata alu, alu src, src dst, dst ata val val, val Register ecode _icode, _ch, _val W icode, ifun, r, r, ddr, ata ch d_src, d_src val alu, alu ata val val, val f_ Register pred 2/21/ /21/ F Select current Read instruction ompute ed ecode Read program registers Operate Read or write data Write ack Update register W Pipeline Stages ecode W_icode, W_val icode, ifun, r, r, ddr, ata 2/21/ _icode, _ch, _val F ch d_src, d_src val alu, alu ata W_val, W_val, W_dst, W_dst val val, val f_ Register pred PIP- Hardware Pipeline registers hold intermediate values from instruction execution Forward (Upward) Paths Values passed from one stage to next annot jump past stages e.g., passes through decode 2/21/ W ecode F icode _ch em. control r f_ Select read write val val dst dst ata ddr Select data out data in icode ch val val dst dst fun. Register dst dst _val icode ifun val val dst dst src src icode ifun r e_ch pred d_rval Predict src d_src W_val W_val _val W_val src d_src S 256/456 - Spring

17 Feedback Paths Predicted Guess value of next ranch information Jump taken/not-taken Fall-through or target address Return point Read from Register updates To register write ports 2/21/ W ecode F icode _ch em. control r f_ Select read write val val dst dst ata ddr Select data out data in icode ch val val dst dst d_rval fun. Register dst dst Predict _val icode ifun val val dst dst src src icode ifun r e_ch pred src d_src W_val W_val _val W_val src d_src Predicting the Instr valid F icode ifun r Split yte 0 Select pred Start fetch of new instruction after current one has completed fetch stage Not enough time to reliably determine next instruction Guess which instruction will follow Recover if prediction was incorrect 2/21/ r lign ytes 1-5 Need Need regids Predict _icode _ch _val W_icode W_val Our Prediction Strategy s that on t Transfer ontrol Predict next to be lways reliable all and Unconditional Jumps Predict next to be (destination) lways reliable onditional Jumps Predict next to be (destination) Only correct if branch is taken Typically right 60% of time Return on t try to predict 2/21/ Recovering from isprediction Instr valid F icode ifun r ispredicted Jump Will see branch flag once instruction reaches stage an get fall-through from val Return Will get return when ret reaches write-back stage Split 2/21/ yte 0 Select pred r lign ytes 1-5 Need Need regids Predict _icode _ch _val W_icode W_val S 256/456 - Spring

18 -level Parallelism Pipelining/super-pipelining Out-of-order execution Super-scalar multiple instructions per pipeline stage ependences Very Large Word (VLIW) ultiple instructions per pipeline stage ependences taken care of by compiler isclaimer Parts of the slides were developed by the course text authors: ave O Hallaron and Randy ryant. The slides are intended for the sole purpose of instruction of computer organization at the University of Rochester. ll copyrighted materials belong to their original owner(s). 2/21/ /21/ S 256/456 - Spring