ECE 274 Digital Logic Fall 2008

Transcription

1 Register ehavior ECE 274 Digital Logic Fall 28 equential Logic Design using Verilog Verilog for Digital Design Ch. 3 equential circuits have storage Register: most common storage component N-bit register stores N bits tructure may consist of connected flip-flops I3 I2 I I 4-bit register I3 I2 I I reg(4) 3 2 D D D D R R R R Register ehavior Vectors Register ehavior Constants Typically just describe register behaviorally Declare output as reg variable to achieve storage Uses vector types Collection of bits More convenient than declaring separate bits like I3, I2, I, I Vector's bits are numbered Options: [:3], [:4], etc. [3:] Most-significant bit is on left Assign with binary constant (more on net slide) module Reg4(I3,I2,I,I,3,); input I3, I2, I, I; I3 I2 I I module Reg4(I,, ); input [3:] I; I: I[3]I[2]I[]I[] I3 I2 I I reg(4) 3 2 `timescale ns/ ns module Reg4(I,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module vldd_ch3_reg4.v 3 inary constant 4'b 4: size, in number of bits 'b: binary base : binary value Other constant bases possible d: decimal base, o: octal base, h: headecimal base 2'hFA2 'h: headecimal base 2: 3 he digits require 2 bits FA2: he value ize is always in bits, and optional 'hfa2 is OK For decimal constant, size and 'd optional 8'd255 or just 255 In previous uses like A <= ; and are actually decimal numbers. b and b would eplicitly represent bits Underscores may be inserted into value for readability 2'b 8 I3 I2 I I reg(4) 3 2 `timescale ns/ ns module Reg4(I,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module vldd_ch3_reg4.v 4

2 Register ehavior Procedure's event control involves input No the I input. Thus, synchronous "posedge " Event is not just any change on, but specifically change from to (positive edge) negedge also possible Process has synchronous reset Resets output only on rising edge of Process writes output declared as reg variable, thus stores value too I3 I2 I I reg(4) 3 2 `timescale ns/ ns module Reg4(I,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module vldd_ch3_reg4.v 5 Register ehavior Testbench reg/wire declarations and module instantiation similar to previous testbenches Module uses two procedures One generates 2 ns clock for ns, for ns Note: always procedure repeats Other provides values for and I (i.e., vectors) initial procedure eecutes just once, does not repeat `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; Reg4 CompToTest(I_s, _s, _s, _s); // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; module (more on net slide) vldd_ch3_reg4t.v 6 Register ehavior Testbench /nets can be shared between procedures Only one procedure should write to variable Variable can be read by many procedures Clock procedure writes to _s Vector procedures reads _s Event control "@(posedge _s)" May be preped to statement to synchronize eecution with event occurrence tatement may be just ";" as in eample In previous eamples, the statement was a sequential block (begin-) Test vectors thus don't include the clock's period hard coded Care taken to change input values away from clock edges `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; Reg4 CompToTest(I_s, _s, _s, _s); // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; module vldd_ch3_reg4t.v 7 Register ehavior Testbench imulation results Note that _s updated only on rising clock edges Note _s thus unknown until first clock edge _s is reset to on first clock edge _s _s I_s _s time (ns) _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; ) begin if ( == ) <= 4'b; <= I; Initial value of a bit is the unknown value vldd_ch3_reg4t.v Remember that _s is connected to, and I_s to I, in the testbench vldd_ch3_reg4.v 8 2

3 Common Pitfalls Common Pitfalls Using "always" instead of "initial" procedure Causes repeated procedure eecution Not including any delay control or event control in an always procedure May cause infinite loop in the simulator imulator eecutes those statements over and over, never eecuting statements of another procedure imulation time can never advance ymptom imulator appears to just hang, generating no waveforms _s _s I_s _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; _s <= ; I_s <= 4'b; Not initializing all module May cause undefined Or simulator may initialize to default value. witching simulators may cause design to fail. Tip: Immediately initialize all module when first writing procedure _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; _s time (ns) 9 Common Pitfalls Finite-tate Machines (s) equential ehavior Forgetting to eplicitly declare as a wire an identifier used in a port connection e.g., _s Verilog implicitly declares identifier as a net of the default net type, typically a one-bit wire Inted as shortcut to save typing for large circuits May not give warning message during compilation Works fine if a one-bit wire was desired ut may be mismatch in this eample, the wire should have been four bits, not one bit Unepected simulation results Always eplicitly declare wires est to avoid use of Verilog's implicit declaration shortcut `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; Reg4 CompToTest(I_s, _s, _s, _s); Finite-state machine () is a common model of sequential behavior Eample: If =, hold = for 3 clock cycles Note: Transitions implicitly ANDed with rising clock edge Implementation model has two parts: tate register HDL model will reflect those two parts Inputs: ; Outputs: = Off = On ' = On2 tate tate register tatenet = On3 2 3

4 Finite-tate Machines (s) equential ehavior Modules with Multiple and hared Finite-tate Machines (s) equential ehavior Inputs: ; Outputs: = Off = On ' = On2 tate tate register tatenet = On3 `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin case (tate) _Off: begin <= ; if ( == ) tatenet <= _Off; tatenet <= _On; _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _Off; case // tatereg ) begin if ( == ) tate <= _Off; tate <= tatenet; module Modules has two procedures One procedure for combinational One procedure for state register ut it's still a behavioral description tate tate register tatenet `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin // tatereg ) begin module vldd_ch3_lasertimereh.v vldd_ch3_lasertimereh.v 3 4 Finite-tate Machines (s) equential ehavior Parameters Finite-tate Machines (s) equential ehavior parameter declaration Not a variable or net, but rather a constant A constant is a value that must be initialized, and that cannot be changed within the module s definition Four parameters defined _Off, _On, _On2, _On3 Correspond to s states hould be initialized to unique values `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin // tatereg ) begin module Module declares two reg variables tate, tatenet Each is 2-bit vector (need two bits to represent four unique state values to 3) are shared between CombLogic and tatereg procedures CombLogic procedure Event control sensitive to tate and input Will output tatenet and tatereg procedure ensitive to input Will output tate, which it stores tate tate register `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin // tatereg ) begin module tatenet vldd_ch3_lasertimereh.v vldd_ch3_lasertimereh.v 5 6 4

5 Finite-tate Machines (s) equential ehavior with Case tatements Procedure may use case statement Preferred over if--if when just one epression determines which statement to eecute case (epression) Eecute statement whose case item epression value matches case epression case item epression : statement statement is commonly a begin- block, as in eample First case item epression that matches eecutes; remaining case items ignored If no item matches, nothing eecutes Last item may be "default : statement" tatement eecutes if none of the previous items matched ) begin case (tate) _Off: begin <= ; if ( == ) tatenet <= _Off; tatenet <= _On; _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _Off; case Finite-tate Machines (s) equential ehavior with Case tatements s CombLogic procedure Case statement describes states case (tate) Eecutes corresponding statement (often a begin- block) based on tate's current value A state's statements consist of Actions of the state etting of net state (transitions) E: tate is _On Eecutes statements for state On, jumps to case Inputs: ; Outputs: = Off = On ' = On2 reg [:] tate, tatenet; ) begin case (tate) uppose tate is _Off: begin _On <= ; if ( == ) tatenet <= _Off; tatenet <= _On; _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _Off; = case On3 vldd_ch3_lasertimereh.v vldd_ch3_lasertimereh.v 7 8 Finite-tate Machines (s) equential ehavior Finite-tate Machines (s) equential ehavior Modules with Multiple and hared tatereg Procedure imilar to 4-bit register Register for tate is 2-bit vector reg variable Procedure has synchronous reset Resets tate to s initial state, _Off parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; // tatereg ) begin if ( == ) tate <= _Off; tate <= tatenet; Inputs: ; Outputs: = Off = On ' = On2 tate tate register tatenet = On3 `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _Off =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin case (tate) _Off: begin <= ; if ( == ) tatenet <= _Off; tatenet <= _On; _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _Off; case // tatereg ) begin if ( == ) tate <= _Off; tate <= tatenet; module vldd_ch3_lasertimereh.v vldd_ch3_lasertimereh.v 9 2 5

6 Finite-tate Machines (s) equential ehavior elf-checking Testbenches testbench First part of file (variable/net declarations, module instantiations) similar to before Vector Procedure Resets ets 's input values ( test vectors ) Waits for specific clock cycles We observe the resulting waveforms to determine if behaves correctly _s _s _s _s time (ns) // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; _s <= ; #5 _s <= ; #5 _s <= ; #5 _s <= ; module Finite-tate Machines (s) equential ehavior elf-checking Testbenches Reading waveforms is error-prone Create self-checking testbench Use if statements to check for epected values If a check fails, print error message E: if _s fell to one cycle too early, simulation might output: _s _s _s _s 95: Third = failed time (ns) _s <= ; _s <= ; #5 if (_s!= ) $display("%t: Reset failed", $time); _s <= ; #5 _s <= ; #5 _s <= ; if (_s!= ) $display("%t: First = failed", $time); #5 if (_s!= ) $display("%t: econd = failed", $time); #5 if (_s!= ) $display("%t: Third = failed", $time); #5 if (_s!= ) $display("%t: Final = failed", $time); vldd_ch3_lasertimert.v 2 vldd_ch3_lasertimertdisplay.v 22 Finite-tate Machines (s) equential ehavior $display ystem Procedure Common Pitfall: Not Assigning Every Output in Every tate $display built-in Verilog system procedure for printing information to display during simulation A system procedure interacts with the simulator and/or host computer system To write to a display, read a file, get the current simulation time, etc. tarts with $ to distinguish from regular procedures tring argument is printed literally $display("hello") will print "Hello" Automatically adds newline character ecept when special sequences appear %t: Display a time epression Time epression must be net argument $time uilt-in system procedure that returns the current simulation time 95: Third = failed _s <= ; _s <= ; #5 if (_s!= ) $display("%t: Reset failed", $time); _s <= ; #5 _s <= ; #5 _s <= ; if (_s!= ) $display("%t: First = failed", $time); #5 if (_s!= ) $display("%t: econd = failed", $time); #5 if (_s!= ) $display("%t: Third = failed", $time); #5 if (_s!= ) $display("%t: Final = failed", $time); should be combinational function of current state (for Moore ) Not assigning output in given state means previous value is remembered Output has memory ehavior is not an olution e sure to assign every output in every state olution 2 Assign default values before case statement Later assignment in state overwrites default ) begin <= ; case (tate) _Off: begin <= ; if ( == ) Could delete this tatenet <= _Off; without changing behavior (but tatenet <= _On; probably clearer to keep it) _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _Off; case vldd_ch3_lasertimertdisplay.v

7 Common Pitfall: Not Assigning Every Output in Every tate The imulation Cycle `timescale ns/ ns olution 2 Assign default values before case statement Later assignment in state overwrites default Helps clarify which actions are important in which state Corresponds directly to the common simplifying diagram notation of implicitly setting unassigned to case tate : begin A <= ; <= ; C <= ; T: begin A <= ; <= ; C <= ; case A <= ; <= ; C <= ; case tate : begin <= ; T: begin C <= ; case A= = C= T A= = C= T = C= Instructive to consider how an HDL simulator works HDL simulation is comple; we'll introduce simplified form Consider eample ime Three reg variables,, Three procedures P, P2, imulator's job: Determine values for nets and variables over time Repeatedly eecutes and susps procedures Note: Actually considers more objects, known collectively as processes, but we'll keep matters simple here to get just the basic idea of simulation Maintains a simulation time Time module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; module vldd_ch3_ime.v The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns tart of simulation imulation time Time is it variables/nets initialized to the unknown value Eecute each procedure In any order, until stops at a delay or event control Time (ns): tart P P2 <=, then stop. Activate when Time is += ns. No actions, then stop. Activate when changes. No actions, then stop. Activate when changes to We'll use arrow to show where a procedure stops module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; imulation cycle et time to net time at which a procedure activates (note: could be same as current time) In this case, time = ns (P activates) Eecute active procedures (in any order) until stops P P2 Time (ns): tart Activate when Time is ns. <=, stop, activate when Time=+=2 ns. Activate when changes. Activate when changes to. module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; module module vldd_ch3_ime.v vldd_ch3_ime.v

8 The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns imulation cycle et time to net time at which a procedure activates till ns; just changed to ( activates) Eecute active procedures (in any order) until stops P Activate when Time is 2 ns. P2 Activate when changes. Activate when changes to <=, stop, activate when changes to again Time (ns): tart module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; imulation cycle et time to net time at which a procedure activates till ns; just changed (P2 activates) Eecute active procedures until stops P P2 Time (ns): tart Activate when Time is 2 ns. Activate when changes. <= (~), stop, activate when changes. Activate when change on to. module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; module module vldd_ch3_ime.v vldd_ch3_ime.v 29 3 The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns imulation cycle et time to net time at which a procedure activates In this case, set Time = 2 ns (P activates) Eecute active procedures until stops P P2 Time (ns): Init Activate when Time is 2 ns. <=, stop, activate when T=2+=3ns. Activate when changes. Activate when change on to. 2 module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; imulation s when user-specified time is reached Variable/net values translate to waveforms Time (ns): Init Time (ns) module ime(); output reg ; reg, ; // P <= ; #; <= ; #; <= ~; <= ; <= ; module module vldd_ch3_ime.v vldd_ch3_ime.v

9 Variable Updates imulation cycle (revised) Assignment using "<=" ("non blocking assignment") et time to net time at doesn't change variable's value immediately which a procedure resumes Instead, schedules a change of value by placing an Eecute active procedures event on an event queue Update variables with cheduled changes occur at of simulation cycle schedule values Important implications Procedure eecution order in a simulation cycle doesn't matter Assume procedures and 2 are both active Assume is. Proc: <= ~; Proc schedules to be, but does not change the present Proc2: value of. is still. A <= ; Proc2 schedules A to be (the present value of ). A will be, not. At of simulation cycle, is updated to and A to Order of assignments to different variables in a procedure doesn't matter Assume C was. cheduled values will be C= and D=, for either Proc3a or Proc3b. Later assignment in procedure effectively overwrites earlier assignment E will be updated with, but then by ; so E is at the of the simulation cycle. Recall output assignment eample, in which default assignments were added before the case statement. Proc3a: C <= ~C; D <= C; ame Proc4: E <= ; E <= ; Proc3b: D <= C; C <= ~C; 33 9