Verilog Introduc/on Part 2. B39VS Systems project

Transcription

1 Verilog Introduc/on Part 2 B39VS Systems project

2 COMBINATIONAL LOGIC

3 VERILOG: Synthesis - Combina/onal Logic Combina/on logic func/on can be expressed as: logic_output(t) = f(logic_inputs(t)) logic_inputs(t) Combina>onal Logic logic_outputs(t) Rules Avoid technology depent modeling; i.e. implement func/onality, not /ming. The combina/onal logic must not have feedback. Specify the output of a combina/onal behavior for all possible cases of its inputs. Logic that is not combina/onal will be synthesized as sequen/al.

4 Mul/plexer - 4 inputs module Mux4(I3, I2, I1, I0, S1, S0, D); input I3, I2, I1, I0; input S1, S0; output D; reg D; I2, I1, I0, S1, S0) begin if (S1==0 && S0==0) D <= I0; else if (S1==0 && S0==1) D <= I1; else if (S1==1 && S0==0) D <= I2; else D <= I3; module The use of IF statement and else- if Mux4 I0 I1 D I2 I3 S1 S0 1/13/11 4

5 Decoder module Dcd2x4(I1, I0, D3, D2, D1, D0); input I1, I0; output D3, D2, D1, D0; reg D3, D2, D1, D0; I0) begin if (I1==0 && I0==0) begin D3 <= 0; D2 <= 0; D1 <= 0; D0 <= 1; else if (I1==0 && I0==1) begin D3 <= 0; D2 <= 0; D1 <= 1; D0 <= 0; else if (I1==1 && I0==0) begin D3 <= 0; D2 <= 1; D1 <= 0; D0 <= 0; else begin D3 <= 1; D2 <= 0; D1 <= 0; D0 <= 0; module The use of begin- (blocks) I0 I1 D0 1 D 2 3 1/13/11 5

6 Mul/plexer - 2 inputs (behaviour) module Mux2b(I1, I0, S0, D); input I1, I0; input S0; output D; reg D; I0, S0) begin if (S0 == 0) D <= I0; else D <= I1; module I0 I1 S0 D 1/13/11 6

7 Mul/plexer - 2 inputs (structure) module Mux2(I1, I0, S0, D); input I1, I0; input S0; output D; I0 N1 I1 And2_1 N2 Or2_1 D N3 wire N1, N2, N3; Inv Inv_1 (S0, N1,); And2 And2_1 (I0, N1, N2); And2 And2_2 (I1, S0, N3); Or2 Or2_1 (N2, N3, D); module S0 And2_2 Inv_1 Circuit A connec/on of modules Also known as structure A circuit is a second way to describe a module vs. using an always procedure, as earlier Instance An occurrence of a module in a circuit May be mul/ple instances of a module Module Instan-a-ons e.g., Car's modules: /res, engine, windows, etc., with 4 /re instances, 1 engine instance, 6 window instances, etc. 1/13/11 7

8 Built- in Gates and And_1(N1, K, P); not Inv_1(N2, S); and And_2(W, N1, N2); 1/13/11 8

9 APPROACHES TO DESIGN

10 Top- Down Design Combina/onal Behavior to Structure Designer may ini/ally know system behavior, but not structure Top- down design Capture behaviour, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfedered by complexity of crea/ng structure 1/13/11 10

11 Mul/plexer - 2 inputs x4 module Mux2_4b(A3, A2, A1, A0, B3, B2, B1, B0, S0, C3, C2, C1, C0); input A3, A2, A1, A0; input B3, B2, B1, B0; input S0; output C3, C2, C1, C0; Create four Mux2 instances A3 B3 A2 B2 Mux2_4b Mux2 I0 D I1 S0 I0 Mux2 D I1 S0 C3 C2 A3 A2 A1 A0 B3 B2 B1 B0 Mux2_4b S0 C3 C2 C1 C0 Mux2b Mux2_3 (B3, A3, S0, C3); Mux2b Mux2_2 (B2, A2, S0, C2); Mux2b Mux2_1 (B1, A1, S0, C1); Mux2b Mux2_0 (B0, A0, S0, C0); module s0 A1 B1 A0 B0 I0 Mux2 D I1 S0 I0 Mux2 D I1 S0 C1 C0 Hierarchical Circuits 1/13/11 11

12 Add/Subtract vector types module AddSub(A, B, AddSub, clk, S); input [3:0] A, B; input AddSub; output S; reg [4:0] S; input clk; reg [4:0] A5, B5; // B, AddSub) begin clk) begin A5 = {1'b0, A}; B5 = {1'b0, B}; if (AddSub == 0) S <= A5 + B5; else if ( A > B) S <= A - B; else S <= 0; module Concatena/on Collec/on of bits More convenient than declaring separate bits like A3, A2, A1, A0 Vector's bits are numbered Op/ons: [0:3], [1:4], [3:0], etc. Most- significant bit is on leh module AddSub(A3,A2,A1,A0,B3,...); input A3, A2, A1, A0; A3 A2 A1 A0 module AddSub(A, B,...); input [3:0] A, B; A: A[3] A[2] A[1] A[0] 1/13/11 12

13 Parallel- in Parallel- out Storage register module Reg4(D, Q, Clk, Rst); input [3:0] D; output [3:0] Q; reg [3:0] Q; input Clk, Rst; Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= D; D3 D2 D1 D0 reg(4) module Rst Q3 Q2 Q1 Q0 D0 Rst Rst Rst Rst 1/13/11 13

14 Constants Binary constant 4'b0000 4: size, in number of bits 'b: binary base 0000: binary value Other constant bases possible d: decimal base, o: octal base, h: hexadecimal base 12'hFA2 'h: hexadecimal base 12: 3 hex digits require 12 bits FA2: hex value Size is always in bits, and op/onal 'hfa2 is OK For decimal constant, size and 'd op/onal 8'd255 or just 255 In previous uses like A <= 1; 1 and 0 are actually decimal numbers. b1 and b0 would explicitly represent bits Underscores may be inserted into value for readability 12'b1111_1010_0010 8_000_000 1/13/11 14

15 STATE MACHINES

16 Finite State Machine (FSM) When the sequence of ac/ons in your design dep on the state of sequen/al elements, a finite state machine (FSM) can be implemented FSMs are widely used in applica/ons that require prescribed sequen/al ac/vity Example: Sequence Detector Fancy counters Traffic Light Controller Data- path Controller Device Interface Controller etc.

17 Finite State Machine (FSM) (cont.) All state machines have the general feedback structure consis/ng of: Combina/onal logic implements the next state logic Next state (ns) of the machine is formed from the current state (cs) and the current inputs State register holds the value of current state Next State Inputs Next- State Logic Memory Current State

18 Types of State Machines Inputs Next- State Logic ns State Register cs Output Logic Outputs Next state deps on the current state and the inputs but the output deps only on the present state next_state(t) = h(current_state(t), input(t)) output = g(current_state(t))

19 Types of State Machines (cont.) Inputs Next- State Logic ns State Register cs Output Logic Outputs Next state and the outputs dep on the current state and the inputs next_state(t) = h(current_state(t), input(t)) output(t) = g(current_state(t), input(t))

20 Finite State Machine in Verilog A system that helds its output HIGH for three cycles, 0,1,1,1 repeat. The system stays on the LOW state un/l a budon is pressed. Inputs: B; Outputs: X X=0 Off B=0 B =1 X=1 X=1 X=1 On1 On2 On3 1/13/11 20

21 Finite State Machine (behaviour) module fsm(b, X, Clk, Rst); Inputs: B; Outputs: X input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; S_On1: begin X <= 1; StateNext <= S_On2; S_On2: begin X <= 1; StateNext <= S_On3; S_On3: begin X <= 1; StateNext <= S_Off; case // StateReg Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; module B FSM inputs X=0 Off X=1 On1 B Clk B X=1 On2 Combinational logic State State register StateNext X=1 On3 X FSM outputs 1/13/11 21

22 Finite State Machine (structure) module fsmr(b, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 2'b00; Inputs: B; Outputs: X X=0 Off B reg [1:0] State, StateNext; // State encodings: // S_Off 00, S_On1 01, S_On2 10, S_On3 11 B X=1 X=1 X=1 // CombLogic B) begin X <= State[1] State[0]; StateNext[1] <= (~State[1] & State[0]) (State[1] & ~State[0]); StateNext[0] <= (~State[1] & ~State[0] & B) (State[1] & ~State[0]); On1 On2 On3 // StateReg Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; module 1/13/11 22

23 Typical Structure of a FSM module mod_name ( ); input ; output ; parameter size = ; reg [size- 1: 0] current_state; wire [size- 1: 0] next_state; // State defini/ons `define state_0 2'b00 `define state_1 2b01 (current_state or the_inputs) begin // Decode for next_state with case or if statement // Use blocked assignments for all register transfers to ensure // no race condi/ons with synchronous assignments (negedge reset or posedge clk) begin if (reset == 1'b0) current_state <= state_0; else current_state <= next_state; Next State Logic State Register //Output assignments module

24 Sequence Detector FSM Func/onality: Detect two successive 0s or 1s in the serial input bit stream reset reset_state out_bit = FSM Flow- Chart out_bit = 0 read_1_zero 1 read_1_one out_bit = read_2_zero read_2_one 1 out_bit = 1 out_bit = 1

25 Sequence Detector FSM (cont.)

26 Sequence Detector FSM (cont.)