ECE 274 Digital Logic Verilog

Transcription

1 ECE 274 igital Logic Verilog egister ehavior equential circuits have storage egister: most common storage component N-bit register stores N bits tructure may consist of connected flip-flops I3 I2 I I 3 2 (Vahid, Lysecky): Ch. 3 I3 I2 I I 4-bit register Typically just describe register behaviorally eclare output as reg variable to achieve storage Uses vector types Collection of bits More convenient than declaring separate bits like I3, I2, I, I Vector's bits are numbered Options: [:3], [:4], etc. [3:] Most-significant bit is on left Assign with binary constant (more on net slide) module eg4(i3,i2,i,i,3,); input I3, I2, I, I; I3 I2 I I module eg4(i,, ); input [3:] I; I: I[3]I[2]I[]I[] egister ehavior Vectors I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module egister ehavior Constants inary constant 4'b 4: size, in number of bits 'b: binary base : binary value Other constant bases possible d: decimal base, o: octal base, h: headecimal base 2'hFA2 'h: headecimal base 2: 3 he digits require 2 bits FA2: he value ize is always in bits, and optional 'hfa2 is OK For decimal constant, size and 'd optional 8'd255 or just 255 In previous uses like A <= ; and are actually decimal numbers. b and b would eplicitly represent bits Underscores may be inserted into value for readability 2'b 8 I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module 3 4 Procedure's event control involves input Not the I input. Thus, synchronous "posedge " Event is not just any change on, but specifically change from to (positive edge) negedge also possible Process has synchronous reset esets output only on rising edge of Process writes output declared as reg variable, thus stores value too egister ehavior I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module 5 egister ehavior Testbench reg/wire declarations and module instantiation similar to previous testbenches Module uses two procedures One generates 2 ns clock for ns, for ns Note: always procedure repeats Other provides values for and I (i.e., vectors) initial procedure eecutes just once, does not repeat (more on net slide) `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; eg4 CompToTest(I_s, _s, _s, _s); // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; module 6 vldd_ch3_eg4t.v

2 egister ehavior Testbench /nets can be shared between procedures Only one procedure should write to variable Variable can be read by many procedures Clock procedure writes to _s Vector procedures reads _s Event control _s)" May be preped to statement to synchronize eecution with event occurrence tatement may be just ";" as in eample In previous eamples, the statement was a sequential block (begin-) Test vectors thus don't include the clock's period hard coded Care taken to change input values away from clock edges `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; eg4 CompToTest(I_s, _s, _s, _s); // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; module 7 vldd_ch3_eg4t.v egister ehavior Testbench imulation results Note that _s updated only on rising clock edges Note _s thus unknown until first clock edge _s is reset to on first clock edge _s _s I_s _s _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; vldd_ch3_eg4t.v ) begin if ( == ) <= 4'b; emember that _s is connected to, and I_s to I, in the testbench <= I; Initial value of a bit is the 8 unknown value Common Pitfalls Using "always" instead of "initial" procedure Causes repeated procedure eecution Not including any delay control or event control in an always procedure May cause infinite loop in the simulator imulator eecutes those statements over and over, never eecuting statements of another procedure imulation time can never advance _s ymptom imulator appears to just _s hang, generating no waveforms _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; _s <= ; I_s <= 4'b; Common Pitfalls Not initializing all module May cause undefined Or simulator may initialize to default value. witching simulators may cause design to fail. Tip: Immediately initialize all module when first writing procedure _s <= ; I_s <= 4'b; #5 _s <= ; I_s <= 4'b; I_s _s Common Pitfalls Finite-tate Machines (s) equential ehavior Forgetting to eplicitly declare as a wire an identifier used in a port connection e.g., _s Verilog implicitly declares identifier as a net of the default net type, typically a one-bit wire Inted as shortcut to save typing for large circuits May not give warning message during compilation Works fine if a one-bit wire was desired ut may be mismatch in this eample, the wire should have been four bits, not one bit Unepected simulation results Always eplicitly declare wires est to avoid use of Verilog's implicit declaration shortcut `timescale ns/ ns module Testbench(); reg [3:] I_s; reg _s, _s; wire [3:] _s; eg4 CompToTest(I_s, _s, _s, _s); Finite-state machine () is a common model of sequential behavior Eample: If =, hold = for 3 clock cycles Note: Transitions implicitly ANed with rising clock edge Implementation model has two parts: tate register HL model will reflect those two parts Inputs: ; Outputs: = = On ' = On2 tate tate register tatenet = On3 2 2

3 Finite-tate Machines (s) equential ehavior Modules with Multiple and hared Finite-tate Machines (s) equential ehavior Inputs: ; Outputs: = = On ' = On2 tate tate register tatenet = On3 `timescale ns/ ns _On: begin module LaserTimer(,,, ); <= ; tatenet <= _On2; input ; output reg ; _On2: begin input, ; <= ; tatenet <= _On3; parameter _ =, _On =, _On2 = 2, _On3 = 3; _On3: begin <= ; reg [:] tate, tatenet; tatenet <= _; case ) begin case (tate) _: begin <= ; ) begin if ( == ) if ( == ) tatenet <= _; tate <= _; tatenet <= _On; tate <= tatenet; module Modules has two procedures One procedure for combinational One procedure for state register ut it's still a behavioral description tate tate register tatenet `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _ =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin ) begin module Code will be eplained on following slides vldd_ch3_lasertimereh.v 3 vldd_ch3_lasertimereh.v 4 Finite-tate Machines (s) equential ehavior Parameters parameter declaration Not a variable or net, but rather a constant A constant is a value that must be initialized, and that cannot be changed within the module s definition Four parameters defined _, _On, _On2, _On3 Correspond to s states hould be initialized to unique values `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _ =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin ) begin module Finite-tate Machines (s) equential ehavior Module declares two reg variables tate, tatenet Each is 2-bit vector (need two bits to represent four unique state values to 3) are shared between CombLogic and tateeg procedures CombLogic procedure Event control sensitive to tate and input Will output tatenet and tateeg procedure ensitive to input Will output tate, which it stores tate tate register tatenet `timescale ns/ ns module LaserTimer(,,, ); input ; output reg ; input, ; parameter _ =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin ) begin module vldd_ch3_lasertimereh.v 5 vldd_ch3_lasertimereh.v 6 Finite-tate Machines (s) equential ehavior with Case tatements Procedure may use case statement Preferred over if--if when just one epression determines which statement to eecute case (epression) Eecute statement whose case item epression value matches case epression case item epression : statement statement is commonly a begin- block, as in eample First case item epression that matches eecutes; remaining case items ignored If no item matches, nothing eecutes Last item may be "default : statement" tatement eecutes if none of the previous items matched Finite-tate Machines (s) equential ehavior with Case tatements s CombLogic procedure reg [:] tate, tatenet; Case statement describes states ) begin case (tate) case (tate) ) begin _: begin Eecutes corresponding statement case (tate) <= ; (often a begin- block) based on uppose tate is _: begin if ( == ) tate's current value _On <= ; tatenet <= _; A state's statements consist of if ( == ) tatenet <= _; Actions of the state tatenet <= _On; etting of net state (transitions) tatenet <= _On; _On: begin E: tate is _On _On: <= ; begin tatenet <= _On2; Eecutes statements for state On, <= ; jumps to case tatenet <= _On2; _On2: begin <= ; Inputs: ; Outputs: _On2: begin tatenet <= _On3; = <= ; tatenet <= _On3; _On3: begin ' <= ; _On3: begin tatenet <= _; <= ; tatenet <= _; case = = = case On On2 On3 7 vldd_ch3_lasertimereh.v 8 vldd_ch3_lasertimereh.v 3

4 Finite-tate Machines (s) equential ehavior Finite-tate Machines (s) equential ehavior Modules with Multiple and hared tateeg Procedure imilar to 4-bit register egister for tate is 2-bit vector reg variable Procedure has synchronous reset esets tate to s initial state, _ parameter _ =, _On =, _On2 = 2, _On3 = 3; reg [:] tate, tatenet; ) begin if ( == ) tate <= _; tate <= tatenet; Inputs: ; Outputs: = = On ' = On2 tate tate register tatenet `timescale ns/ ns _On: begin module LaserTimer(,,, ); <= ; tatenet <= _On2; input ; output reg ; _On2: begin input, ; <= ; tatenet <= _On3; parameter _ =, _On =, _On2 = 2, _On3 = 3; _On3: begin <= ; reg [:] tate, tatenet; tatenet <= _; case ) begin case (tate) _: begin <= ; ) begin if ( == ) if ( == ) tatenet <= _; tate <= _; tatenet <= _On; tate <= tatenet; module Code should 9 now be clear vldd_ch3_lasertimereh.v vldd_ch3_lasertimereh.v 2 = On3 Finite-tate Machines (s) equential ehavior elf-checking Testbenches testbench First part of file (variable/net declarations, module instantiations) similar to before Vector Procedure esets ets 's input values ( test vectors ) Waits for specific clock cycles We observe the resulting waveforms to determine if behaves correctly _s _s _s _s // Clock Procedure _s <= ; #; _s <= ; #; // Note: Procedure repeats _s <= ; _s <= ; #5 _s <= ; #5 _s <= ; #5 _s <= ; module vldd_ch3_lasertimert.v 2 _s _s _s _s Finite-tate Machines (s) equential ehavior elf-checking Testbenches eading waveforms is error-prone Create self-checking testbench Use if statements to check for epected values If a check fails, print error message E: if _s fell to one cycle too early, simulation might output: 95: Third = failed _s <= ; _s <= ; #5 if (_s!= ) $display("%t: eset failed", $time); _s <= ; #5 _s <= ; #5 _s <= ; if (_s!= ) $display("%t: First = failed", $time); #5 if (_s!= ) $display("%t: econd = failed", $time); #5 if (_s!= ) $display("%t: Third = failed", $time); #5 if (_s!= ) $display("%t: Final = failed", $time); vldd_ch3_lasertimertisplay.v 22 Finite-tate Machines (s) equential ehavior $display ystem Procedure $display built-in Verilog system procedure for printing information to _s <= ; display during simulation _s <= ; A system procedure interacts with the simulator and/or host computer system #5 if (_s!= ) $display("%t: eset failed", $time); To write to a display, read a file, get the _s <= ; current simulation time, etc. tarts with $ to distinguish from regular #5 _s <= ; procedures tring argument is printed literally #5 _s <= ; if (_s!= ) $display("hello") will print "Hello" $display("%t: First = failed", $time); Automatically adds newline character ecept when special sequences appear #5 if (_s!= ) %t: isplay a time epression Time epression must be net argument $time uilt-in system procedure that returns the current simulation time 95: Third = failed $display("%t: econd = failed", $time); #5 if (_s!= ) $display("%t: Third = failed", $time); #5 if (_s!= ) $display("%t: Final = failed", $time); vldd_ch3_lasertimertisplay.v 23 Top-own esign s to Controller tructure ecall from Chapter 2 Top-down design Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfettered by compleity of creating structure Capture behavior: Capture structure: Controller Create architecture (state register and combinational ) Encode states Create stable table (describes combinational ) Implement combinational Capture behavior Capture structure imulate imulate N N tate register K_s P_s _s W_s K_s P_s _s W_s hould be the same Inputs: ; Outputs: LaserTimer eample = ' = = = On On2 On3 24 4

5 Top-own esign s to Controller tructure ecall from Chapter 2 Top-down design Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfettered by compleity of creating structure Capture behavior: Capture structure: Controller Create architecture (state register and combinational ) Encode states Create stable table (describes combinational ) Implement combinational Inputs: ; Outputs: = clk ' = = = On On2 On3 b s s tate register n n 25 Common Pitfall: Not Assigning Every Output in Every tate should be combinational function of current state (for Moore ) Not assigning output in given state means previous value is remembered Output has memory ehavior is not an olution e sure to assign every output in every state olution 2 Assign default values before case statement Later assignment in state overwrites default ) begin <= ; case (tate) _: begin <= ; if ( == ) Could delete this tatenet <= _; without changing behavior (but tatenet <= _On; probably clearer to keep it) _On: begin <= ; tatenet <= _On2; _On2: begin <= ; tatenet <= _On3; _On3: begin <= ; tatenet <= _; case 26 Common Pitfall: Not Assigning Every Output in Every tate olution 2 Assign default values before case statement Later assignment in state overwrites default Helps clarify which actions are important in which state Corresponds directly to the common simplifying diagram notation of implicitly setting unassigned to case tate : begin A <= ; <= ; C <= ; T: begin A <= ; <= ; C <= ; case A <= ; <= ; C <= ; case tate : begin <= ; T: begin C <= ; case A= = C= T A= = C= T = C= The imulation Cycle Instructive to consider how an HL simulator works HL simulation is comple; we'll introduce simplified form Consider eample ime Three reg variables,, Three procedures P,, imulator's job: etermine values for nets and variables over time epeatedly eecutes and susps procedures Note: Actually considers more objects, known collectively as processes, but we'll keep matters simple here to get just the basic idea of simulation Maintains a simulation time Time `timescale ns/ ns module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; module 27 vldd_ch3_ime.v 28 The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns tart of simulation imulation time Time is it variables/nets initialized to the unknown value Eecute each procedure In any order, until stops at a delay or event control We'll use arrow to show where a Time (ns): tart P <=, then stop. Activate when Time is += ns. No actions, then stop. Activate when changes. No actions, then stop. Activate when changes to procedure stops module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; imulation cycle et time to net time at which a procedure activates (note: could be same as current time) In this case, time = ns (P activates) Eecute active procedures (in any order) until stops P Time (ns): tart Activate when Time is ns. <=, stop, activate when Time=+=2 ns. Activate when changes. Activate when changes to. module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; module vldd_ch3_ime.v 29 module vldd_ch3_ime.v 3 5

6 The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns imulation cycle et time to net time at which a procedure activates till ns; just changed to ( activates) Eecute active procedures (in any order) until stops P Time (ns): tart Activate when Time is 2 ns. Activate when changes. Activate when changes to <=, stop, activate when changes to again module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; imulation cycle et time to net time at which a procedure activates till ns; just changed ( activates) Eecute active procedures until stops P Time (ns): tart Activate when Time is 2 ns. Activate when changes. <= (~), stop, activate when changes. Activate when change on to. module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; module vldd_ch3_ime.v 3 module vldd_ch3_ime.v 32 The imulation Cycle `timescale ns/ ns The imulation Cycle `timescale ns/ ns imulation cycle et time to net time at which a procedure activates In this case, set Time = 2 ns (P activates) Eecute active procedures until stops P Time (ns): Init Activate when Time is 2 ns. <=, stop, activate when T=2+=3ns. Activate when changes. Activate when change on to. 2 module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; imulation s when user-specified time is reached Variable/net values translate to waveforms Time (ns): Init Time (ns) module ime(); output reg ; reg, ; // P <= ; #; <= ; #; begin <= (posedge ); <= (posedge ); <= ; module vldd_ch3_ime.v 33 module vldd_ch3_ime.v 34 Variable Updates Assignment using "<=" ("non blocking assignment") imulation cycle (revised) doesn't change variable's value immediately et time to net time at which a procedure resumes Instead, schedules a change of value by placing an event on an event queue Eecute active procedures cheduled changes occur at of simulation cycle Update variables with schedule values Important implications Procedure eecution order in a simulation cycle doesn't Assume is. matter Proc: Assume procedures and 2 are both active <= ~; Proc schedules to be, but does not change the present value of. is still. Proc2: Proc2 schedules A to be A <= (the present value of ). ; At of simulation cycle, is updated to and A to A will be, not. Order of assignments to different variables in a procedure doesn't matter Proc3a: ame Proc3b: Assume C was. cheduled values will be C= and =, C <= ~C; <= C; for either Proc3a or Proc3b. <= C; C <= ~C; Later assignment in procedure effectively overwrites earlier assignment E will be updated with, but then by ; so E is at the Proc4: E <= ; of the simulation cycle. E <= ; ecall output assignment eample, 35 in which default assignments were added before the case statement. eset ehavior of a register when a reset input is asserted Good practice dictates having defined reset behavior for every register eset behavior should always have priority over normal register behavior eset behavior Usually clears register to s May initialize to other value e.g., state register of a controller may be initialized to encoding of initial state of eset usually asserted eternally at start of sequential circuit operation, but also to restart due to failure, user request, or other reason esets I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module 36 6

7 Previous eamples used synchronous resets input only considered during rising clock I = has no effect until rising clock ynchronous eset I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; ) begin if ( == ) <= 4'b; <= I; module Can also use asynchronous reset input considered indepently from clock Add "posedge " to sensitivity list I Asynchronous reset = has almost immediate effect I ynchronous reset = has no effect until net rising clock Asynchronous eset I3 I2 I I 3 2 `timescale ns/ ns module eg4(i,,, ); input [3:] I; output [3:] ; reg [3:] ; input, ; posedge ) begin if ( == ) <= 4'b; <= I; module 37 vldd_ch3_eg4asy.v 38 Asynchronous eset Could have used asynchronous reset for state register too ) begin if ( == ) tate <= _; ynchronous tate <= tatenet; posedge ) begin if ( == ) tate <= _; Asynchronous tate <= tatenet; vldd_ch3_lasertimerehasy.v ynchronous versus Asynchronous esets Which is better synchronous or asynchronous reset? Hotly debated in design community Each has pros and cons e.g., asynchronous can still reset even if clock is not functioning, synchronous avoids timing analysis problems sometimes accompanying asynchronous designs We won t try to settle the debate here What s important is to be consistent throughout a design All registers should have defined reset behavior that takes priority over normal register behavior That behavior should all be synchronous reset or all be asynchronous reset We will use synchronous resets in all of our remaining eamples