Data/Thread Level Speculation (TLS) in the Stanford Hydra Chip Multiprocessor (CMP)

Size: px

Start display at page:

Download "Data/Thread Level Speculation (TLS) in the Stanford Hydra Chip Multiprocessor (CMP)"

Valerie Woods
6 years ago
Views:

1 Data/Thread Level Speculation (TLS) in the Stanford Hydra Chip Multiprocessor (CMP) A 4-core Chip Multiprocessor (CMP) based microarchitecture/compiler effort at Stanford that provides hardware/software support for Data/Thread Level Speculation (TLS) to extract parallel speculated threads from sequential code (single thread) augmented with software thread speculation handlers (Primary papers: 4, 6) #1 lec # 10 Fall

2 Motivation for Chip Multiprocessors (CMPs) A CMP offers implementation benefits High-speed signals are localized in individual CPUs A proven CPU design is replicated across the die (including SMT processors, e.g IBM Power 5) Overcomes diminishing performance/transistor return problem in uniprocessors (similar motivation for SMT) Transistors are used today mostly for ILP extraction MPs use transistors to run multiple threads (exploit thread level parallelism, TLP): On parallelized programs With multiprogrammed workloads A number of single-threaded applications executing of different CPUs Fast inter-processor communication eases parallelization of code (Using shared L2 cache) Potential Drawback of CMPs: High power/heat issues using current VLSI processes. #2 lec # 10 Fall

Stanford Hydra CMP Approach Goals Exploit all levels of program parallelism. Develop a single-chip multiprocessor architecture that simplifies microprocessor design and achieves high performance.

3 Stanford Hydra CMP Approach Goals Exploit all levels of program parallelism. Develop a single-chip multiprocessor architecture that simplifies microprocessor design and achieves high performance. Make the multiprocessor transparent to the average user. Integrate use of parallelizing compiler technology in the design of microarchitecture that supports data/thread level speculation (TLS). On multiple CPU cores within a single CMP or multiple CMPs On multiple CPU cores within a single CMP using Thread Level Speculation (TLS) Within a single CPU core #3 lec # 10 Fall

4 Hydra Prototype Overview 4 CPU cores with modified private L1 caches. Speculative coprocessor (for each processor core) Speculative memory reference controller Speculative interrupt screening mechanism Statistics mechanisms for performance evaluation and to allow feedback for code tuning Memory system Read and write buses Controllers for all resources On-chip shared L2 cache L2 Speculation write buffers. Simple off-chip main memory controller I/O and debugging interface #4 lec # 10 Fall

5 The Basic Hydra CMP 4 processors and secondary cache on a chip 2 buses connect processors and memory Coherence: writes are broadcast on write bus #5 lec # 10 Fall

6 Hydra Memory Hierarchy Characteristics #6 lec # 10 Fall

7 Hydra Prototype Layout Shared L2 L2 Speculation Write Buffers 250 MHz clock rate target #7 lec # 10 Fall

CMP Parallel Performance Varying levels of performance Multiprogrammed workloads work well Very parallel apps (matrix-based FP and multimedia) are excellent Acceptable only

8 CMP Parallel Performance Varying levels of performance Multiprogrammed workloads work well Very parallel apps (matrix-based FP and multimedia) are excellent Acceptable only with a few less parallel (i.e. integer) applications Thread Level Speculation (TLS) Target Applications Without Thread Level Speculation (TLS) #8 lec # 10 Fall

9 The Parallelization Problem Current automated parallelization software (parallel compilers) is limited Parallel compilers are generally successful for scientific applications with statically known dependencies (e.g dense matrix computations). Automated parallization of general-purpose applications provides poor parallel performance especially for integer applications due to ambiguous dependencies resulting from: Significant pointer use: Pointer aliasing (Pointer disambiguation problem) Dynamic loop limits Complex control flow Irregular array accesses Inter-procedural dependencies Ambiguous dependencies limit extracted parallelism/performance: Complicate static dependency analysis Introduce imprecision into dependence relations Force conservative performance-degrading synchronization to safely handle potential dependencies. Parallelism may exist in algorithm, but code hides it. Manual parallelization can provide good performance on a much wider range of applications: Requires different initial program design/data structures/algorithms Programmers with additional skills. Handling ambiguous dependencies present in general-purpose applications may still force conservative synchronization greatly limiting parallel performance Can hardware help the situation? #9 lec # 10 Fall

10 Possible Limited Parallel Software Solution: Data Speculation & Thread Level Speculation (TLS) Data speculation and Thread Level Speculation (TLS) enable parallelization without regard for data dependencies Normal sequential program is broken up into speculative threads Speculative threads are now run in parallel on multiple physical CPUs (e.g. CMP) and/or logical CPUs (e.g. SMT). Speculation hardware (TLS processor) architecture ensures correctness Parallel software implications Loop parallelization is now easily automated Ambiguous dependencies resolved dynamically without conservative synchronization More arbitrary threads are possible (subroutines) Add synchronization only for performance Thread Level Speculation (TLS) hardware support mechanisms Speculative thread control mechanism Five basic speculation hardware/memory system requirements for correct data/thread speculation #10 lec # 10 Fall

11 Subroutine Thread Speculation Speculated Thread #11 lec # 10 Fall

Speculation (TLS) Speculated Threads Original Sequential

12 Loop Iteration Speculative Threads A Simple example of a speculatively executed loop using Data/Thread Level Speculation (TLS) Speculated Threads Original Sequential (Single Thread) Loop Most common Application of TLS #12 lec # 10 Fall

13 Overview of Loop-Iteration Thread Speculation Parallel regions (loop iterations) are annotated by the compiler. e.g. Begin_Speculation End_Speculation The hardware uses these annotations to run loop iterations in parallel as speculated threads on a number of CPUs. Each CPU knows which loop iteration it is running CPUs dynamically prevent data/name dependency violations later iterations can t use data before write by earlier iterations (RAW) earlier iterations never see writes by later iterations (WAW, WAR hazards prevented): Multiple views of memory are created by TLS hardware If a later iteration has used data that an earlier iteration writes (RAW hazard), it is restarted All following iterations are halted and restarted, also All writes by the later iteration are discarded (undo speculated work). #13 lec # 10 Fall

14 Hydra s Data & Thread Speculation Operations #14 lec # 10 Fall

15 Hydra Loop Compiling for Speculation Speculated Threads #15 lec # 10 Fall

16 Loop Execution with Thread Speculation Data Dependency Violation (RAW hazard) #16 lec # 10 Fall

17 Speculative Thread Creation in Hydra Register Passing Buffer (RPB) #17 lec # 10 Fall

18 Speculative Data Access in Speculated Threads i Less Speculated thread i+1 More speculated thread i WAR i+1 RAW WAW Write by i+1 Not seen by i #18 lec # 10 Fall

19 Speculative Data Access in Speculated Threads To provide the desired memory behavior, the data/thread speculation hardware must provide: 1. A method for detecting true memory dependencies, in order to determine when a dependency has been violated (RAW hazard). 2. A method for backing up and re-executing speculative loads and any instructions that may be dependent upon them when the load causes a violation. 3. A method for buffering any data written during a speculative region of a program so that it may be discarded when a violation occurs or permanently committed at the right time. #19 lec # 10 Fall

20 Five Basic Speculation Hardware Requirements For Correct Data/Thread Speculation 1. Forward data between parallel threads (RAW). A speculative system must be able to forward shared data quickly and efficiently from an earlier thread running on one processor to a later thread running on another. 2. Detect when reads occur too early (RAW hazards). If a data value is read by a later thread and subsequently written by an earlier thread, the hardware must notice that the read retrieved incorrect data since a true dependence violation has occurred. 3. Safely discard speculative state after violations. All speculative changes to the machine state must be discarded after a violation, while no permanent machine state may be lost in the process. 4. Retire speculative writes in the correct order (WAW hazards). Once speculative threads have completed successfully, their state must be added to the permanent state of the machine in the correct program order, considering the original sequencing of the threads. 5. Provide memory renaming (WAR hazards). The speculative hardware must ensure that the older thread cannot see any changes made by later threads, as these would not have occurred yet in the original sequential program. (i.g. Multiple views of memory) #20 lec # 10 Fall

Speculative Hardware/Memory Requirements 1-2 2 1 More Speculated

21 Speculative Hardware/Memory Requirements More Speculated Thread (RAW) (RAW hazard or violation) #21 lec # 10 Fall

22 Speculative Hardware/Memory Requirements 3-4 More Speculated Thread Restart 3 4 (RAW hazard). (prevent WAW hazards) #22 lec # 10 Fall

Speculative Hardware/Memory Requirement 5 Less speculated Thread i More Speculated Thread i + 1 Even more Speculated Thread i + 2 Not visible to less speculated thread

23 Speculative Hardware/Memory Requirement 5 Less speculated Thread i More Speculated Thread i + 1 Even more Speculated Thread i + 2 Not visible to less speculated thread i 5 Write X by i+1 not visible to less speculated threads (thread i here) (i.e. no WAR hazard) Memory Renaming to prevent WAR hazards. #23 lec # 10 Fall

24 Hydra Thread Level Speculation (TLS) Hardware #24 lec # 10 Fall

25 Hydra Thread Level Speculation (TLS) Support #25 lec # 10 Fall

26 L1 Cache Tag Details - Record writes of more speculated threads #26 lec # 10 Fall

27 L2 Speculation Buffer Details #27 lec # 10 Fall

28 The Operation of Speculative Loads Less Speculative More Speculative Check Last Do Not Check: More Speculated Later writes not visible (otherwise WAR) Check First #28 lec # 10 Fall

29 Reading L2 Cache Speculative Buffers Similar to last slide #29 lec # 10 Fall

30 Less Speculated More Speculated The Operation of Speculative Stores RAW Detection Similar to invalidate cache coherency protocols #30 lec # 10 Fall

31 Hydra s Handling of Five Basic Speculation Hardware Requirements For Correct Data/Thread Speculation 1. Forward data between parallel threads (RAW). Speculative Load When a speculative thread writes data over the write bus, all more-speculative threads that may need the data have their current copy of that cache line invalidated. This is similar to the way the system works during nonspeculative operation (invalidate cache coherency protocol). If any of the threads subsequently need the new speculative data forwarded to them, they will miss in their primary cache and access the secondary cache. The speculative data contained in the write buffers of the current or older threads replaces data returned from the secondary cache on a byte-by-byte basis just before the composite line is returned to the processor and primary cache. #31 lec # 10 Fall

32 Hydra s Handling of Five Basic Speculation Hardware Requirements For Correct Data/Thread Speculation 2. Detect when reads occur too early (RAW hazards). Primary cache bits are set to mark any reads that may cause violations. Subsequently, if a write to that address from an earlier thread (less speculated) invalidates the address, a violation is detected, and the thread is restarted. 3. Safely discard speculative state after violations. Since all permanent machine state in Hydra is always maintained within the secondary cache, anything in the primary caches and secondary cache speculation buffers may be invalidated at any time without risking a loss of permanent state. As a result, any lines in the primary cache containing speculative data (marked with a special modified bit) may simply be invalidated all at once to clear any speculative state from a primary cache. In parallel with this operation, the secondary cache buffer for the thread may be emptied to discard any speculative data written by the thread. #32 lec # 10 Fall

33 Hydra s Handling of Five Basic Speculation Hardware Requirements For Correct Data/Thread Speculation 4. Retire speculative writes in the correct order (WAW hazards). Separate secondary cache speculation buffers are maintained for each thread. As long as these are drained into the secondary cache in the original program sequence of the threads, they will reorder speculative memory references correctly. 5. Provide memory renaming (WAR hazards). Each processor can only read data written by itself or earlier threads (less speculated threads) when reading its own primary cache or the secondary cache speculation buffers. Writes from later threads don t cause immediate invalidations in the primary cache, since these writes should not be visible to earlier (less speculative) threads. However, these ignored invalidations are recorded using an additional preinvalidate primary cache bit associated with each line. This is because they must be processed before a different speculative or non-speculative thread executes on this processor. If future threads have written to a particular line in the primary cache, the preinvalidate bit for that line is set. When the current thread completes, these bits allow the processor to quickly simulate the effect of all stored invalidations caused by all writes from later processors all at once, before a new thread begins execution on this processor. More speculative writes not visible #33 lec # 10 Fall

34 Thread Speculation Performance Results representative of entire uniprocessor applications Simulated with accurate modeling of Hydra s memory and hardware speculation support. #34 lec # 10 Fall

35 Hydra Conclusions Hydra offers a number of advantages Good performance on parallel applications Promising performance on difficult to parallelize sequential (single-threaded) applications using data/thread Level Speculation (TLS) mechanisms. Scalable, modular design Low hardware overhead support for speculative thread parallelism, yet greatly increases the number of parallel applications. #35 lec # 10 Fall

36 Other Thread Level Speculation (TLS) Efforts: Wisconsin Multiscalar (1995) This CMP-based design proposed the first reasonable hardware to implement TLS. Unlike Hydra, Multiscalar implements a ring-like network between all of the processors to allow direct register-to-register communication. Along with hardware-based thread sequencing, this type of communication allows much smaller threads to be exploited at the expense of more complex processor cores. The designers proposed two different speculative memory systems to support the Multiscalar core. The first was a unified primary cache, or address resolution buffer (ARB). Unfortunately, the ARB has most of the complexity of Hydra s secondary cache buffers at the primary cache level, making it difficult to implement. Later, they proposed the speculative versioning cache (SVC). The SVC uses write-back primary caches to buffer speculative writes in the primary caches, using a sophisticated coherence scheme. #36 lec # 10 Fall

37 Other Thread Level Speculation (TLS) Efforts: Carnegie-Mellon Stampede This CMP-with-TLS proposal is very similar to Hydra, Including the use of software speculation handlers. However, the hardware is simpler than Hydra s. The design uses write-back primary caches to buffer writes similar to those in the SVC and sophisticated compiler technology to explicitly mark all memory references that require forwarding to another speculative thread. Their simplified SVC must drain its speculative contents as each thread completes, unfortunately resulting in heavy bursts of bus activity. #37 lec # 10 Fall

38 Other Thread Level Speculation (TLS) Efforts: MIT M-machine This CMP design has three processors that share a primary cache and can communicate register-to-register through a crossbar. Each processor can also switch dynamically among several threads. (TLS & SMT??) As a result, the hardware connecting processors together is quite complex and slow. However, programs executed on the M-machine can be parallelized using very fine-grain mechanisms that are impossible on an architecture that shares outside of the processor cores, like Hydra. Performance results show that on typical applications extremely fine-grained parallelization is often not as effective as parallelism at the levels that Hydra can exploit. The overhead incurred by frequent synchronizations reduces the effectiveness. #38 lec # 10 Fall

Data/Thread Level Speculation (TLS) in the Stanford Hydra Chip Multiprocessor (CMP)

Data/Thread Level Speculation (TLS) in the Stanford Hydra Chip Multiprocessor (CMP) Hydra ia a 4-core Chip Multiprocessor (CMP) based microarchitecture/compiler effort at Stanford that provides hardware/software