Spring 2012 Prof. Hyesoon Kim
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1 Spring 2012 Prof. Hyesoon Kim
2 Descending (address grows download) Ascending (Address grows upward) Full/Empty: the stack pointer can be r10 either point to the last item (a full stack) or the next free space (an empty stack) IA r4 r1 r0 IB DA DB r4 r1 r0 r4 r1 r0 r4 r1 r0 Increasing Address Stack Type Push Pop Full descending STMFD /STMDB LDMFD /LDMIA Full Ascending STMFA / STMIB LDMFA /LDMDA Empty Descending STMED /STMDA LDMED /LDMIB Empty Ascending STMEA /STMIA LDMEA /LDMDB
3 R15: PC PC may be used as a source operand Register-based shift cannot use R15 as source operands. Running-ahead PC s behavior PC is always running ahead PC is always pointing +8 of the current instruction Imagine 3-stage pipeline machine. PC is pointing what to fetch when an instruction is in the WB stage in the 3-stage pipeline machine When R15 is a source, the current PC + 8 is supplied to the source operand. When R15 is a destination S: 1: SPSRà CPSR, affecting interrupt, resource PC and CPSR automatically,
4 Pre-fetch abort : instruction fetch Fetch Decode Execute PC+4 PC+8 Data abort : memory execution Fetch Decode Execute
5 void event_enableirq (void)! {! asm {! }!!!MRS r1, CPSR!!!BIC r1, r1, #0x80!!!MSR CPSR_c, r1!!}! // Enable Bit 7 (set register 0)! void event_disableirq (void) { asm { MRS r1, CPSR ORR r1, r1, #0x80 MSR CPSR_c, r1 } } // Disable bit 7 (set 1) N Z C V unused IF T mode Bit 7: interrupt Bit 6: Fast interrupt
6 SUB lr, lr, #4 STMFD sp!{reglist, lr} ;. LDMFD sp!, {reglist,pc}^
7 Soc for embedded system. Single chip DSP Embedded applications running an RTOS Mass storage - HDD & DVD Speech coders Automotive control Cruise control, ABS, etc. Hands-free interfaces Modems and soft-modems Audio decoding Dolby AC3 digital MPEG MP3 audio Speech recognition and synthesis.
8 Data processing instructions Load and store instructions Branch instructions Coprocessor instructions Coprocessor data processing Coprocessor register transfer Coprocessor data transfer
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10 Improve Memory Accesses Non-blocking (hit-under-miss) operations LD/ST and ALU are decoupled. Out-of-order completion: Instructions that have no dependency on the outcome of the previous instruction can complete.!!! à Good or Bad? The ARM11 Microarchitecture, David Cormie, ARM Ltd
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12 Thumb-2 is a superset of the Thumb instruction set. Thumb-2 introduces 32-bit instructions that are intermixed with the 16-bit instructions. The Thumb-2 instruction set covers almost all the functionality of the ARM instruction set. Thumb-2 is backwards compatible with the ARMv6 Thumb instruction set.
13 Neon: ARM s SIMD engine 128bit SIMD NEON instructions perform "Packed SIMD" processing: Registers are considered as vectors of elements of the same data type Data types can be: signed/unsigned 8-bit, 16-bit, 32-bit, 64-bit, single precision floating point Instructions perform the same operation in all lanes
14 Watch any video in any format Edit and enhance captured videos - video stabilization Anti-aliased rendering and compositing Game processing Process multi-megapixel photos quickly Voice recognition Powerful multichannel hi-fi audio processing
15
16 ARM Core/CPU DMA controller AHB or ASB On-chip RAM bridge Test i/f ctrl External bus interface UART APB timer Single clock edge protocol Parallel i/f
17 AHB (Advanced High-performance Bus) New standard Connect high-performance system Burst mode data transfer and split transactions Pipelined ASB (Advanced System Bus) Old standard Connect high-performance system Pipelined Multiple systems APB (Advanced Peripheral Bus) A simpler interface for low-performance peripherals Low power Latched address, simple interface
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19 Arbiter Bus grant Master 1 Addr data Slave 1 Read data Master 2 Slave 2 Master 3 Slave 3 Decoder
20 A bus transaction is initiated by a bus master which requests access from a central arbiter. The arbiter decides priorities when there are conflicting requests. The design of the arbiter is a system specific issue. The ASB only specifies the protocol: The master issues a request to the arbiter When the bus is available, the arbiter issues a grant to the master. wuzwuz.nuigalway.ie/.../soc_lecture_02_ucg%20november%2012% ppt
21 A memory access consists of several cycles (including arbitration) Since the bus is not used in all cycles, pipelining can be used to increase performance
22 A transaction is splitted into a two transactions Request-transaction Reply-transaction Both transactions have to compete for the bus by arbitration Variable request sizes
23 Overheads can be reduced if the requests are sent as a burst Overheads Arbitration, Addressing, Acknowledgement Better efficiency, but be careful with long requests
24 Bus bridges are used to separate highperformance devices from low-performance devices All communication from high-performance bus with the low performance device goes via the bridge
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COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor 4.1 Introduction Introduction CPU performance factors Instruction count Determined by ISA and compiler