Some Common Terms. Introduction To ASIC/IC/SoC Design. ASIC: Advantages. ASIC: Disadvantages. Definition. Verilog HDL Introduction

Transcription

1 Verilog HDL Introduction CE 411 Digital System Design Dr. Arshad Aziz Some Common Terms Some commonly used terms HDL: Hardware Description Language (Verilog, VHDL etc) Netlist: HDL representation of a circuit in the form of gates (NAND, NOR etc) RTL: HDL representation of a circuit in the form of functions, procedures etc Layout: A drawing of the physical circuits contains different layers for mask production Cell: Basic building blocks of an ASIC a simple logic gate (NAND, NOR etc) or more complex functions (RAM, adder etc) Die: a piece of silicon on which an IC is fabricated Wafer: A large round piece of silicon on which several dies are made 1 4 Introduction To ASIC/IC/SoC Design Definition Integrated Circuits ASIC Design Flow Overview of ASIC Fabrication Process ASIC Packages ASIC: Advantages ASICs offer several benefits over general purpose Integrated Circuits Maybe the only way to implement a given design May include unique features that add value and differentiation from competing products May replace a large number of standard IC s and offer power, die size or board space savings Performance Frequency and speed of operation 2 5 Definition ASIC: Application Specific Integrated Circuit An IC designed for a specific application to perform a dedicated task e.g. an ASIC to do table lookups for routers e.g. an ASIC to process real-time data stream encryption as opposed to a general purpose IC e.g. general purpose micro-processors (intel x86) e.g. RAM e.g. ROM ASIC: Disadvantages ASICs have some disadvantages as well... Cost of Design and Development Design to silicon cycle is very long. Typically 6- to 8- weeks. Design changes not easy. Testing and debug difficult

2 Overview of ASIC Design Flow Types of ICs: Cell-based Document RTL (Verilog, VHDL) Structural (Verilog netlist) Functional Specification Logic Design Logic Implementation Cell-based Layout uses predefined circuit elements called cells Available in cell libraries Interconnects between cells are made as specified by the netlist Process is known as routing Permit integration of macros or 3 rd party cores Microprocessors and peripheral controllers, RAM, ROM, Mixed digital/analog functions and complex datapath elements Layout DB Physical Design Silicon Fabrication 7 10 Types of Digital Integrated Circuits What is an FPGA? Full-Custom ASICs Integrated Circuits Semi-Custom/ Cell Based ASICs User Programmable Bloc ck RAMs Bloc ck RAMs Configurable Logic Blocks I/O Blocks PLD FPGA Block RAMs PAL PLA PML LUT (Look-Up Table) MUX Gates Types of ICs: Full Custom Full Custom Circuit elements of the design are individually drawn and positioned in the layout. Transistors, resistors, capacitors and element interconnects Requires high skill and is process specific! Types of ICs (contd.) FPGA: Field Programmable Gate Array Array of logic blocks embedded in a matrix of programmable interconnect lines Each logic block consists of flip-flopsflops and combinational logic that can be configured via user programming

3 Two competing implementation approaches Overview of ASIC Design Flow (contd.) ASIC Application Specific Integrated Circuit designed all the way from behavioral description to physical layout designs must be sent for expensive and time consuming fabrication in semiconductor foundry FPGA Field Programmable Gate Array no physical layout design; design s with a bitstream used to configure a device bought off the shelf and reconfigured by designers themselves Functional Specification: Document describing the features, behavior of design Algorithmic description flow charts, block diagrams, C/C++, SPW(Cadence Signal Processing Worksystem), Matlab Emphasis on design of functions, algorithms and interfaces Underlying hardware implementation not fixed at this stage 16 ASICs High performance Low power Low cost (but only in high volumes) FPGAs vs. ASICs FPGAs Off-the-shelf Low development costs Short time to the market Reconfigurability Overview of ASIC Design Flow (contd.) Logic Design RTL (Register Transfer Level) description Hardware description language Verilog, VHDL Focus on actual implementation (data flow) of the design using logic elements (busses, registers, FSM, data paths, RAM s) module full_adder(sum, CARRY, A, B, C); input A, B, C; output SUM, CARRY; assign CARRY = A & B A & C B & C; assign SUM = A ^ B ^ C; 17 Overview of ASIC Design Flow Document RTL (Verilog, VHDL) Structural (Verilog netlist) Functional Specification Logic Design Logic Implementation Overview of ASIC Design Flow (contd.) Logic Implementation: RTL description is synthesized using automatic synthesis tools E.g. Synopsys Design Compiler The result is a gate-level netlist SUM = A B C CARRY = AB + AC + BC A B C SUM Layout DB Silicon Physical Design Fabrication 15 A B A C B C 18 3

4 Overview of ASIC Design Flow (contd.) Physical Design The gate-level netlist is used to layout the ASIC An automatic P&R tool is used (Avanti, Cadence etc) The tool reads the netlist Places the cells Routes the interconnects As described by the netlist Outputs a layout map of the entire chip ASIC Packages Several types of packages for various applications Dual-inline (DIP): Cheap, old technology, obsolete Poor electric characteristics, low (pin) density PLCC: (Plastic Leaded Chip Carrier) Cheap, better density than DIP, obsolete QFP: (Quad Flat Package) Cheap, high density moderate thermal/electrical characteristics ASIC Fabrication Process Tools read in the layout map of the chip Circuits to be formed on the ASIC are drawn on a mask as a pattern Light is projected on silicon wafer through the mask to transfer the pattern on the die Various electrical/chemical processes are used to convert these patterns into desired features Series of masks are used to form transistors and interconnects The process of forming features on silicon using light is called Photolithography ASIC Package (contd.) BGA: (Ball Grid Array) Relatively expensive, very high density Very good thermal/electrical characteristics, Very common in ASIC MCM: Multi Chip Module, a type of BGA where several die s are housed in the same package. Very good characteristics, very high density, very high speed, Very expensive, modern technology FlipChip BGA: A more sophisticated form of BGA which allows even greater pin density. New technology, expensive. With time, all high ASIC s will move to such packages ASIC Fabrication Process (Contd.) Each layer is made using its associated mask Transistors are formed using series of layers of Metal3 Via2 Metal2 Via1 Metal1 Polygate, P-Diffusion, N- Contact Diffusion. Polysilicon Gate Interconnects are formed using another series of layers Many ASIC s can be layed out Gate oxide N Diffusion P Diffusion Silicon Wafer Introduction to Hardware Description Language (HDL)

5 Recommed reading Wikipedia The Free On-line Encyclopedia VHDL - Verilog - ped / e og Verilog-II Verilog allows the designer to simulate and verify the design at each level EDA (electronic design automation) tools help the designer to move from higher to lower levels of abstraction Behavioral synthesis tools create dataflow descriptions from a behavioral description Logic synthesis tools convert an RTL description to a switch level interconnection of transistors, which is input to an automatic place and route tool that creates the chip layout With Verilog and EDA tools one could sit at a computer at home, design a complex chip, the design to a silicon foundry in California, and receive the fabricated chip through regular mail in a few weeks! The Verilog environment is that of a programming language. Designers, particularly with C programming experience, find it easy to learn and work with 28 What is HDL In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. The two most widely-used and well-supported HDL varieties used in industry are: VHDL (VHSIC hardware description language) Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction. VHDL vs. Verilog Government Developed Ada based Strongly Type Cast Case-insensitive Difficult to learn More Powerful Commercially Developed C based Mildly Type Cast Case-sensitive Easier to Learn Less Powerful 26 Structural Level Verilog-I Verilog is a hardware description language (HDL) Verilog is used by several companies in the commercial chip design and manufacturing sector today. It is rapidly overtaking the rival HDL called VHDL Verilog allows a designer to develop a complex hardware system, e.g., a VLSI chip containing millions of transistors, by defining it at various levels of abstraction at the (highest) behavioral, or algorithmic, level the design consists of C- like procedures that express functionality without regard to implementation at the dataflow level the design consist of specifying how data is processed and moved between registers at the gate level the structure is defined as an interconnection of logic gates at the (lowest) switch level the structure is an interconnection of transistors Learning Verilog Verilog is essentially a programming language similar to C with some Pascal-like constructs The best way to learn any programming language is from live code We will get you started by going through several example programs and explaining the key concepts We will not try to teach you the syntax line-by-line: pick up what you need from the books and on-line tutorials Tip: Start by copying existing programs and modifying them incrementally making sure you understand the output behavior at each step Tip: The best way to understand and remember a construct or keyword is to experiment with it in code, not by reading about it We shall not design at the switch (transistor) level in this course the lowest level we shall reach is the gate level. The transistor level is more appropriate for an electronics-oriented course

6 How to learn Verilog by yourself? Modules Modules are basic building blocks of Verilog Description of the logic being modeled is placed inside modules Module definition starts with keyword module Ends with the keyword Modules declarations cannot be nested Modules are: Declared Instantiated 34 Simulation and Synthesis Modules and Primitives Styles Structural Descriptions Language Conventions Overview Data Types Delay Behavioral Constructs Compiler Directives Simulation and Testbenches Module Example module hello; initial $display( Welcome to the MSEE Class! ); $display( Good luck to all Participants ); $finish; Simulation and Synthesis Simulation tools typically accept full set of Verilog language constructs Some language constructs and their use in a Verilog description make simulation efficient i and are ignored by synthesis tools Synthesis tools typically accept only a subset of the full Verilog language constructs In this lecture, Verilog language constructs not supported in Xilinx ISE are in red italics Module Ports Modules communicate with the outside world through ports Module port are similar to pins in hardware For Example: module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; clk) q = d; qn = ~d;

7 Port Types Inputs Inputs are values being provided to the module Outputs Outputs are values being driven by the module Inouts Ports that act as input and output ports Module Instances Modules can be instantiated within other modules to create a hierarchy module top; reg data_in, clock; wire data_out, data_outb; dff D_flipflop(data_out, data_outb, data_in, clock);.... data_in data_out Top 37 clock data_outb 40 Module Declaration Annotated Example /* module_keyword module_identifier (list of ports) */ module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declaration input E_n ; // input_declaration output [3:0] D ; // output_declaration assign D = {4{~E_n}} & ((A == 2'b00)? 4'b0001 : (A == 2'b01)? 4'b0010 : (A == 2'b10)? 4'b0100 : (A == 2'b11)? 4'b1000 : 4'bxxxx) ; // continuous_assign 38 Example Module Instantiation module C_4_16_decoder_with_enable (A, E_n, D) ; input [3:0] A ; input E_n ; output [15:0] D ; wire [3:0] S; wire [3:0] S_n; C_2_4_decoder_with_enable DE (A[3:2], E_n, S); C_2_4_decoder_with_enable D0 (A[1:0], S_n[0], D[3:0]); C_2_4_decoder_with_enable D1 (A[1:0], S_n[1], D[7:4]); C_2_4_decoder_with_enable D2 (A[1:0], S_n[2], D[11:8]); C_2_4_decoder_with_enable D3 (A[1:0], S_n[3], D[15:12]); 41 Module Declaration Primitives Identifiers - must not be keywords! Ports First example of signals Scalar: e. g., E_n Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3] Range is MSB to LSB Can refer to partial ranges - D[2:1] Type: defined by keywords input output inout (bi-directional) 39 Gate Level and, nand or, nor xor, xnor buf, not bufif0, bufif1, notif0, notif1 (three-state) Switch Level *mos where * is n, p, c, rn, rp, rc; pullup, pulldown; *tran + where * is (null), r and + (null), if0, if1 with both * and + not (null) 42 7

8 Primitives No declaration; can only be instantiated and(out, in1,in2) All output ports appear in list before any input ports Optional drive strength, delay, name of instance Example: and N25 (Z, A, B, C); //instance name and #10 (Z, A, B, X); // delay (X, C, D, E); //delay /*Usually better to provide instance name for debugging.*/ or N30 (SET, Q1, AB, N5), N41 (N25, ABC, R1); and #10 N33(Z, A, B, X); // name + delay 43 Style Example - RTL/Dataflow module fa_rtl (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; assign S = A ^ B ^ CI; //continuous assignment assign CO = A & B A & CI B & CI; //continuous assignment 46 Styles Structural - instantiation of primitives and modules RTL/Dataflow - continuous assignments Behavioral -procedural assignments 44 Style Example - Behavioral module fa_bhv (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; reg S, CO; // required to hold values between events. always@(a or B or CI) //; S <= A ^ B ^ CI; // procedural assignment CO <= A & B A & CI B & CI; // procedural assignment 47 Style Example - Structural Blocks module full_add (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; wire N1, N2, N3; half_add HA1 (A, B, N1, N2), HA2 (N1, CI, S, N3); or P1 (CO, N3, N2); module half_add (X, Y, S, C); input X, Y ; output S, C ; xor (S, X, Y) ; and (C, X, Y) ; Concurrent Blocks Blocks of code that seem to execute in the same point in time

9 Types Procedural initial always Concurrent Blocks Continuous assignments assign Always Block Definition Executes every time a specified event occurs e.g clock edge Syntax (sensitivity list / event) Example module ANDgate; wire a, b; (a or b) out = a & b; Procedural blocks Two Types initial: executes only once at time zero always: block is active throughout the simulation Within each block, all statements executed sequentially Continuous Assignments Continuous assignments Single statement which executes continuously and does not wait for any event to occur Syntax assign a = b + c; initial always Definition Executes once at time zero Example Initial Block module test; reg a, b; wire out; 2inputAND (out, a, b); // AND gate instance initial a = 0; b = 0; Concurrent Execution All procedural blocks execute concurrently Allows you to model the inherent concurrency in hardware All procedural blocks are activated at time 0, waiting to be executed upon specified conditions initial always assign

10 Signal Values and Resolution 0 Zero, Low, False, Logic low, Ground, VSS, Negative Assertion 1 One, High, True, Logic High, Power, VDD, VCC, Positive Assertion x Unknown: Occurs at Logical Conflict which cannot be resolved z Hi-Z: High Impedance, Tri-stated, Disabled Driver 56 Data Types in Verilog Wire Connect modules or primitives in a design Can t retain their value Registers Can hold their value Integers 32 bit signed numbers 59 Sensitivity List Signals or events that trigger the execution of a statement or a block of statements Constantly monitored by the simulator Al large sensitivity list tdegrades d simulation performance (posedge clock or reset) Data Types in Verilog: Wire Wire: Connects modules or primitives Wires can t store their values, must be driven Wire can be one bit wide or more than one bit wide (vector) Examples, wire a; wire x, y, z; // declares a as a wire // declares x, y, z as three wires wire [7:0] b, c, d; // declares b, c, d as three 8-bit vector wires default data type in Verilog module ports are implicitly defined as wire by Verilog Format Numbers in Verilog number of bits radix value Number of bits Radix Value Number of bits and radix are optional Default no. of bits = 32, default radix = decimal Letter used for radix b binary, d decimal, o octal, h hexadecimal. Case insensitive. iti White spaces OK, except between and radix Examples, 8 b // 8-bit binary number (165) 16 habcd // 16-bit hex number (abcd) b 101 // 32-bit binary number (5) 1 bz // 1 bit binary number (z) 1 b x // 1 bit binary number (x) 1 b 1 // Illegal 8 b101xx101 // 8-bit binary number Data Types in Verilog: Wire Wire (example 1): c is explicitly defined as a wire three other wires in this module, y, a, b, are also port modules y, a, b are implicitly defined as wires a b U1 c U2 y module nand_gate (y, a, b); input a, b; output y; wire c; and2_gate U1 (c, a, b); not_gate U2 (y, c); 58 module nand_gate 61 10

11 Data Types in Verilog : Reg Registers: Registers (unlike wires) can store values Registers can be one bit, or more than one bit (vectors) Driven Outputs need to be of type reg Examples, reg a; // declares a as a register reg x, y; // defines x and y as two registers reg [4:0] b; // declares b as a 5-bit (vector) register 62 Data Types in Verilog (contd.) Integer: examples. integer j, k, l; // declares j, k, l as three integer j = 32 d5; // assigns 5 to j k = 32 b110; l = -32 d5; // assigns 6 to k // assigns -5 to l (2 s complement) Data Types in Verilog (contd.) Registers (example): The output port q is defined as a one bit register q is assigned the value of input d at the positive edge of the input clk Difference between scalar and a vector Scalar: reg a, b; Vector: reg [4:0] A, B; module dff(q, d, clk); input q, clk; d q d-val x d-val output q; reg q; clk (posedge clk) q = d; Data Types in Verilog (contd.) Integers: Integers are 32 bit wide in Verilog Integers are signed numbers example, integer j, k, l; // declares three integers Keyword integer, NOT int Main difference between integer and reg is, integer is signed, reg is unsigned Integers cannot have bit-selects ie. J [4:0] Integers are not recommed for synthesis Strings No explicit data type Must be stored in reg whose size is 8*(num. of characters) reg [255:0] buffer; //stores 32 characters

12 Constants (Paramters) Declaration of parameters parameter A = 2 b00, B = 2 b01, C = 2 b10; parameter regsize = 8; reg [regsize - 1:0]; /* illustrates use of parameter regsize */ Logical Operator Logical operators (&&, ) produce a scalar value (0, 1, or X). module logical_block; initial $display (2 b00 && 2 b10); // 0 $display (2 b01 && 2 b10); // 1 $display (2 b00 2 b00); // 0 $display (2 b01 2 b00); // 1 $display (2 b00 && 2 b1x); // x $display (2 b1z && 2 b10); // x Operators in Verilog Shift Logical Conditional Negation Relational Replication Concatenation Equality Unary Reduction Bit-wise Conditional Operator The conditional operator (?:) Also called ternary operator, Must have 3 operands. It selects from two operands, based on a third. Syntax: <conditional expression>? <true_expression> : <false_expression> It can be thought of as if-else statement. if (conditional_expression) LHS = true_expression; else LHS = false_expression; An unknown conditional expression can still produce a known value if all possible selections are identical Shift operator The left shift operator (<<) shifts the left operand left by the number of bit positions specified by the right operand. The right shift operator (>>) shifts the left operand right by the number of bit positions specified by the right operand. module shift; initial $display (8 b << 2); // $display (8 b >> 3); // Conditional operator Example 1 module tristate (O, I, E); output O; input I, E; assign O = E? I : 1 bz; Example 2 module mux41 (O,S,A,B,C,D); output O; input A, B, C, D; input [1:0] S; assign O = (S == 2 d0)? A : (S == 2 d1)? B : (S == 2 d2)? C : D;

13 Lab 2: Ternary Operator Objective: Write a module for a 8 to 1 mux. Specification: module 8to1(in0,in1,in2,in3,in4,in5,in6,in7,select, out) ; input [2:0] select; input in0,in1,in2,in3,in4,in5,in6,in7; output out; Operators: Concatenation Concatenation operator Allows you to select bits from different vectors to join then into a new vector. {} concatenation Example new_vector[8:0] = {rega[4:2],regb[1:2],1 b0,regc[3:0]}; Other Operators Negation operator: (!) logical (~) bitwise Reduces an operand to its logical inverse. $display (!4 b0100 ); // 0 $display (!4 b0000 ); // 1 $display (~4 b01xx ); //10xx Other operators Logical equality(==) operator Evaluates to be true if LHS is equal to the RHS. Logical equality(==) operator evaluates to be unknown (X) if either LHS or RHS have an x Operation is inverse for the inequality (!=) operator. $display ( 4 b0011 == 4 b1010 ) ; // 0 $display ( 4 b0011!= 4 b1x10 ) ; // x Relational Operators Less than (<), Less than or equal to (<=), Greater than or equal to (>=), Greater than (>). if (A >= 2 b11) then B = 1 b1; 75 Case equality (===) Case inequality (!==) operators are the same as the logical equality except that they perform definitive match of bit positions that are Z or X. Example valid = (A == 2 b11)?1: 0; 78 Operators: Replication Bit-Wise Operators Replication operator Replicates an expression a fixed number of times to form a new vector quantity. ({n{}}) Example rega = 2 b11; bus = {4{regA}}; // bus = Bit-wise operators perform bit-wise manipulations on two operands (vectors) They compare each bit in one operand with its corresponding bit in the other operand to calculate each bit of the result Example: ~ not & and or ^ xor ~^ / ^~ xnor rega 4 b1001; regb 4 b1010; regc 4 b11x0; rega & 0; //0000 rega & regb; //1000 rega regb; //1011 regb & regc; //10x0 regb regc; //

14 Unary Reduction Operator Unary reduction operators operate on all bits of a single operand(vector) to produce a single-bit result (scalar) ~ not & and or ^ xor ~^/ ^~ xnor rega 4 b0100; regb 4 b1111; &rega ; //0 rega ; //1 ^regb ; //0 ~ rega ; //0 (nor) ~&rega ; //1 (nand) 80 Expressions with Operands Containing x or z Arithmetic If any bit is x or z, result is all x s. Divide by 0 produces all x s. Relational If any bit is x or z, result is x. Logical == and!= If any bit is x or z, result is x. === and!== All bits including x and z values must match for equality 83 Review The difference between Scalar value and Vector value The difference between ~ and! The difference between & and && 81 Expressions with Operands Containing x or z Bitwise Defined by tables for 0, 1, x, z operands. Reduction Defined by tables as for bitwise operators. Shifts z changed to x. Vacated positions zero filled. Conditional If conditional expression is ambiguous (e.g., x or z), both expressions are evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x. 84 Operator precedence Type of Operator Symbols Concatenate & replicate {} {{ }} Unary! ~ & ^ ^~ Arithmetic * / % + - Logical shift << >> Relational < <= > >= Equality ==!= ===!== Binary bit-wise & ^ ^~ Binary logical && Conditional? : Simulation Time Scales Compiler Directive `timescale <time_unit> / <time_precision> time_unit - the time multiplier for time values time_precision - minimum step size during simulation - determines rounding of numerical values Allowed unit/precision values: { , s ms us ns ps} 85 14

15 Simulation Time Scales (continued) `timescale 10ps / 1ps nor #3.57 (z, x1, x2); nor delay used = 3.57 x 10 ps = 35.7 ps => 36 ps Different timescales can be used for different sequences of modules The smallest time precision determines the precision of the simulation. Blocking Assignments - Inter- Assignment Delay Delays evaluation of RHS and assignment to LHS clk) b = 0; c = 0; b = a + a; // uses a at posedge clock #5 c = b + a; // uses a at posedge clock + 5 d = c + a; // uses a at posedge clock + 5 /*c = 2 a(at posedge clock)+ a(at posedge clock + 5) d = 2 a(at posedge clock) + 2 a(at posedge clock + 5)*/ Blocking Assignments Identified by = Sequence of blocking assignments executes sequentially clk) b = 0; c = 0; b = a + a; c = b + a; d = c + a; 87 Blocking Assignment - Intra- Assignment Delay Delays assignment to LHS and subsequent statements, not evaluation of RHS Example: clk) b = 0; c = 0; b = a + a; // uses a at posedge clock c = #5 b + a; // uses a at posedge clock d = c + a; // uses a at posedge clock + 5 /* c = 3 a(at posedge clock) d = 3a (at posedge clock)+ a (at posedge clock + 5)*/ 90 Non-Blocking Assignments Identified by <= Sequence of non-blocking assignments executes concurrently Example 1: clk) b <= 0; c <= 0; b <= a + a; c <= b + a; d <= c + a; /*Calculates b = 2a, c = b + a, d <= c + a. All values used on RHS are those at posedge clock. Note that there are two assignments to b and c. Only the last one is effective. */ 88 Non-Blocking Assignment - Inter-Assignment Delay Delays evaluation of RHS and assignment to LHS Delays subsequent statements clk) b <= 0; c <= 0; b <= a + a; // uses a at posedge clock #5 c <= b + a; // uses b and a at posedge clock + 5 d <= c + a; // uses a at posedge clock + 5 /*c = b(at posedge clock + 5) + a(at posedge clock + 5) posedge clock + 5) + a (at posedge clock +5) */ d = c(at 91 15

16 Non-Blocking Assignment - Intra-Assignment Delay Delays only assignment to LHS Lab 3: If-else Objective: Use if-else construct to compare two 8-bit inputs a and b. There are three one bit outputs g(reater), l(ess), e(qual) Condition g l e clk) b <= 0; c <= 0; b <= a + a; // uses a at posedge clock c <= #5 b + a; // uses a and b at posedge clock d <= c + a; // uses a and c at posedge clock /* Calculates *c(posedge clock + 5) = b(at posedge clock) + a(at posedge clock); d(posedge clock) = c(at posedge clock) + a (at posedge clock) */ 92 a>b a<b a=b None of the above a[7:0] b[7:0] a>b a<b a=b g l e 95 Control Constructs in Verilog We will cover four control constructs in Verilog: 1. if-else 2. case 3. while 4. for 93 Control constructs (case) Structure: case (condition) value1: procedural_block1 value2: procedural_block2.. valuen: procedural_blockn default: procedural_block case Condition can be an expression or just a value A procedural block matching the value of the expression is executed Default statement is executed if there are no matches Unlike C, no break! module mux4a (y, a, b, c, d sel); input a, b,c, d; input [2:0] sel; output y; reg y; or b or c or d or sel) case (sel) 3 b000 : y = a; 3 b001 : y = b; 3 b010 : y = c; 3 b011 : y = d; default : y = 1 bx; case a b c d sel[2:0] module mux4a y 96 Control constructs (if-else) Structure: if (condition) procedural_block1 else procedural_block2 Condition can be an expression or just a value - a 0 or unknown is FALSE, 1 or more is TRUE No then or if in Verilog! If nested if s are used, else belongs to immediately preceding if a b sel module mux y module mux (y, a, b, sel); input a, b, sel; output y; reg y; (a or b or sel) if (sel) y = a; else y = b; 94 Control constructs (casez, casex) case statement matches x with x and z with z to be true case does not allow wild character (?) In casez,? or z will match to any value, i.e. use? or z for don t cares In casex,? Is not supported. Use x or z to indicate don t cares Value case casez casex x x x 0 1 x z z z 0 1 x z 0 1 x z? unused 0 1 x z unused Summary of Case Values and Match per Case Type module counta(clk, rst, ld, up, din, dout); input clk, rst, ld, up; input [15:0] din; output [15:0] dout; reg [15:0] dout; clk) casez ({rst, ld, up}) 3 b1zz : dout = 8 b0; 3 b01? : dout = din; 3 b001 : dout = dout + 1; 3 b000 : dout = dout - 1; default : dout = 8 bx; case 97 16

17 Lab 4: Case Objective: Use case construct to create an 8-bit counter with a two bit control input c, 8-bit data input din, 8-bit data output dout. All operations are synchronous w.r.t +ve edge clock clk. c[1:0] dout(n+1) Comment 00 din Load data 01 dout(n)+1 Increment by 1 10 dout(n)-1 Decrement by Reset Control constructs (while loop) Structure: while (condition) procedural_block1 Condition is evaluated, if TRUE the loop is entered While loop is executed as long as condition remains TRUE Not Synthesizable count=1 count=2 count= Read next number at posedge clock /* counts the number of leading zero s in 16 bit input */ module zerocount (count, datain, clk); input clk; input [15:0] datain; output [4:0] count; reg [4:0] count; reg [15:0] din_reg; din[7:0] c[1:0] clk dout[7:0] 98 clk) count = 0; din_reg = datain; while ((din_reg[15]==0) && (count < 16)) count = count+1; din_reg = din_reg << 1; // while // always 101 Control constructs (for loop) Structure: for (expr1; expr2; expr3) procedural_block1 expr1 is initialization expression which is executed when the loop is entered the first time expr2 is the condition which is evaluated and if TRUE the for loop is entered (or re-entered) expr3 is the increment which is performed after the loop is executed The three expression don t need to refer to the same reg or variable // add the 5 LSB s of 16 bit input module counter (sum, datain, clk); input clk; input [15:0] datain; output [2:0] sum; reg [2:0] sum, i; (posedge clk) for (i=0; i<5; i = i+1) sum = sum + datain[i]; 99 Lab 6 : while loop Objective: Use while loop to design a circuit which divides a 16-bit input din by 3. The 15-bit output result holds the result of the division, and 2-bit output remainder the remainder. Hint: Use successive subtractions to get the result and the remainder. You can assume that t din is always a positive number. din[15:0] result[14:0] remainder[1:0] 102 Lab 5: for loop Testbench Approach Objective: Use a for loop to detect number of times 010 pattern is found in a 32-bit input din. The patterns can overlap each other, ex counts as two patterns. The 4-bit output is named count Use Verilog module to produce testing environment including stimulus generation and/or response monitoring din[31:0] count[3:0] Stimulus UUT Module Response Testbench Module

18 References 1. IEEE, IEEE Standard Description Language Based on the Verilog(TM) Hardware Description Language. 2. Synopsys, FPGA Compiler II/FPGA Express: Verilog HDL Reference Manual, Version , May Thomas, D. E., and P. R. Moorby, The Verilog Hardware Description Language, 4th Ed., Kluwer Academic Publishers, Smith, D. R., and P. D. Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall, Ciletti, Michael D., Modeling, Synthesis, and Rapid Prototyping with the Verilog DHL, Prentice Hall, Palnitkar, Samir, Verilog HDL: A Guide to Design and Synthesis, Sunsoft Press,